From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by sourceware.org (Postfix) with ESMTPS id BC5733858000 for ; Tue, 15 Nov 2022 03:13:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BC5733858000 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-lj1-x22c.google.com with SMTP id b9so15874305ljr.5 for ; Mon, 14 Nov 2022 19:13:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=88JX4VnIpmPRZsFbYK4wir88gDmNd762sjeGOh/mRL4=; b=EdyxCLTIzlHl+SlAxu0uDpFwDVwZwen9deK9qI8Yj2uXYhvFf4+BaDxV80ElY+bFXc ToU+Zox8Lrk0wAGqPnEWr3rkmS59E9nBiPPLMXji7/pWABA+kt1PuPZp9sFuonoO2fWo UxlNIqpNvBtbnnC1qLymuDIoN7mMJREM7zp4OEoL1twtBLXADrJF3nGPbLPKL3nrFVCP wXYwLTWx8sQNpZDNcYSvBjHPJcWFFbx5s7AeWaCngQ1ighKTVD1XBd6YTeYrMR42aw4z GvrINHCh7g1NchRwM//CLrPyTZ1AwQVAzGZKPVSrSZSF5/0NpPYwIiHZb2Vnd4pX7FYo jPtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=88JX4VnIpmPRZsFbYK4wir88gDmNd762sjeGOh/mRL4=; b=MLwcIMlylS6PN/ExVtkHx79WTWomDS8CBsIuWtrXTgav47icF7gqjViykBZ2qFpnZ1 WcomahTwixdNoKgpgECWT/de8OgJWqB25+WP35YGO11zlwFmtBdAKeFtUx84uF/lqF3f YOPM6kUJQ3V4RGm6nsoqf9+AzWcZMY5J+M8ZyNYeSkgXno4PNUwoANL1FtLKQvrnY78+ 9I2vDcDKZGSl5BargfvtVXIgDpq+4B0Rdk27RDSklAdDrdgOsbqABXJrZv/3Rlm4rofE WfBOyjwnWkfytuxHxQC2dEbqd8Y/wSckhSM6hpHpuTSGxobS9C035+M///+r1MMtWpsb t59g== X-Gm-Message-State: ANoB5pm5gEBEfGlFKpSinHmHUFkrIs46uVCETK5QHf5GxTqG6pErP6g7 i5kVdSurFzo9TAVnMxbwr4XCv1fQOSd99c9lHaFj+w== X-Google-Smtp-Source: AA0mqf56CR6KHV4huq2NJclqFIREmbQ/3uAp898Wy33agueHRN4GZUmzT2MV3H3Nr6EsWU29P7HBkwnxxCQGD0WYJ6Y= X-Received: by 2002:a2e:a5c8:0:b0:26d:d55f:f1cf with SMTP id n8-20020a2ea5c8000000b0026dd55ff1cfmr4819451ljp.175.1668481995013; Mon, 14 Nov 2022 19:13:15 -0800 (PST) MIME-Version: 1.0 References: <20221114162918.1563116-1-jiawei@iscas.ac.cn> <4daf8bdf.263a4.18479264c94.Coremail.jiawei@iscas.ac.cn> In-Reply-To: From: Kito Cheng Date: Mon, 14 Nov 2022 19:13:02 -0800 Message-ID: Subject: Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic. To: "juzhe.zhong" Cc: jiawei , "kito.cheng" , gcc-patches , palmer , "christoph.muellner" , "philipp.tomsich" , wuwei2016 Content-Type: multipart/alternative; boundary="000000000000a0949105ed79bc7d" X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000a0949105ed79bc7d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable I would suggest add a sperated case and scan-assembly-not to demonstrate this patch. juzhe.zhong@rivai.ai =E6=96=BC 2022=E5=B9=B411=E6=9C= =8815=E6=97=A5 =E9=80=B1=E4=BA=8C 10:47 =E5=AF=AB=E9=81=93=EF=BC=9A > I think you'd better change assembler checking of "spill-*.c" cases. > Check they don't have "addi sp,sp,0" redundant instruction. > Let's see whether Kito aggree with that. > ------------------------------ > juzhe.zhong@rivai.ai > > > *From:* jiawei > *Date:* 2022-11-15 10:37 > *To:* Kito Cheng > *CC:* gcc-patches ; kito.cheng > ; palmer ; juzhe.zhong > ; christoph.muellner ; > philipp.tomsich ; wuwei2016 > > *Subject:* Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic. > > -----=E5=8E=9F=E5=A7=8B=E9=82=AE=E4=BB=B6----- > > =E5=8F=91=E4=BB=B6=E4=BA=BA: "Kito Cheng" > > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2022-11-15 09:48:26 (=E6=98=9F= =E6=9C=9F=E4=BA=8C) > > =E6=94=B6=E4=BB=B6=E4=BA=BA: jiawei > > =E6=8A=84=E9=80=81: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, > palmer@rivosinc.com, juzhe.zhong@rivai.ai, christoph.muellner@vrull.eu, > philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn > > =E4=B8=BB=E9=A2=98: Re: [PATCH] RISC-V: Optimal RVV epilogue logic. > > > > Could you provide some testcase? > > Sorry for not giving a clear description=EF=BC=8C > > You can use amost all testcases in gcc.target/riscv/rvv/base/spill-*.c > > compile with -march=3Drv64gcv and check the assemble file spill-*.s, > > before this patch, it will generate assemble code contain additional > > `addi sp,sp,0`: > > ``` > csrr t0,vlenb > slli t1,t0,1 > add sp,sp,t1 > addi sp,sp,0 > ld s0,24(sp) > addi sp,sp,32 > jr ra > ``` > > after this patch it will removed: > > ``` > csrr t0,vlenb > slli t1,t0,1 > add sp,sp,t1 > ld s0,24(sp) > addi sp,sp,32 > jr ra > ``` > > > > > On Tue, Nov 15, 2022 at 12:29 AM jiawei wrote: > > > > > > Skip add insn generate if the adjust size equal to zero. > > > > > > gcc/ChangeLog: > > > > > > * config/riscv/riscv.cc (riscv_expand_epilogue): > > > New if control segement. > > > > > > --- > > > gcc/config/riscv/riscv.cc | 18 ++++++++++-------- > > > 1 file changed, 10 insertions(+), 8 deletions(-) > > > > > > diff --git a/gcc/config/riscv/riscv.cc > b/gcc/config/riscv/riscv.cc > > > index 02a01ca0b7c..af138db7545 100644 > > > --- a/gcc/config/riscv/riscv.cc > > > +++ b/gcc/config/riscv/riscv.cc > > > @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style) > > > } > > > > > > /* Get an rtx for STEP1 that we can add to BASE. */ > > > - rtx adjust =3D GEN_INT (step1.to_constant ()); > > > - if (!SMALL_OPERAND (step1.to_constant ())) > > > + if (step1.to_constant () !=3D 0){ > > > + rtx adjust =3D GEN_INT (step1.to_constant ()); > > > + if (!SMALL_OPERAND (step1.to_constant ())) > > > { > > > riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); > > > adjust =3D RISCV_PROLOGUE_TEMP (Pmode); > > > } > > > > > > - insn =3D emit_insn ( > > > + insn =3D emit_insn ( > > > gen_add3_insn (stack_pointer_rtx, > stack_pointer_rtx, adjust)); > > > > > > - rtx dwarf =3D NULL_RTX; > > > - rtx cfa_adjust_rtx =3D gen_rtx_PLUS (Pmode, > stack_pointer_rtx, > > > + rtx dwarf =3D NULL_RTX; > > > + rtx cfa_adjust_rtx =3D gen_rtx_PLUS (Pmode, > stack_pointer_rtx, > > > GEN_INT (step2)); > > > > > > - dwarf =3D alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rt= x, > dwarf); > > > - RTX_FRAME_RELATED_P (insn) =3D 1; > > > + dwarf =3D alloc_reg_note (REG_CFA_DEF_CFA, > cfa_adjust_rtx, dwarf); > > > + RTX_FRAME_RELATED_P (insn) =3D 1; > > > > > > - REG_NOTES (insn) =3D dwarf; > > > + REG_NOTES (insn) =3D dwarf; > > > + } > > > } > > > else if (frame_pointer_needed) > > > { > > > -- > > > 2.25.1 > > > > > > --000000000000a0949105ed79bc7d--