Re: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]

[Kito Cheng <kito.cheng@sifive.com>]

On Wed, Nov 8, 2023 at 2:37 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> Another question raise to me.
>
> Is it necessary we have such many variant of vsetvls?
>
> I am thinking about redesign:
>
> __riscv_vsetvl_e8mf8
> __riscv_vsetvl_e16mf4
> __riscv_vsetvl_e32mf2
> __riscv_vsetvl_e64m1
>
> They are quite redundant. They have the same result.
>
> May be just design as :
>
> __riscv_vsetvl_ratio64
>
> I am no proposing it since it has been used for a long time. Just raise my concern.

Yeah, I agree those variant are just having same behavior even
semantic on the current intrinsic model, one reason is we don't have
smart vsetvli insertion pass at design stage, also it's more obviously
to user to pick the right vsetvli intrinsic, however I intend not to
change that interface, the reason is simple, it's used for a long time
as you mentioned, change that would be huge disturbance.

There may have same argument for vbool* stuffs, but vbool* kind of
mixing historical reason* and also we didn't found better way to model
that.

* We have define MLEN is v-spec long times ago, I forgot it's 0.7 or 0.8..