From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by sourceware.org (Postfix) with ESMTPS id 9B8C03B91DC6 for ; Mon, 19 Dec 2022 06:30:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9B8C03B91DC6 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-lf1-x12f.google.com with SMTP id y25so12183165lfa.9 for ; Sun, 18 Dec 2022 22:30:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=fAL86+9EeVj5jNBXVZyOqsyWfSWLlH3jSjmabzI3PIE=; b=TaMsrpmB4tbAwZSybmO8qXhh9MHXnibXKlgyrOdHFJDpojxpnhlF1zIrMyq678HVP5 G+4rdTzc8taqtXEQ4cbFD4j6fMV7hocP+lqqzkn5LWwf7GR/VDcCq8oZUe5Ngb4qY8OO YCfCp7VSR2AlnhkNKdY2MA2AtCSGfiiU/haws7tU7BG9uvV2KnJMQxnYYq/L91uw+3WL uxpigaYeEfKXxSeEXedZRoC2f0Ww1S42QTPTDxfgrRyhKq1+hbN8HK9mAQbhohBiSYYz Bivx/pOhwGGwXasCDDYSd+G+1Ks8Z7gHgejVjyOLxEZVyEq3ou1i+w51CnqJZOe5SXuU vGVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fAL86+9EeVj5jNBXVZyOqsyWfSWLlH3jSjmabzI3PIE=; b=t5E6yoIplXGuiCZAV2+Map7wfUu4sadq7Mnu29DfUFKdJ6dJpHb7jJO97yGjygl9V1 Iy3QlDJuESgmwmaS4IDfMc+o4/Eh8+AmxKkdVyVCF1nGf8QMfR9lfOiNqSvMFXmbycrj qeBf4INy5Ak49cBi2+Grtjdndk1lqG/L4CjSEDf4+EBVrQp3tBZALwbdwTwZ2DfZfnLU kKd8G8ViG5C2/ID6aCbePbpCTsAQqBC3KMrLeDzsbhmPTDtVt8KKZdHGMI1MIZZD1RZb SeyfjW4aVYbEcrBcM3QwBURbx9dJzt5yGqlfJ0+9FYGALjwVyRgvwEzxm0IF23Eme3ec 0owA== X-Gm-Message-State: ANoB5pkOETSZvFPs6FSYBb5FWILAzcXC1yLFZyCjveeMks/0lSvC+BsG 2Lk+Mp0JmI1+eIlC3/AvKjFAnjCyRhCuqEt7zH5qug== X-Google-Smtp-Source: AA0mqf5BUtGoQc0OlVjxFGdnq5TZkEiHozsIs7rCbghoikVVq0KDeaSZ2CgJwzg/hYZPZ3T8ihrZuYARJBYavawHHy8= X-Received: by 2002:ac2:5545:0:b0:4b5:c489:8cf7 with SMTP id l5-20020ac25545000000b004b5c4898cf7mr1943473lfk.242.1671431434991; Sun, 18 Dec 2022 22:30:34 -0800 (PST) MIME-Version: 1.0 References: <20221219010838.3878675-1-christoph.muellner@vrull.eu> <20221219010838.3878675-3-christoph.muellner@vrull.eu> In-Reply-To: <20221219010838.3878675-3-christoph.muellner@vrull.eu> From: Kito Cheng Date: Mon, 19 Dec 2022 14:30:23 +0800 Message-ID: Subject: Re: [PATCH v2 02/11] riscv: Restructure callee-saved register save/restore code To: Christoph Muellner Cc: gcc-patches@gcc.gnu.org, Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: just one more nit: Use INVALID_REGNUM as sentinel value for riscv_next_saved_reg, otherwise LGTM, and feel free to commit that separately :) On Mon, Dec 19, 2022 at 9:08 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch restructures the loop over the GP registers > which saves/restores then as part of the prologue/epilogue. > No functional change is intended by this patch, but it > offers the possibility to use load-pair/store-pair instructions. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_next_saved_reg): New function. > (riscv_is_eh_return_data_register): New function. > (riscv_for_each_saved_reg): Restructure loop. > > Signed-off-by: Christoph M=C3=BCllner > --- > gcc/config/riscv/riscv.cc | 94 +++++++++++++++++++++++++++------------ > 1 file changed, 66 insertions(+), 28 deletions(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 6dd2ab2d11e..a8d5e1dac7f 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -4835,6 +4835,49 @@ riscv_save_restore_reg (machine_mode mode, int reg= no, > fn (gen_rtx_REG (mode, regno), mem); > } > > +/* Return the next register up from REGNO up to LIMIT for the callee > + to save or restore. OFFSET will be adjusted accordingly. > + If INC is set, then REGNO will be incremented first. */ > + > +static unsigned int > +riscv_next_saved_reg (unsigned int regno, unsigned int limit, > + HOST_WIDE_INT *offset, bool inc =3D true) > +{ > + if (inc) > + regno++; > + > + while (regno <=3D limit) > + { > + if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) > + { > + *offset =3D *offset - UNITS_PER_WORD; > + break; > + } > + > + regno++; > + } > + return regno; > +} > + > +/* Return TRUE if provided REGNO is eh return data register. */ > + > +static bool > +riscv_is_eh_return_data_register (unsigned int regno) > +{ > + unsigned int i, regnum; > + > + if (!crtl->calls_eh_return) > + return false; > + > + for (i =3D 0; (regnum =3D EH_RETURN_DATA_REGNO (i)) !=3D INVALID_REGNU= M; i++) > + if (regno =3D=3D regnum) > + { > + return true; > + } > + > + return false; > +} > + > /* Call FN for each register that is saved by the current function. > SP_OFFSET is the offset of the current stack pointer from the start > of the frame. */ > @@ -4844,36 +4887,31 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, r= iscv_save_restore_fn fn, > bool epilogue, bool maybe_eh_return) > { > HOST_WIDE_INT offset; > + unsigned int regno; > + unsigned int start =3D GP_REG_FIRST; > + unsigned int limit =3D GP_REG_LAST; > > /* Save the link register and s-registers. */ > - offset =3D (cfun->machine->frame.gp_sp_offset - sp_offset).to_constant= (); > - for (unsigned int regno =3D GP_REG_FIRST; regno <=3D GP_REG_LAST; regn= o++) > - if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) > - { > - bool handle_reg =3D !cfun->machine->reg_is_wrapped_separately[reg= no]; > - > - /* If this is a normal return in a function that calls the eh_ret= urn > - builtin, then do not restore the eh return data registers as t= hat > - would clobber the return value. But we do still need to save = them > - in the prologue, and restore them for an exception return, so = we > - need special handling here. */ > - if (epilogue && !maybe_eh_return && crtl->calls_eh_return) > - { > - unsigned int i, regnum; > - > - for (i =3D 0; (regnum =3D EH_RETURN_DATA_REGNO (i)) !=3D INVA= LID_REGNUM; > - i++) > - if (regno =3D=3D regnum) > - { > - handle_reg =3D FALSE; > - break; > - } > - } > - > - if (handle_reg) > - riscv_save_restore_reg (word_mode, regno, offset, fn); > - offset -=3D UNITS_PER_WORD; > - } > + offset =3D (cfun->machine->frame.gp_sp_offset - sp_offset).to_constant= () > + + UNITS_PER_WORD; > + for (regno =3D riscv_next_saved_reg (start, limit, &offset, false); > + regno <=3D limit; > + regno =3D riscv_next_saved_reg (regno, limit, &offset)) > + { > + if (cfun->machine->reg_is_wrapped_separately[regno]) > + continue; > + > + /* If this is a normal return in a function that calls the eh_retu= rn > + builtin, then do not restore the eh return data registers as tha= t > + would clobber the return value. But we do still need to save th= em > + in the prologue, and restore them for an exception return, so we > + need special handling here. */ > + if (epilogue && !maybe_eh_return > + && riscv_is_eh_return_data_register (regno)) > + continue; > + > + riscv_save_restore_reg (word_mode, regno, offset, fn); > + } > > /* This loop must iterate over the same space as its companion in > riscv_compute_frame_info. */ > -- > 2.38.1 >