From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by sourceware.org (Postfix) with ESMTPS id D15073858D33 for ; Thu, 27 Apr 2023 14:57:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D15073858D33 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4efef769000so5918616e87.3 for ; Thu, 27 Apr 2023 07:57:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1682607465; x=1685199465; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=mUaJg7UG5XYf4aGAd4Fr1JpzfHAIN6/+qa7JbXa5ev0=; b=H27E2aBWDPwHYhri8TqOBDU8UtdQ72R8iOwT0cKLhHJpE9ZLslLIQcsftappdhBvXV l7rK6Sx5rHXgsQ79gVnGDzDXB7T5iKJGon3hEc7N5jYZLFSoQyWlkgUalLuOHbrha+y4 hsf8BBBMiFxZl+aTq3qt4lPMFeVbR5O+/44ygENNHeG9M1sAephsSv3wDAt06Yaa0T8Z Yy1JXFh2T+qTSJ/jip3eRup8ajp6DiM17qI6/i23wfAlHhsFRmS10c5EcCEk/6tsehVT mqZkwqqbpnl6pncqlRGAJLKNENJQxm1EeXM6gIANVIIWdv0jb4LPNT86Y/vRZccnmERh 6cDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682607465; x=1685199465; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=mUaJg7UG5XYf4aGAd4Fr1JpzfHAIN6/+qa7JbXa5ev0=; b=cbDAxYGumvWGG62iJ8UOm2UU5VuMtu7F6vbDoutuOg7PrDe8qDlWmkveRs7yjPRDTl ISs/GSTmeWt0oUaKiCmHL/CPixVtojQr/ZIQ+/0XOu2rlolP2S98FNi1CSs6quoWuw13 IxKuTcJKRwCeRcs4mxsEtboYrKgAg8v55LMCiZA7E87vciTwQdUojt76fxi87NEeGNhq FVSeKiCAJAqRbAAQOjEUmF8pPTpU4hV0Yh0WoWImPK0n06cAz6kJccXMQcDyeMlZejus QQLvDMIngon75vB/j3hDVPAchu9LhYe7fSl3r6lXSGt5Xcb4TMFL5R6LNGLtgp5xdye4 CJkg== X-Gm-Message-State: AC+VfDyP2HzyY84DHRxTAByv0KV7dANTphWEA9AnC5NcB540JD2ZoZC/ JM1tCSQR4nt70nN2BYIUMpkl3ACuXI9wn3En8zSf1Q== X-Google-Smtp-Source: ACHHUZ4wyya+tTGHPrFmWCKZwsAYK6/8GFs7cMZq6Jx14uAco+bbIsfrHKTeFodsE1zYx3qs1EkjwzEoa7n4qJhtVJU= X-Received: by 2002:a2e:240a:0:b0:2a7:b1db:7f42 with SMTP id k10-20020a2e240a000000b002a7b1db7f42mr726577ljk.49.1682607465170; Thu, 27 Apr 2023 07:57:45 -0700 (PDT) MIME-Version: 1.0 References: <20230427143005.1781966-1-pan2.li@intel.com> In-Reply-To: <20230427143005.1781966-1-pan2.li@intel.com> From: Kito Cheng Date: Thu, 27 Apr 2023 22:57:34 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR To: pan2.li@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, yanzhang.wang@intel.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > +(define_split > + [(set (match_operand: 0 "register_operand") > + (if_then_else: > + (unspec: > + [(match_operand: 1 "vector_all_trues_mask_operand") > + (match_operand 6 "vector_length_operand") > + (match_operand 7 "const_int_operand") > + (match_operand 8 "const_int_operand") > + (reg:SI VL_REGNUM) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (match_operator: 3 "comparison_simplify_to_clear_operator" > + [(match_operand:VI 4 "register_operand") > + (match_operand:VI 5 "vector_arith_operand")]) > + (match_operand: 2 "vector_merge_operand")))] > + "TARGET_VECTOR && reload_completed && operands[4] == operands[5]" Could you try something like this? that should be more generic: (define_split [(set (match_operand:VB 0 "register_operand") (if_then_else:VB (unspec:VB [(match_operand:VB 1 "vector_all_trues_mask_operand") (match_operand 4 "vector_length_operand") (match_operand 5 "const_int_operand") (match_operand 6 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operand:VB 3 "vector_move_operand") (match_operand:VB 2 "vector_undef_operand")))] "TARGET_VECTOR && reload_completed" [(const_int 0)] { emit_insn (gen_pred_mov (mode, operands[0], CONST1_RTX (mode), RVV_VUNDEF (mode), CONST0_RTX (mode), operands[4], operands[5])); DONE; } )