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Wed, 24 May 2023 21:02:24 -0700 (PDT) MIME-Version: 1.0 References: <20230524112614.258594-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230524112614.258594-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Thu, 25 May 2023 12:02:13 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Remove FRM_REGNUM dependency for rtx conversions To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, palmer@rivosinc.com, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM, thanks :) On Wed, May 24, 2023 at 7:26=E2=80=AFPM wrote: > > From: Juzhe-Zhong > > According to RVV ISA: > The conversions use the dynamic rounding mode in frm, except for the rtz = variants, which round towards zero. > > So rtz conversion patterns should not have FRM dependency. > > We can't support mode switching for FRM yet since rvv intrinsic doc is no= t updated but > I think this patch is correct. > > gcc/ChangeLog: > > * config/riscv/vector.md: Remove FRM_REGNUM dependency in rtz ins= tructions. > > --- > gcc/config/riscv/vector.md | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 9afef0d12bc..15f66efaa48 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -7072,10 +7072,8 @@ > (match_operand 5 "const_int_operand" " i, i, i= , i") > (match_operand 6 "const_int_operand" " i, i, i= , i") > (match_operand 7 "const_int_operand" " i, i, i= , i") > - (match_operand 8 "const_int_operand" " i, i, i= , i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM) > - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (any_fix: > (match_operand:VF 3 "register_operand" " vr, vr, vr= , vr")) > (match_operand: 2 "vector_merge_operand" " vu, 0, vu= , 0")))] > @@ -7142,10 +7140,8 @@ > (match_operand 5 "const_int_operand" " i, i= ") > (match_operand 6 "const_int_operand" " i, i= ") > (match_operand 7 "const_int_operand" " i, i= ") > - (match_operand 8 "const_int_operand" " i, i= ") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM) > - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (any_fix:VWCONVERTI > (match_operand: 3 "register_operand" " vr, vr= ")) > (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0= ")))] > @@ -7233,10 +7229,8 @@ > (match_operand 5 "const_int_operand" " i, i, = i, i, i, i") > (match_operand 6 "const_int_operand" " i, i, = i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, = i, i, i, i") > - (match_operand 8 "const_int_operand" " i, i, = i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM) > - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (any_fix: > (match_operand:VF 3 "register_operand" " 0, 0, = 0, 0, vr, vr")) > (match_operand: 2 "vector_merge_operand" " vu, 0, v= u, 0, vu, 0")))] > -- > 2.36.1 >