From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by sourceware.org (Postfix) with ESMTPS id 1A1BF3858C60 for ; Fri, 28 Apr 2023 08:36:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1A1BF3858C60 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4ec81773cf7so10202896e87.2 for ; Fri, 28 Apr 2023 01:36:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1682670967; x=1685262967; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=LPvBCqY+MCeCZ8tS9eaBfCtxB1xG3srxr5JZy26rSGw=; b=SCfm82W4rO1h5qqnh+oakmQGtznwURbTb4AFA57KPNKf1i38Q16zOHEZi66/ZFfeik 728PfxV5Oc7XncobjJ+wRxiE0sVJfyz/hpjgZnxkb6Na00C1X/IdYJxXIi9Mo05jX8uc OI52b+ILrerOuJDCPbn39X+XLZCZmPUDLLvqHNR4SwT/iIhSv3v4mBcR+Jq45ya/anl2 ICC5rSz8/e8cL1qlLIIAGxy8uXlu1/cTbGN5VPkYX7LFnanoKad4aIneEmdYApayNnGa kEs9SurPA/cBrBhDbU5f6BX52CCZDBZSSXAgw2tSltydZI7VxKkRLztmIyI0D57GJge4 2WGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682670967; x=1685262967; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LPvBCqY+MCeCZ8tS9eaBfCtxB1xG3srxr5JZy26rSGw=; b=V9gTJX8o/Cdj4nlj/iI4snZI5NgJMUccRg3dKlqUOO5BmLStKk7g7qACjB5Ped8e3w xtShCWpiCJOnvML1MDteWHPiF8GXL8XC4AkbBNFBzYfCbbfHlin720/IaA9GkZLZlXVR n3q+AZUONdTj8w23Tfg5xSwV8EZOZCMc5TMREqQVJMuWz1k0RhdKBP5dX5iZ9W2laXKN 9HmBoDgXEC4LWVsZ7I/zVIm8BMVv2VPPk9aSYmDzjMuBM++JOFc/tiqWPflkRyF+bD1y fVZN1Fau7nYIPxdxI2WhQki5/KZMvu/La9ru8WoKIRHnQGF1PdInEN8MhwuohwrgaCit QDCw== X-Gm-Message-State: AC+VfDyitefKYn6cBMAO5pEYdaOOoUscfxg/RE+w1GSJ8irwn5Rm57Xi 7Y35XivbiPUCokfugrycY07LUC201ZR7i5hcaiv8yw== X-Google-Smtp-Source: ACHHUZ62zI4GOzHvcSSFvsqbGW5RDXN/BSXTTIilHkEHAM3L+Gvf/A7xZV+QmNDdupDdBrdWWvdoDzpVk4gBo7thnSA= X-Received: by 2002:a2e:9dc6:0:b0:2a8:c32d:1238 with SMTP id x6-20020a2e9dc6000000b002a8c32d1238mr1410559ljj.15.1682670967523; Fri, 28 Apr 2023 01:36:07 -0700 (PDT) MIME-Version: 1.0 References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> From: Kito Cheng Date: Fri, 28 Apr 2023 16:35:56 +0800 Message-ID: Subject: Re: [PATCH 00/11] Improvements for XThead* support To: Christoph Muellner Cc: gcc-patches@gcc.gnu.org, Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Feel free to just commit those patch got approved, I think last two patch will take longer time to review than others :P On Fri, Apr 28, 2023 at 2:12=E2=80=AFPM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This series improves the support for the XThead* ISA extensions > which are available e.g. on the T-Head XuanTie C906. > > The ISA spec can be found here: > https://github.com/T-head-Semi/thead-extension-spec > > So far the following extension support has been merged in GCC: > * XTheadBa > * XTheadBb > * XTheadBs > * XTheadCmo > * XTheadCondMov > * XTheadMemPair > > This patchset builds upon that and contains the following changes: > * Fix for sign/zero extension support for th.ext and th.extu > This is actually a resend, that has not been merged. > Jeff Law acked the patch last Friday. > * Fix for CFA reg notes creation > * Small fix for documentation of th_mempair_order_operands() > * Introduction of Xmode macro > * Two non-functional preparation commits for additional addressing modes > * A patch that moves XThead* specific peephole passes in its own file > * Support for XTheadMemIdx and its addressing modes > * Support for XTheadFMemIdx, which is similar to XTheadMemIdx > > All patches have been tested and don't introduce regressions > for RV32 or RV64. The patches have also been tested with > SPEC CPU2017 on QEMU (multiple combinations of extensions). > > Support patches of these extensions for Binutils, QEMU, and > LLVM have already been merged in the corresponding upstream > projects. > > Support patches for XTheadMemIdx and XTheadFMemIdx have been > submitted in an earlier series as well and received a couple of > rework-comments from Kito. We rewrote the whole support to > better meet the (reasonable) goal of keeping vendor extension > code separated from RISC-V standard code and to address other issues. > The resulting code is structured much better, which can be seen > in the small number of changes that are required for the last patch > (XTheadFMemIdx support). > > Christoph M=C3=BCllner (11): > riscv: xtheadbb: Add sign/zero extension support for th.ext and > th.extu > riscv: xtheadmempair: Fix CFA reg notes > riscv: xtheadmempair: Fix doc for th_mempair_order_operands() > riscv: thead: Adjust constraints of th_addsl INSN > riscv: Simplify output of MEM addresses > riscv: Define Xmode macro > riscv: Move address classification info types to riscv-protos.h > riscv: Prepare backend for index registers > riscv: thead: Factor out XThead*-specific peepholes > riscv: thead: Add support for the XTheadMemIdx ISA extension > riscv: thead: Add support for the XTheadFMemIdx ISA extension > > gcc/config/riscv/constraints.md | 24 + > gcc/config/riscv/peephole.md | 56 -- > gcc/config/riscv/riscv-protos.h | 74 +++ > gcc/config/riscv/riscv.cc | 87 ++- > gcc/config/riscv/riscv.h | 13 +- > gcc/config/riscv/riscv.md | 26 +- > gcc/config/riscv/thead-peephole.md | 292 ++++++++++ > gcc/config/riscv/thead.cc | 506 +++++++++++++++++- > gcc/config/riscv/thead.md | 240 ++++++++- > .../gcc.target/riscv/xtheadbb-ext-1.c | 67 +++ > .../gcc.target/riscv/xtheadbb-extu-1.c | 67 +++ > .../riscv/xtheadfmemidx-index-update.c | 20 + > .../xtheadfmemidx-index-xtheadbb-update.c | 20 + > .../riscv/xtheadfmemidx-index-xtheadbb.c | 22 + > .../gcc.target/riscv/xtheadfmemidx-index.c | 22 + > .../riscv/xtheadfmemidx-uindex-update.c | 20 + > .../xtheadfmemidx-uindex-xtheadbb-update.c | 20 + > .../riscv/xtheadfmemidx-uindex-xtheadbb.c | 24 + > .../gcc.target/riscv/xtheadfmemidx-uindex.c | 25 + > .../gcc.target/riscv/xtheadmemidx-helpers.h | 222 ++++++++ > .../riscv/xtheadmemidx-index-update.c | 27 + > .../xtheadmemidx-index-xtheadbb-update.c | 27 + > .../riscv/xtheadmemidx-index-xtheadbb.c | 36 ++ > .../gcc.target/riscv/xtheadmemidx-index.c | 36 ++ > .../riscv/xtheadmemidx-modify-xtheadbb.c | 74 +++ > .../gcc.target/riscv/xtheadmemidx-modify.c | 74 +++ > .../riscv/xtheadmemidx-uindex-update.c | 27 + > .../xtheadmemidx-uindex-xtheadbb-update.c | 27 + > .../riscv/xtheadmemidx-uindex-xtheadbb.c | 44 ++ > .../gcc.target/riscv/xtheadmemidx-uindex.c | 44 ++ > 30 files changed, 2146 insertions(+), 117 deletions(-) > create mode 100644 gcc/config/riscv/thead-peephole.md > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-up= date.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xt= headbb-update.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xt= headbb.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-u= pdate.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-x= theadbb-update.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-x= theadbb.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-upd= ate.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xth= eadbb-update.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xth= eadbb.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify-xt= headbb.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-up= date.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xt= headbb-update.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xt= headbb.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex.c > > -- > 2.40.1 >