From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by sourceware.org (Postfix) with ESMTPS id 4D7D63940CF0 for ; Thu, 10 Sep 2020 08:18:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 4D7D63940CF0 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=kito.cheng@sifive.com Received: by mail-lf1-x134.google.com with SMTP id d15so3077465lfq.11 for ; Thu, 10 Sep 2020 01:18:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=U+4DR+TYrkCNHbyBieO2vunRi2NdAIbsm1FTC3sXMFI=; b=DbrEDh0uKEj/94KCpBUwr3FvlvVpF3akpLePnVIFpla2mrAZCt5FZX7pwnxHaUvHWv +c6HKQyM0ARpnvhffU9qs5zSQ4KnEjbp7SlDIbv718n/Ixn7HbLg0zxROEGYQOsTzyWc h5BclYTCwkY7VpWhV+Q6cwyEq3iv/tDIaBofOm15Yy2mGc1pAVq0WcMQ2T45HdMbq4x/ rcxqciIWpdm+bx/mmbT4Eyvh6JbWj59AwntpH4pTjukUYuJa4Ap/EqQgZ9oZg66B/MyD bNiTPduR8Ir9WJvGQ7M2ajlZtfSKgRj3MPFhDyU9+0NiUQcpDUaDKo/R+2Io2pY+NMUp OzMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=U+4DR+TYrkCNHbyBieO2vunRi2NdAIbsm1FTC3sXMFI=; b=aoLGCE9Yofmk06U4iwSXArovC/O5gXIlqn9aNv0VBoP3BRgcj+RevjrL8hgo0jbINf KCNazZMfcaUJLTgJvFwvzUomO1CnvNN8aqBmDiIL+L2LW9xZl0XBFc49lDFLeM/2x30p ZTzs7tezQjHjUi0sMRj0scWhaN9az7C2ec9micG1+ReaG0OFsrZuWDMn7ieXb2xVnTGc nbHXBj1YKXIex+ZiOQ/8zU/0Y4I2RvdHRoNaF5CFCZAu2QYMuOLgC/+Y7XKblE0XrQf1 Zk8XhLqbm4j1xwszUX8QRdr2gV4ASOSuer3zQ4I7/EPQZgcd3SrNpCRyWFSveE59B+s2 dA8Q== X-Gm-Message-State: AOAM531X6VaJrgwJ3e9CoMuU4glkyH3DOfQ+F8z4X/m2esKby5IlNWXs I0+E1zWLcHobldNBjGP+3jv8p77x3PBPGFQ9kz7zKA== X-Google-Smtp-Source: ABdhPJyBk9RoI1claBJiKFN+UhGItMclMlRd1Bxy7tOelttT3n/0ERyUZ50ZCLr3LOG9L5VK/vD7EiJN4VBxFa08YHw= X-Received: by 2002:a19:8789:: with SMTP id j131mr3790476lfd.90.1599725931865; Thu, 10 Sep 2020 01:18:51 -0700 (PDT) MIME-Version: 1.0 References: <20200910034405.39647-1-kito.cheng@sifive.com> In-Reply-To: From: Kito Cheng Date: Thu, 10 Sep 2020 16:18:40 +0800 Message-ID: Subject: Re: [PATCH] PR target/96759 - Handle global variable assignment from misaligned structure/PARALLEL return values. To: Richard Biener Cc: GCC Patches , Kito Cheng Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 10 Sep 2020 08:18:54 -0000 Hi Richard: Thanks for your review :) > riscv doesn't seem to have movmisalign and I don't see why movmisalign > should not support a TImode parallel RHS so at least you should > put this check after the icode != CODE_FOR_nothing check? RISC-V has an option `-mno-strict-align` to enable mis-aligned access, but we didn't provide movmisalign pattern, I guess might be another issue, I tried to add movmisalign pattern and then it will feed PARALLEL into that, and got into a similar situation again, most targets are not except got PARALLEL, so that's the reason why I put before icode != CODE_FOR_nothing check. > Also wouldn't it be better to support PARALLEL from within > store_bit_field? For the above reason, I think store_bit_field supports PARALLEL is not enough. > After all this is a misaligned access and > since you didn't quote the RTL involved I'm guessing that > emit_group_store knows nothing about this fact. Oh, good point, how do you think about loading into temp and then storing it in the DECL, so that we could use original logic to handle misaligned store. A PoC for this idea, didn't fully tested yet: diff --git a/gcc/expr.c b/gcc/expr.c index 1a15f24b3979..6ef97740c764 100644 --- a/gcc/expr.c +++ b/gcc/expr.c @@ -5166,8 +5166,19 @@ expand_assignment (tree to, tree from, bool nontemporal) || targetm.slow_unaligned_access (mode, align))) { rtx reg, mem; + push_temp_slots (); reg = expand_expr (from, NULL_RTX, VOIDmode, EXPAND_NORMAL); + + if (GET_CODE (reg) == PARALLEL) + { + rtx temp = assign_stack_temp (mode, + GET_MODE_SIZE (mode)); + emit_group_store (temp, reg, TREE_TYPE (from), + int_size_in_bytes (TREE_TYPE (from))); + reg = temp; + } + reg = force_not_mem (reg); mem = expand_expr (to, NULL_RTX, VOIDmode, EXPAND_WRITE); if (TREE_CODE (to) == MEM_REF && REF_REVERSE_STORAGE_ORDER (to)) @@ -5186,6 +5197,7 @@ expand_assignment (tree to, tree from, bool nontemporal) else store_bit_field (mem, GET_MODE_BITSIZE (mode), 0, 0, 0, mode, reg, false); + pop_temp_slots (); return; }