From: Kito Cheng <kito.cheng@sifive.com>
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com,
jeffreyalaw@gmail.com, rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Support vi variant for vec_cmp
Date: Thu, 18 Jan 2024 18:04:26 +0800 [thread overview]
Message-ID: <CALLt3TiDsD09vWzJP_bXMLhORZ6pSHXUbRjqs+ijUpWTv-zf7Q@mail.gmail.com> (raw)
In-Reply-To: <20240118095857.272830-1-juzhe.zhong@rivai.ai>
LGTM, thanks :)
On Thu, Jan 18, 2024 at 5:59 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> While running various benchmarks, I notice we miss vi variant support for integer comparison.
> That is, we can vectorize code into vadd.vi but we can't vectorize into vmseq.vi.
>
> Consider this following case:
>
> void
> foo (int n, int **__restrict a)
> {
> int b;
> int c;
> int d;
> for (b = 0; b < n; b++)
> for (long e = 8; e > 0; e--)
> a[b][e] = a[b][e] == 15;
> }
>
> Before this patch:
>
> vsetivli zero,4,e32,m1,ta,ma
> vmv.v.i v4,15
> vmv.v.i v3,1
> vmv.v.i v2,0
> .L3:
> ld a5,0(a1)
> addi a4,a5,4
> addi a5,a5,20
> vle32.v v1,0(a5)
> vle32.v v0,0(a4)
> vmseq.vv v0,v0,v4
>
> After this patch:
>
> ld a5,0(a1)
> addi a4,a5,4
> addi a5,a5,20
> vle32.v v1,0(a5)
> vle32.v v0,0(a4)
> vmseq.vi v0,v0,15
>
> It's the missing feature caused by our some mistakes, support vi variant for vec_cmp like other patterns (add, sub, ..., etc).
>
> Tested with no regression, ok for trunk ?
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Support vi variant.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/macro.h: New test.
>
> ---
> gcc/config/riscv/autovec.md | 4 +--
> .../riscv/rvv/autovec/cmp/cmp_vi-1.c | 16 +++++++++++
> .../riscv/rvv/autovec/cmp/cmp_vi-2.c | 16 +++++++++++
> .../riscv/rvv/autovec/cmp/cmp_vi-3.c | 28 +++++++++++++++++++
> .../riscv/rvv/autovec/cmp/cmp_vi-4.c | 28 +++++++++++++++++++
> .../riscv/rvv/autovec/cmp/cmp_vi-5.c | 16 +++++++++++
> .../riscv/rvv/autovec/cmp/cmp_vi-6.c | 16 +++++++++++
> .../riscv/rvv/autovec/cmp/cmp_vi-7.c | 28 +++++++++++++++++++
> .../riscv/rvv/autovec/cmp/cmp_vi-8.c | 28 +++++++++++++++++++
> .../riscv/rvv/autovec/cmp/cmp_vi-9.c | 18 ++++++++++++
> .../gcc.target/riscv/rvv/autovec/cmp/macro.h | 11 ++++++++
> 11 files changed, 207 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/macro.h
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 706cd9717cb..5ec1c59bdd4 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -664,7 +664,7 @@
> [(set (match_operand:<VM> 0 "register_operand")
> (match_operator:<VM> 1 "comparison_operator"
> [(match_operand:V_VLSI 2 "register_operand")
> - (match_operand:V_VLSI 3 "register_operand")]))]
> + (match_operand:V_VLSI 3 "nonmemory_operand")]))]
> "TARGET_VECTOR"
> {
> riscv_vector::expand_vec_cmp (operands[0], GET_CODE (operands[1]),
> @@ -677,7 +677,7 @@
> [(set (match_operand:<VM> 0 "register_operand")
> (match_operator:<VM> 1 "comparison_operator"
> [(match_operand:V_VLSI 2 "register_operand")
> - (match_operand:V_VLSI 3 "register_operand")]))]
> + (match_operand:V_VLSI 3 "nonmemory_operand")]))]
> "TARGET_VECTOR"
> {
> riscv_vector::expand_vec_cmp (operands[0], GET_CODE (operands[1]),
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c
> new file mode 100644
> index 00000000000..10c232f77bd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "macro.h"
> +
> +CMP_VI (ne_char, char, n, !=, 15)
> +CMP_VI (ne_short, short, n, !=, 15)
> +CMP_VI (ne_int, int, n, !=, 15)
> +CMP_VI (ne_long, long, n, !=, 15)
> +CMP_VI (ne_unsigned_char, unsigned char, n, !=, 15)
> +CMP_VI (ne_unsigned_short, unsigned short, n, !=, 15)
> +CMP_VI (ne_unsigned_int, unsigned int, n, !=, 15)
> +CMP_VI (ne_unsigned_long, unsigned long, n, !=, 15)
> +
> +/* { dg-final { scan-assembler-times {vmsne\.vi} 16 } } */
> +/* { dg-final { scan-assembler-not {vmsne\.vv} } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c
> new file mode 100644
> index 00000000000..92bea596cd8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "macro.h"
> +
> +CMP_VI (ne_char, char, n, !=, -16)
> +CMP_VI (ne_short, short, n, !=, -16)
> +CMP_VI (ne_int, int, n, !=, -16)
> +CMP_VI (ne_long, long, n, !=, -16)
> +CMP_VI (ne_unsigned_char, unsigned char, n, !=, -16)
> +CMP_VI (ne_unsigned_short, unsigned short, n, !=, -16)
> +CMP_VI (ne_unsigned_int, unsigned int, n, !=, -16)
> +CMP_VI (ne_unsigned_long, unsigned long, n, !=, -16)
> +
> +/* { dg-final { scan-assembler-times {vmsne\.vi} 13 } } */
> +/* { dg-final { scan-assembler-not {vmsne\.vv} } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c
> new file mode 100644
> index 00000000000..c9003279b0c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
> +
> +#include "macro.h"
> +
> +CMP_VI (ne_char, char, 4, !=, 15)
> +CMP_VI (ne_short, short, 4, !=, 15)
> +CMP_VI (ne_int, int, 4, !=, 15)
> +CMP_VI (ne_long, long, 4, !=, 15)
> +CMP_VI (ne_unsigned_char, unsigned char, 4, !=, 15)
> +CMP_VI (ne_unsigned_short, unsigned short, 4, !=, 15)
> +CMP_VI (ne_unsigned_int, unsigned int, 4, !=, 15)
> +CMP_VI (ne_unsigned_long, unsigned long, 4, !=, 15)
> +
> +/* { dg-final { scan-assembler-times {vmsne\.vi} 32 } } */
> +/* { dg-final { scan-assembler-not {vmsne\.vv} } } */
> +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c
> new file mode 100644
> index 00000000000..544ff751522
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
> +
> +#include "macro.h"
> +
> +CMP_VI (ne_char, char, 4, !=, -16)
> +CMP_VI (ne_short, short, 4, !=, -16)
> +CMP_VI (ne_int, int, 4, !=, -16)
> +CMP_VI (ne_long, long, 4, !=, -16)
> +CMP_VI (ne_unsigned_char, unsigned char, 4, !=, -16)
> +CMP_VI (ne_unsigned_short, unsigned short, 4, !=, -16)
> +CMP_VI (ne_unsigned_int, unsigned int, 4, !=, -16)
> +CMP_VI (ne_unsigned_long, unsigned long, 4, !=, -16)
> +
> +/* { dg-final { scan-assembler-times {vmsne\.vi} 20 } } */
> +/* { dg-final { scan-assembler-not {vmsne\.vv} } } */
> +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c
> new file mode 100644
> index 00000000000..b7a5a4397c1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "macro.h"
> +
> +CMP_VI (eq_char, char, n, ==, 15)
> +CMP_VI (eq_short, short, n, ==, 15)
> +CMP_VI (eq_int, int, n, ==, 15)
> +CMP_VI (eq_long, long, n, ==, 15)
> +CMP_VI (eq_unsigned_char, unsigned char, n, ==, 15)
> +CMP_VI (eq_unsigned_short, unsigned short, n, ==, 15)
> +CMP_VI (eq_unsigned_int, unsigned int, n, ==, 15)
> +CMP_VI (eq_unsigned_long, unsigned long, n, ==, 15)
> +
> +/* { dg-final { scan-assembler-times {vmseq\.vi} 16 } } */
> +/* { dg-final { scan-assembler-not {vmseq\.vv} } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c
> new file mode 100644
> index 00000000000..f297ac80bbd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "macro.h"
> +
> +CMP_VI (eq_char, char, n, ==, -16)
> +CMP_VI (eq_short, short, n, ==, -16)
> +CMP_VI (eq_int, int, n, ==, -16)
> +CMP_VI (eq_long, long, n, ==, -16)
> +CMP_VI (eq_unsigned_char, unsigned char, n, ==, -16)
> +CMP_VI (eq_unsigned_short, unsigned short, n, ==, -16)
> +CMP_VI (eq_unsigned_int, unsigned int, n, ==, -16)
> +CMP_VI (eq_unsigned_long, unsigned long, n, ==, -16)
> +
> +/* { dg-final { scan-assembler-times {vmseq\.vi} 13 } } */
> +/* { dg-final { scan-assembler-not {vmseq\.vv} } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c
> new file mode 100644
> index 00000000000..63ded00947d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
> +
> +#include "macro.h"
> +
> +CMP_VI (eq_char, char, 4, ==, 15)
> +CMP_VI (eq_short, short, 4, ==, 15)
> +CMP_VI (eq_int, int, 4, ==, 15)
> +CMP_VI (eq_long, long, 4, ==, 15)
> +CMP_VI (eq_unsigned_char, unsigned char, 4, ==, 15)
> +CMP_VI (eq_unsigned_short, unsigned short, 4, ==, 15)
> +CMP_VI (eq_unsigned_int, unsigned int, 4, ==, 15)
> +CMP_VI (eq_unsigned_long, unsigned long, 4, ==, 15)
> +
> +/* { dg-final { scan-assembler-times {vmseq\.vi} 32 } } */
> +/* { dg-final { scan-assembler-not {vmseq\.vv} } } */
> +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c
> new file mode 100644
> index 00000000000..f29b5f12c51
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
> +
> +#include "macro.h"
> +
> +CMP_VI (eq_char, char, 4, ==, -16)
> +CMP_VI (eq_short, short, 4, ==, -16)
> +CMP_VI (eq_int, int, 4, ==, -16)
> +CMP_VI (eq_long, long, 4, ==, -16)
> +CMP_VI (eq_unsigned_char, unsigned char, 4, ==, -16)
> +CMP_VI (eq_unsigned_short, unsigned short, 4, ==, -16)
> +CMP_VI (eq_unsigned_int, unsigned int, 4, ==, -16)
> +CMP_VI (eq_unsigned_long, unsigned long, 4, ==, -16)
> +
> +/* { dg-final { scan-assembler-times {vmseq\.vi} 20 } } */
> +/* { dg-final { scan-assembler-not {vmseq\.vv} } } */
> +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c
> new file mode 100644
> index 00000000000..bfc1a68a1e4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "macro.h"
> +
> +CMP_VI (le_char, char, n, <=, 15)
> +CMP_VI (le_short, short, n, <=, 15)
> +CMP_VI (le_int, int, n, <=, 15)
> +CMP_VI (le_long, long, n, <=, 15)
> +CMP_VI (le_unsigned_char, unsigned char, n, <=, 15)
> +CMP_VI (le_unsigned_short, unsigned short, n, <=, 15)
> +CMP_VI (le_unsigned_int, unsigned int, n, <=, 15)
> +CMP_VI (le_unsigned_long, unsigned long, n, <=, 15)
> +
> +/* { dg-final { scan-assembler-times {vmsle\.vi} 7 } } */
> +/* { dg-final { scan-assembler-times {vmsleu\.vi} 9 } } */
> +/* { dg-final { scan-assembler-not {vmsle\.vv} } } */
> +/* { dg-final { scan-assembler-not {vmsleu\.vv} } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/macro.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/macro.h
> new file mode 100644
> index 00000000000..3fe6ee89a99
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/macro.h
> @@ -0,0 +1,11 @@
> +#define CMP_VI(NAME, TYPE, NITERS, OP, IMM) \
> + void NAME (int n, TYPE **__restrict a) \
> + { \
> + int b; \
> + int c; \
> + int d; \
> + for (b = 0; b < NITERS; b++) \
> + for (int e = 8; e > 0; e--) \
> + a[b][e] = a[b][e] OP IMM; \
> + }
> +
> --
> 2.36.3
>
prev parent reply other threads:[~2024-01-18 10:04 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-18 9:58 Juzhe-Zhong
2024-01-18 10:04 ` Kito Cheng [this message]
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