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* [PATCH] RISC-V: Fix RVV_VLMAX
@ 2024-01-19  8:11 Juzhe-Zhong
  2024-01-19  8:19 ` Kito Cheng
  0 siblings, 1 reply; 3+ messages in thread
From: Juzhe-Zhong @ 2024-01-19  8:11 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, kito.cheng, jeffreyalaw, rdapp.gcc, Juzhe-Zhong

This patch fixes memory hog found in SPEC2017 wrf benchmark which caused by
RVV_VLMAX since RVV_VLMAX generate brand new rtx by gen_rtx_REG (Pmode, X0_REGNUM)
every time we call RVV_VLMAX, that is, we are always generating garbage and redundant
(reg:DI 0 zero) rtx.

After this patch fix, the memory hog is gone.

Time variable                                   usr           sys          wall           GGC
 machine dep reorg                  :   1.99 (  9%)   0.35 ( 56%)   2.33 ( 10%)   939M ( 80%) [Before this patch]
 machine dep reorg                  :   1.71 (  6%)   0.16 ( 27%)   3.77 (  6%)   659k (  0%) [After this patch]
 
Time variable                                   usr           sys          wall           GGC
 machine dep reorg                  :  75.93 ( 18%)  14.23 ( 88%)  90.15 ( 21%) 33383M ( 95%) [Before this patch]
 machine dep reorg                  :  56.00 ( 14%)   7.92 ( 77%)  63.93 ( 15%)  4361k (  0%) [After this patch]

Test is running. Ok for trunk if I passed the test with no regresion ?

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
	(RVV_VUNDEF): Ditto.
	* config/riscv/riscv-vsetvl.cc: Add timevar.

---
 gcc/config/riscv/riscv-protos.h  | 5 ++---
 gcc/config/riscv/riscv-vsetvl.cc | 2 +-
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 7853b488838..7fe26fcd939 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -299,10 +299,9 @@ void riscv_run_selftests (void);
 #endif
 
 namespace riscv_vector {
-#define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM)
+#define RVV_VLMAX regno_reg_rtx[X0_REGNUM]
 #define RVV_VUNDEF(MODE)                                                       \
-  gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)),        \
-		  UNSPEC_VUNDEF)
+  gen_rtx_UNSPEC (MODE, gen_rtvec (1, RVV_VLMAX), UNSPEC_VUNDEF)
 
 /* These flags describe how to pass the operands to a rvv insn pattern.
    e.g.:
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 2067073185f..54c85ffb7d5 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3556,7 +3556,7 @@ const pass_data pass_data_vsetvl = {
   RTL_PASS,	 /* type */
   "vsetvl",	 /* name */
   OPTGROUP_NONE, /* optinfo_flags */
-  TV_NONE,	 /* tv_id */
+  TV_MACH_DEP,	 /* tv_id */
   0,		 /* properties_required */
   0,		 /* properties_provided */
   0,		 /* properties_destroyed */
-- 
2.36.3


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] RISC-V: Fix RVV_VLMAX
  2024-01-19  8:11 [PATCH] RISC-V: Fix RVV_VLMAX Juzhe-Zhong
@ 2024-01-19  8:19 ` Kito Cheng
  2024-01-19  8:35   ` juzhe.zhong
  0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2024-01-19  8:19 UTC (permalink / raw)
  To: Juzhe-Zhong; +Cc: gcc-patches, kito.cheng, jeffreyalaw, rdapp.gcc

LGTM, nice catch, I wasn't aware that would be a problem.

On Fri, Jan 19, 2024 at 4:12 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> This patch fixes memory hog found in SPEC2017 wrf benchmark which caused by
> RVV_VLMAX since RVV_VLMAX generate brand new rtx by gen_rtx_REG (Pmode, X0_REGNUM)
> every time we call RVV_VLMAX, that is, we are always generating garbage and redundant
> (reg:DI 0 zero) rtx.
>
> After this patch fix, the memory hog is gone.
>
> Time variable                                   usr           sys          wall           GGC
>  machine dep reorg                  :   1.99 (  9%)   0.35 ( 56%)   2.33 ( 10%)   939M ( 80%) [Before this patch]
>  machine dep reorg                  :   1.71 (  6%)   0.16 ( 27%)   3.77 (  6%)   659k (  0%) [After this patch]
>
> Time variable                                   usr           sys          wall           GGC
>  machine dep reorg                  :  75.93 ( 18%)  14.23 ( 88%)  90.15 ( 21%) 33383M ( 95%) [Before this patch]
>  machine dep reorg                  :  56.00 ( 14%)   7.92 ( 77%)  63.93 ( 15%)  4361k (  0%) [After this patch]
>
> Test is running. Ok for trunk if I passed the test with no regresion ?
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
>         (RVV_VUNDEF): Ditto.
>         * config/riscv/riscv-vsetvl.cc: Add timevar.
>
> ---
>  gcc/config/riscv/riscv-protos.h  | 5 ++---
>  gcc/config/riscv/riscv-vsetvl.cc | 2 +-
>  2 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 7853b488838..7fe26fcd939 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -299,10 +299,9 @@ void riscv_run_selftests (void);
>  #endif
>
>  namespace riscv_vector {
> -#define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM)
> +#define RVV_VLMAX regno_reg_rtx[X0_REGNUM]
>  #define RVV_VUNDEF(MODE)                                                       \
> -  gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)),        \
> -                 UNSPEC_VUNDEF)
> +  gen_rtx_UNSPEC (MODE, gen_rtvec (1, RVV_VLMAX), UNSPEC_VUNDEF)
>
>  /* These flags describe how to pass the operands to a rvv insn pattern.
>     e.g.:
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index 2067073185f..54c85ffb7d5 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -3556,7 +3556,7 @@ const pass_data pass_data_vsetvl = {
>    RTL_PASS,     /* type */
>    "vsetvl",     /* name */
>    OPTGROUP_NONE, /* optinfo_flags */
> -  TV_NONE,      /* tv_id */
> +  TV_MACH_DEP,  /* tv_id */
>    0,            /* properties_required */
>    0,            /* properties_provided */
>    0,            /* properties_destroyed */
> --
> 2.36.3
>

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: Re: [PATCH] RISC-V: Fix RVV_VLMAX
  2024-01-19  8:19 ` Kito Cheng
@ 2024-01-19  8:35   ` juzhe.zhong
  0 siblings, 0 replies; 3+ messages in thread
From: juzhe.zhong @ 2024-01-19  8:35 UTC (permalink / raw)
  To: Kito.cheng; +Cc: gcc-patches, kito.cheng, jeffreyalaw, Robin Dapp

[-- Attachment #1: Type: text/plain, Size: 3334 bytes --]

Thanks. I will commit V2 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/643420.html 
after I finishing testing.

V2 no difference from V1 in codes except adding:

PR target/113495



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2024-01-19 16:19
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Fix RVV_VLMAX
LGTM, nice catch, I wasn't aware that would be a problem.
 
On Fri, Jan 19, 2024 at 4:12 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> This patch fixes memory hog found in SPEC2017 wrf benchmark which caused by
> RVV_VLMAX since RVV_VLMAX generate brand new rtx by gen_rtx_REG (Pmode, X0_REGNUM)
> every time we call RVV_VLMAX, that is, we are always generating garbage and redundant
> (reg:DI 0 zero) rtx.
>
> After this patch fix, the memory hog is gone.
>
> Time variable                                   usr           sys          wall           GGC
>  machine dep reorg                  :   1.99 (  9%)   0.35 ( 56%)   2.33 ( 10%)   939M ( 80%) [Before this patch]
>  machine dep reorg                  :   1.71 (  6%)   0.16 ( 27%)   3.77 (  6%)   659k (  0%) [After this patch]
>
> Time variable                                   usr           sys          wall           GGC
>  machine dep reorg                  :  75.93 ( 18%)  14.23 ( 88%)  90.15 ( 21%) 33383M ( 95%) [Before this patch]
>  machine dep reorg                  :  56.00 ( 14%)   7.92 ( 77%)  63.93 ( 15%)  4361k (  0%) [After this patch]
>
> Test is running. Ok for trunk if I passed the test with no regresion ?
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
>         (RVV_VUNDEF): Ditto.
>         * config/riscv/riscv-vsetvl.cc: Add timevar.
>
> ---
>  gcc/config/riscv/riscv-protos.h  | 5 ++---
>  gcc/config/riscv/riscv-vsetvl.cc | 2 +-
>  2 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 7853b488838..7fe26fcd939 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -299,10 +299,9 @@ void riscv_run_selftests (void);
>  #endif
>
>  namespace riscv_vector {
> -#define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM)
> +#define RVV_VLMAX regno_reg_rtx[X0_REGNUM]
>  #define RVV_VUNDEF(MODE)                                                       \
> -  gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)),        \
> -                 UNSPEC_VUNDEF)
> +  gen_rtx_UNSPEC (MODE, gen_rtvec (1, RVV_VLMAX), UNSPEC_VUNDEF)
>
>  /* These flags describe how to pass the operands to a rvv insn pattern.
>     e.g.:
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index 2067073185f..54c85ffb7d5 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -3556,7 +3556,7 @@ const pass_data pass_data_vsetvl = {
>    RTL_PASS,     /* type */
>    "vsetvl",     /* name */
>    OPTGROUP_NONE, /* optinfo_flags */
> -  TV_NONE,      /* tv_id */
> +  TV_MACH_DEP,  /* tv_id */
>    0,            /* properties_required */
>    0,            /* properties_provided */
>    0,            /* properties_destroyed */
> --
> 2.36.3
>
 

^ permalink raw reply	[flat|nested] 3+ messages in thread

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2024-01-19  8:11 [PATCH] RISC-V: Fix RVV_VLMAX Juzhe-Zhong
2024-01-19  8:19 ` Kito Cheng
2024-01-19  8:35   ` juzhe.zhong

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