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From: Kito Cheng <kito.cheng@sifive.com>
To: Robin Dapp <rdapp.gcc@gmail.com>
Cc: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
	Richard Biener <richard.guenther@gmail.com>,
	 gcc-patches <gcc-patches@gcc.gnu.org>,
	palmer <palmer@dabbelt.com>,  "kito.cheng" <kito.cheng@gmail.com>,
	jeffreyalaw <jeffreyalaw@gmail.com>,
	 "pan2.li" <pan2.li@intel.com>
Subject: Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V
Date: Tue, 30 May 2023 17:11:08 +0800	[thread overview]
Message-ID: <CALLt3Tic_G5uGvSDEntwB5jRKetzDgsn=+brqD28c1nmGb6KNA@mail.gmail.com> (raw)
In-Reply-To: <5873dbb5-ef8f-6411-1841-d849030554e3@gmail.com>

(I am still on the meeting hell, and will be released very later,
apology for short and incomplete reply, and will reply complete later)

One point for adding VLS mode support is because SLP, especially for
those SLP candidate not in the loop, those case use VLS type can be
better, of cause using larger safe VLA type can optimize too, but that
will cause one issue we found in RISC-V in LLVM - it will spill/reload
whole register instead of exact size.

e.g.

int32x4_t a;
// def a
// spill a
foo ()
// reload a
// use a

Consider we use a VLA mode for a, it will spill and reload with whole
register VLA mode
Online demo here: https://godbolt.org/z/Y1fThbxE6

On Tue, May 30, 2023 at 5:05 PM Robin Dapp <rdapp.gcc@gmail.com> wrote:
>
> >>> but ideally the user would be able to specify -mrvv-size=32 for an
> >>> implementation with 32 byte vectors and then vector lowering would make use
> >>> of vectors up to 32 bytes?
> >
> > Actually, we don't want to specify -mrvv-size = 32 to enable vectorization on GNU vectors.
> > You can take a look this example:
> > https://godbolt.org/z/3jYqoM84h <https://godbolt.org/z/3jYqoM84h>
> >
> > GCC need to specify the mrvv size to enable GNU vectors and the codegen only can run on CPU with vector-length = 128bit.
> > However, LLVM doesn't need to specify the vector length, and the codegen can run on any CPU with RVV  vector-length >= 128 bits.
> >
> > This is what this patch want to do.
> >
> > Thanks.
> I think Richard's question was rather if it wasn't better to do it more
> generically and lower vectors to what either the current cpu or what the
> user specified rather than just 16-byte vectors (i.e. indeed a fixed
> vlmin and not a fixed vlmin == fixed vlmax).
>
> This patch assumes everything is fixed for optimization purposes and then
> switches over to variable-length when nothing can be changed anymore.  That
> is, we would work on "vlmin"-sized chunks in a VLA fashion at runtime?
> We would need to make sure that no pass after reload makes use of VLA
> properties at all.
>
> In general I don't have a good overview of which optimizations we gain by
> such an approach or rather which ones are prevented by VLA altogether?
> What's the idea for the future?  Still use LEN_LOAD et al. (and masking)
> with "fixed vlmin"?  Wouldn't we select different IVs with this patch than
> what we would have for pure VLA?
>
> Regards
>  Robin

  reply	other threads:[~2023-05-30  9:11 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-30  6:06 Kito Cheng
2023-05-30  6:32 ` juzhe.zhong
2023-05-30  6:51   ` Kito Cheng
2023-05-30  6:59     ` juzhe.zhong
2023-05-30  7:13 ` Richard Biener
2023-05-30  7:45   ` juzhe.zhong
2023-05-30  9:05     ` Robin Dapp
2023-05-30  9:11       ` Kito Cheng [this message]
2023-05-30  9:16         ` Kito Cheng
2023-05-30  9:16       ` juzhe.zhong
2023-05-30  9:29         ` Richard Biener
2023-05-30  9:37           ` juzhe.zhong
2023-05-30  9:44           ` juzhe.zhong
2023-05-30 15:45             ` Kito Cheng
2023-05-30 23:19               ` 钟居哲
     [not found]             ` <DC99791C4B2B4D40+106F137E-2B0D-4732-A7C5-8EE0242F9F5A@rivai.ai>
2023-06-12 23:34               ` Jeff Law
     [not found]               ` <529320C359BE5467+690CDE73-D54E-48E2-81C4-B742060D7F28@rivai.ai>
2023-06-13 16:10                 ` Jeff Law
2023-05-30  7:27 ` Robin Dapp
2023-05-30  7:40   ` juzhe.zhong

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