From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id 743DD3858416 for ; Tue, 6 Jun 2023 01:48:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 743DD3858416 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1b04782fe07so30256855ad.3 for ; Mon, 05 Jun 2023 18:48:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1686016114; x=1688608114; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=ik0BjbFDk53WHoMa2QJeco7zLfwIvf2n5y+pqQa7Gjg=; b=NVC/EFS6vZi2DPMZuZriEvIL/f8ff8Hd+Mshd5AfmG4Zo6+EvKq/Lr7T6MM+PtFAz/ pleQJ7R+YDCbjwQRVcdxOzaIbffNjH/GJ6sh3GXc94gWSHp8EmMX8DX2nJtH5gciIvmo Qpvw5T6n5XH+Xr/K3IJJ+t1UGLNzGWTlrVP9A2FZiLdKWVe04qhOsS9Xhr7Go1SWRIRj 0fEm3BquhiON+BLrSAw0EybhbQnm0kdcYykAnIUGBD2zMjt24mROhuHaD8cxD5GrH4uZ z94cSXY0gmnuOK15TjNDhF8y62/kuddHgkKclwF6K4+UohNIv/Fw1lAO/JNnKQbTOBhA xaZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686016114; x=1688608114; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ik0BjbFDk53WHoMa2QJeco7zLfwIvf2n5y+pqQa7Gjg=; b=O9EtlrZVOH7cxkw6LDurXwgCtx0iUNJNveid8Bn1/2Pkni8pYOlr7oK41pjQZJk9fu 7uHDocMN5RsmhwwIhnTusHqcS5YVH8fpuq6q/nlU1h1tUqiataCqYLgMlfAOIQA1wQ/Q LleoSwsLxZz/+7+Ek8u0FlEY4SDoKGNQhJes/TuUtAHq8fH/k2yj1xxsqKyFxLYad+So dJ7aQ9jXug1tzUu5RQDgNe7vzLImYZKeE+alllbgy/S0gRvEZ4Mo9F81rpy2Zvlrlfoj 5I79ai1yivgQgoUW0ALhCEpVvFSfKSTR+p2ugljEvhv5dNt/JFrcYZ0DPYOYqnwl3Ez6 JSaw== X-Gm-Message-State: AC+VfDzoHIyhXfDRKigcKCLXKwywU8GcIYv8uJYgxNZ4dyOybz3AqwuJ nlktPaeiEZICAYO5DhOddXefmbqEFrf50XLg6RL7tg== X-Google-Smtp-Source: ACHHUZ6e9O/CwO9cDpLhQ7Ld655xzD4U+1Buevw+OWStvCGomAkj3WNDitMfiNcWpzaQjqMQFEJMWUwdxwUhwrYQ6lU= X-Received: by 2002:a17:902:c94b:b0:1b0:7c3c:31f7 with SMTP id i11-20020a170902c94b00b001b07c3c31f7mr469285pla.28.1686016114156; Mon, 05 Jun 2023 18:48:34 -0700 (PDT) MIME-Version: 1.0 References: <20230605144952.2546564-1-pan2.li@intel.com> <60250B9FED9AB19E+2023060609104365666371@rivai.ai> <67CCBF2ADF5ACE0B+2023060609412034104775@rivai.ai> In-Reply-To: <67CCBF2ADF5ACE0B+2023060609412034104775@rivai.ai> From: Kito Cheng Date: Tue, 6 Jun 2023 09:48:22 +0800 Message-ID: Subject: Re: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction floating-point intrinsic API To: "juzhe.zhong@rivai.ai" Cc: "kito.cheng" , "pan2.li" , gcc-patches , "yanzhang.wang" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: OK for landing this patch first, and fix by follow up patches. On Tue, Jun 6, 2023 at 9:41=E2=80=AFAM juzhe.zhong@rivai.ai wrote: > > I think we should split instructions pattern which belongs to ZVFHMIN. > And add ZVFH gating into all original iterator for example: VF VWF....etc= . > > ________________________________ > juzhe.zhong@rivai.ai > > > From: Kito Cheng > Date: 2023-06-06 09:32 > To: juzhe.zhong@rivai.ai > CC: pan2.li; gcc-patches; Kito.cheng; yanzhang.wang > Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction floating-= point intrinsic API > > diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/ve= ctor-iterators.md > > index e4f2ba90799..c338e3c9003 100644 > > --- a/gcc/config/riscv/vector-iterators.md > > +++ b/gcc/config/riscv/vector-iterators.md > > @@ -330,10 +330,18 @@ (define_mode_iterator VF_ZVE32 [ > > ]) > > (define_mode_iterator VWF [ > > + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") > > + (VNx2HF "TARGET_VECTOR_ELEN_FP_16") > > + (VNx4HF "TARGET_VECTOR_ELEN_FP_16") > > + (VNx8HF "TARGET_VECTOR_ELEN_FP_16") > > + (VNx16HF "TARGET_VECTOR_ELEN_FP_16") > > + (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > > + (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >=3D 128") > > I am little concern about using TARGET_VECTOR_ELEN_FP_16 as predictor her= e, > zvfhmin also set TARGET_VECTOR_ELEN_FP_16 flag, > so it means zvfhmin also enabled reduction? > > and also has the same concern for V and VF in the last patch[1] too. > > [1] https://patchwork.sourceware.org/project/gcc/patch/20230605082043.170= 7158-1-pan2.li@intel.com/ > > Give a more practical example to explain my concern: > > We've using V and VF iterators in autovec.md, and zvfhmin will set > MASK_VECTOR_ELEN_FP_16 > which means zvfhmin WILL enable most autovec patterns with fp16, > that should not what we expected to do I think? >