From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x230.google.com (mail-oi1-x230.google.com [IPv6:2607:f8b0:4864:20::230]) by sourceware.org (Postfix) with ESMTPS id 8439F3854153 for ; Thu, 27 Jul 2023 11:51:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8439F3854153 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-oi1-x230.google.com with SMTP id 5614622812f47-3a38953c928so755117b6e.1 for ; Thu, 27 Jul 2023 04:51:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1690458698; x=1691063498; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=EGD1RFvljVRyuoJDt7bv8hwe2X0vEq19blPOUjOiOK4=; b=JUUPZ2WDpkoz7yPuE61iMu4fZpq+iTCnGenWVMQTpsyDxhCP47NR/4a0yiNcteVCdP VBCPz1D04XAEnCmDC3kVnxkniPNqrGsK8FHZk5TYdx9G+cFrvJCtrVBSCIvtVFfguH0v Or7jHI6zfoZRZgAIgAbCPckg2rqVnE1uGL6DpC4YVZUMS6QvPXXHJ/RLVl+vifycTekV ep1Ry3XmodnEAxkKbJVg/vZM8lJlf92K1HAExtToDRlih6LD+yASLPfhxp6eVGYvFM5Q gzbRQpeBy9j9nAvv1vwHzg2/MDWsPpIyAhSxVWTnQ3lWwEnNa3vh3wdbYUXsnpxS4PnA GiMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690458698; x=1691063498; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EGD1RFvljVRyuoJDt7bv8hwe2X0vEq19blPOUjOiOK4=; b=BCaxaVRminH1WFp94h4irJ530rKBCT4lhMJ15Nj70365gpLO5bPvffADODznZDSgy4 WlKq/jzyO6sCX9m9kpNGM7KFL0s1q5lNei1SgcYjqxMSuifFwGo0TwetZ5LindnZ0uG9 sQaoUdnu6xnhrKehPOKV7X6sX+5PIHrJXIumuGWFvque8ORs2Jf3lLk8jaKvBoWQd65M CDNivyzHWJvsDwwYx7FEEW9gnfMaURDZ0kSeZLTKG1N4tifGHHWYunV3GHr3jjdBt+Li v9imzN+FtpHZ3lDx0ZyYdTL+DJs+RXLgECeBqbFSjo75fbVph5/FLz51Kmo/swutVO8S fEVQ== X-Gm-Message-State: ABy/qLa5Mx5MfcdA/cj+TN7E8Ew/EfWxc01jro78e3hWhvyOZ2+i4WKY ZFqfj2VqZ6CmYmQgMd5UazdMMQ0SyeSUbJt+RQCwNg== X-Google-Smtp-Source: APBJJlHeJ43LqeIV6T0NaVpvNCQ/EXnr03hDnvAiALDEoa4h2DfNRQC+3VVMULeCjQa2AdydaGzOjN5NYDH0YnfNbrc= X-Received: by 2002:a54:4501:0:b0:3a1:d075:348b with SMTP id l1-20020a544501000000b003a1d075348bmr2729227oil.59.1690458697708; Thu, 27 Jul 2023 04:51:37 -0700 (PDT) MIME-Version: 1.0 References: <20230727114702.219531-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230727114702.219531-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Thu, 27 Jul 2023 19:51:26 +0800 Message-ID: Subject: Re: [PATCH V4] RISC-V: Enable basic VLS modes support To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Thanks, it's LGTM, it's really another big move for vector support! On Thu, Jul 27, 2023 at 7:47=E2=80=AFPM Juzhe-Zhong = wrote: > > Support && Test VLS modes load/store/reg move as well as LRA spilling > > gcc/ChangeLog: > > * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Add VLS modes. > (ADJUST_ALIGNMENT): Ditto. > (ADJUST_PRECISION): Ditto. > (VLS_MODES): Ditto. > (VECTOR_MODE_WITH_PREFIX): Ditto. > * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): New macro. > * config/riscv/riscv-protos.h (riscv_v_ext_vls_mode_p): New funct= ion. > * config/riscv/riscv-v.cc (INCLUDE_ALGORITHM): Add include. > (legitimize_move): Enable basic VLS modes support. > (get_vlmul): Ditto. > (get_ratio): Ditto. > (get_vector_mode): Ditto. > * config/riscv/riscv-vector-switch.def (VLS_ENTRY): Add vls modes= . > * config/riscv/riscv.cc (riscv_v_ext_vls_mode_p): New function. > (VLS_ENTRY): New macro. > (riscv_v_ext_mode_p): Add vls modes. > (riscv_get_v_regno_alignment): New function. > (riscv_print_operand): Add vls modes. > (riscv_hard_regno_nregs): Ditto. > (riscv_hard_regno_mode_ok): Ditto. > (riscv_regmode_natural_size): Ditto. > (riscv_vectorize_preferred_vector_alignment): Ditto. > * config/riscv/riscv.md: Ditto. > * config/riscv/vector-iterators.md: Ditto. > * config/riscv/vector.md: Ditto. > * config/riscv/autovec-vls.md: New file. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Add more checks. > * gcc.target/riscv/rvv/rvv.exp: Add VLS modes tests. > * gcc.target/riscv/rvv/autovec/vls/def.h: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-1.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-10.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-11.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-12.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-13.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-14.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-15.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-16.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-17.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-2.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-3.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-4.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-5.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-6.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-7.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-8.c: New test. > * gcc.target/riscv/rvv/autovec/vls/mov-9.c: New test. > * gcc.target/riscv/rvv/autovec/vls/spill-1.c: New test. > * gcc.target/riscv/rvv/autovec/vls/spill-2.c: New test. > * gcc.target/riscv/rvv/autovec/vls/spill-3.c: New test. > * gcc.target/riscv/rvv/autovec/vls/spill-4.c: New test. > * gcc.target/riscv/rvv/autovec/vls/spill-5.c: New test. > * gcc.target/riscv/rvv/autovec/vls/spill-6.c: New test. > * gcc.target/riscv/rvv/autovec/vls/spill-7.c: New test. > > --- > gcc/config/riscv/autovec-vls.md | 141 ++++++ > gcc/config/riscv/riscv-modes.def | 84 ++++ > gcc/config/riscv/riscv-opts.h | 4 + > gcc/config/riscv/riscv-protos.h | 1 + > gcc/config/riscv/riscv-v.cc | 153 +++++- > gcc/config/riscv/riscv-vector-switch.def | 102 ++++ > gcc/config/riscv/riscv.cc | 97 +++- > gcc/config/riscv/riscv.md | 10 +- > gcc/config/riscv/vector-iterators.md | 476 ++++++++++++++++++ > gcc/config/riscv/vector.md | 237 +++++++-- > .../riscv/rvv/autovec/partial/slp-9.c | 1 + > .../gcc.target/riscv/rvv/autovec/vls/def.h | 88 ++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-1.c | 179 +++++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-10.c | 139 +++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-11.c | 248 +++++++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-12.c | 229 +++++++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-13.c | 209 ++++++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-14.c | 190 +++++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-15.c | 229 +++++++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-16.c | 209 ++++++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-17.c | 190 +++++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-2.c | 19 + > .../gcc.target/riscv/rvv/autovec/vls/mov-3.c | 166 ++++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-4.c | 19 + > .../gcc.target/riscv/rvv/autovec/vls/mov-5.c | 152 ++++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-6.c | 19 + > .../gcc.target/riscv/rvv/autovec/vls/mov-7.c | 139 +++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-8.c | 166 ++++++ > .../gcc.target/riscv/rvv/autovec/vls/mov-9.c | 152 ++++++ > .../riscv/rvv/autovec/vls/spill-1.c | 133 +++++ > .../riscv/rvv/autovec/vls/spill-2.c | 124 +++++ > .../riscv/rvv/autovec/vls/spill-3.c | 115 +++++ > .../riscv/rvv/autovec/vls/spill-4.c | 106 ++++ > .../riscv/rvv/autovec/vls/spill-5.c | 124 +++++ > .../riscv/rvv/autovec/vls/spill-6.c | 115 +++++ > .../riscv/rvv/autovec/vls/spill-7.c | 106 ++++ > gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + > 37 files changed, 4798 insertions(+), 75 deletions(-) > create mode 100644 gcc/config/riscv/autovec-vls.md > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.= c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.= c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.= c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.= c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.= c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.= c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.= c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.= c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.= c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-= 1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-= 2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-= 3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-= 4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-= 5.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-= 6.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-= 7.c > > diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-v= ls.md > new file mode 100644 > index 00000000000..9ece317ca4e > --- /dev/null > +++ b/gcc/config/riscv/autovec-vls.md > @@ -0,0 +1,141 @@ > +;; Machine description for VLS of RVV auto-vectorization. > +;; Copyright (C) 2023 Free Software Foundation, Inc. > +;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies= Ltd. > + > +;; This file is part of GCC. > + > +;; GCC is free software; you can redistribute it and/or modify > +;; it under the terms of the GNU General Public License as published by > +;; the Free Software Foundation; either version 3, or (at your option) > +;; any later version. > + > +;; GCC is distributed in the hope that it will be useful, > +;; but WITHOUT ANY WARRANTY; without even the implied warranty of > +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +;; GNU General Public License for more details. > + > +;; You should have received a copy of the GNU General Public License > +;; along with GCC; see the file COPYING3. If not see > +;; . > + > +;; We define VLS modes as 'define_insn_and_split' with normal > +;; RTX_CODE operation, so we can gain benefits from Combine optimization= s. > + > +;; ----------------------------------------------------------------- > +;; ---- Moves Operations > +;; ----------------------------------------------------------------- > + > +(define_expand "mov" > + [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand") > + (match_operand:VLS_AVL_IMM 1 "general_operand"))] > + "TARGET_VECTOR" > +{ > + if (riscv_vector::legitimize_move (operands[0], operands[1])) > + DONE; > +}) > + > +(define_insn_and_split "*mov_mem_to_mem" > + [(set (match_operand:VLS_AVL_IMM 0 "memory_operand") > + (match_operand:VLS_AVL_IMM 1 "memory_operand"))] > + "TARGET_VECTOR && can_create_pseudo_p ()" > + "#" > + "&& 1" > + [(const_int 0)] > + { > + if (GET_MODE_BITSIZE (mode).to_constant () <=3D MAX_BITS_PER_W= ORD) > + { > + /* Opitmize the following case: > + > + typedef int8_t v2qi __attribute__ ((vector_size (2))); > + v2qi v =3D *(v2qi*)in; > + *(v2qi*)out =3D v; > + > + We prefer scalar load/store instead of vle.v/vse.v when > + the VLS modes size is smaller scalar mode. */ > + machine_mode mode; > + unsigned size =3D GET_MODE_BITSIZE (mode).to_constant (); > + if (FLOAT_MODE_P (mode)) > + mode =3D mode_for_size (size, MODE_FLOAT, 0).require (); > + else > + mode =3D mode_for_size (size, MODE_INT, 0).require (); > + emit_move_insn (gen_lowpart (mode, operands[0]), > + gen_lowpart (mode, operands[1])); > + } > + else > + { > + operands[1] =3D force_reg (mode, operands[1]); > + emit_move_insn (operands[0], operands[1]); > + } > + DONE; > + } > +) > + > +(define_insn_and_split "*mov" > + [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=3Dvr, m, vr"= ) > + (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))] > + "TARGET_VECTOR > + && (register_operand (operands[0], mode) > + || register_operand (operands[1], mode))" > + "@ > + # > + # > + vmv%m1r.v\t%0,%1" > + "&& reload_completed > + && (!register_operand (operands[0], mode) > + || !register_operand (operands[1], mode))" > + [(const_int 0)] > + { > + bool ok_p =3D riscv_vector::legitimize_move (operands[0], operands[1= ]); > + gcc_assert (ok_p); > + DONE; > + } > +) > + > +(define_expand "mov" > + [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand") > + (match_operand:VLS_AVL_REG 1 "general_operand"))] > + "TARGET_VECTOR" > +{ > + bool ok_p =3D riscv_vector::legitimize_move (operands[0], operands[1])= ; > + gcc_assert (ok_p); > + DONE; > +}) > + > +(define_expand "@mov_lra" > + [(parallel > + [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand") > + (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand")) > + (clobber (match_scratch:P 2))])] > + "TARGET_VECTOR && (lra_in_progress || reload_completed)" > +{}) > + > +(define_insn_and_split "*mov_lra" > + [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=3Dvr, m,vr") > + (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr")) > + (clobber (match_scratch:P 2 "=3D&r,&r,X"))] > + "TARGET_VECTOR && (lra_in_progress || reload_completed) > + && (register_operand (operands[0], mode) > + || register_operand (operands[1], mode))" > + "#" > + "&& reload_completed" > + [(const_int 0)] > +{ > + if (REG_P (operands[0]) && REG_P (operands[1])) > + emit_insn (gen_rtx_SET (operands[0], operands[1])); > + else > + { > + emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (mode), > + Pmode)); > + riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (mode), > + riscv_vector::RVV_UNOP, operands,= operands[2]); > + } > + DONE; > +}) > + > +(define_insn "*mov_vls" > + [(set (match_operand:VLS 0 "register_operand" "=3Dvr") > + (match_operand:VLS 1 "register_operand" " vr"))] > + "TARGET_VECTOR" > + "vmv%m1r.v\t%0,%1" > + [(set_attr "type" "vmov") > + (set_attr "mode" "")]) > diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-mo= des.def > index d6b90e9e304..e3c6ccb2809 100644 > --- a/gcc/config/riscv/riscv-modes.def > +++ b/gcc/config/riscv/riscv-modes.def > @@ -309,6 +309,90 @@ RVV_NF4_MODES (4) > > RVV_NF2_MODES (2) > > +/* VLS modes used as SIMD auto-vectorization for epilogue. We know the > + return type of GET_MODE_BITSIZE is poly_uint16 or unsigned short. > + The maximum bitsize of all vector modes is 65536 =3D (8192 (LMUL1) * = 8), > + even though RISC-V 'V' ISA spec allow maximum bitsize =3D 65536 * 8. > + > + Note: We don't enable of vector modes of TI/TF. */ > + > +VECTOR_BOOL_MODE (V1BI, 1, BI, 1); /* V1BI */ > +VECTOR_BOOL_MODE (V2BI, 2, BI, 1); /* V2BI */ > +VECTOR_BOOL_MODE (V4BI, 4, BI, 1); /* V4BI */ > +VECTOR_BOOL_MODE (V8BI, 8, BI, 1); /* V8BI */ > +VECTOR_BOOL_MODE (V16BI, 16, BI, 2); /* V16BI */ > +VECTOR_BOOL_MODE (V32BI, 32, BI, 4); /* V32BI */ > +VECTOR_BOOL_MODE (V64BI, 64, BI, 8); /* V64BI */ > +VECTOR_BOOL_MODE (V128BI, 128, BI, 16); /* V128BI */ > +VECTOR_BOOL_MODE (V256BI, 256, BI, 32); /* V256BI */ > +VECTOR_BOOL_MODE (V512BI, 512, BI, 64); /* V512BI */ > +VECTOR_BOOL_MODE (V1024BI, 1024, BI, 128); /* V1024BI */ > +VECTOR_BOOL_MODE (V2048BI, 2048, BI, 256); /* V2048BI */ > +VECTOR_BOOL_MODE (V4096BI, 4096, BI, 512); /* V4096BI */ > + > +ADJUST_ALIGNMENT (V1BI, 1); > +ADJUST_ALIGNMENT (V2BI, 1); > +ADJUST_ALIGNMENT (V4BI, 1); > +ADJUST_ALIGNMENT (V8BI, 1); > +ADJUST_ALIGNMENT (V16BI, 1); > +ADJUST_ALIGNMENT (V32BI, 1); > +ADJUST_ALIGNMENT (V64BI, 1); > +ADJUST_ALIGNMENT (V128BI, 1); > +ADJUST_ALIGNMENT (V256BI, 1); > +ADJUST_ALIGNMENT (V512BI, 1); > +ADJUST_ALIGNMENT (V1024BI, 1); > +ADJUST_ALIGNMENT (V2048BI, 1); > +ADJUST_ALIGNMENT (V4096BI, 1); > + > +ADJUST_PRECISION (V1BI, 1); > +ADJUST_PRECISION (V2BI, 2); > +ADJUST_PRECISION (V4BI, 4); > +ADJUST_PRECISION (V8BI, 8); > +ADJUST_PRECISION (V16BI, 16); > +ADJUST_PRECISION (V32BI, 32); > +ADJUST_PRECISION (V64BI, 64); > +ADJUST_PRECISION (V128BI, 128); > +ADJUST_PRECISION (V256BI, 256); > +ADJUST_PRECISION (V512BI, 512); > +ADJUST_PRECISION (V1024BI, 1024); > +ADJUST_PRECISION (V2048BI, 2048); > +ADJUST_PRECISION (V4096BI, 4096); > + > +#define VLS_MODES(NBYTES) = \ > + VECTOR_MODE_WITH_PREFIX (V, INT, QI, NBYTES, 1); = \ > + VECTOR_MODE_WITH_PREFIX (V, INT, HI, NBYTES / 2, 1); = \ > + VECTOR_MODE_WITH_PREFIX (V, INT, SI, NBYTES / 4, 1); = \ > + VECTOR_MODE_WITH_PREFIX (V, INT, DI, NBYTES / 8, 1); = \ > + VECTOR_MODE_WITH_PREFIX (V, FLOAT, HF, NBYTES / 2, 1); = \ > + VECTOR_MODE_WITH_PREFIX (V, FLOAT, SF, NBYTES / 4, 1); = \ > + VECTOR_MODE_WITH_PREFIX (V, FLOAT, DF, NBYTES / 8, 1); > + > +VECTOR_MODE_WITH_PREFIX (V, INT, QI, 1, 1); /* V1QI */ > +VECTOR_MODE_WITH_PREFIX (V, INT, HI, 1, 1); /* V1HI */ > +VECTOR_MODE_WITH_PREFIX (V, INT, SI, 1, 1); /* V1SI */ > +VECTOR_MODE_WITH_PREFIX (V, INT, DI, 1, 1); /* V1DI */ > +VECTOR_MODE_WITH_PREFIX (V, FLOAT, HF, 1, 1); /* V1HF */ > +VECTOR_MODE_WITH_PREFIX (V, FLOAT, SF, 1, 1); /* V1SF */ > +VECTOR_MODE_WITH_PREFIX (V, FLOAT, DF, 1, 1); /* V1DF */ > +VECTOR_MODE_WITH_PREFIX (V, INT, QI, 2, 1); /* V2QI */ > +VECTOR_MODE_WITH_PREFIX (V, INT, QI, 4, 1); /* V4QI */ > +VECTOR_MODE_WITH_PREFIX (V, INT, QI, 8, 1); /* V8QI */ > +VECTOR_MODE_WITH_PREFIX (V, INT, HI, 2, 1); /* V2HI */ > +VECTOR_MODE_WITH_PREFIX (V, INT, HI, 4, 1); /* V4HI */ > +VECTOR_MODE_WITH_PREFIX (V, FLOAT, HF, 2, 1); /* V2HF */ > +VECTOR_MODE_WITH_PREFIX (V, FLOAT, HF, 4, 1); /* V4HF */ > +VECTOR_MODE_WITH_PREFIX (V, INT, SI, 2, 1); /* V2SI */ > +VECTOR_MODE_WITH_PREFIX (V, FLOAT, SF, 2, 1); /* V2SF */ > +VLS_MODES (16); /* V16QI V8HI V4SI V2DI V8HF V4= SF V2DF */ > +VLS_MODES (32); /* V32QI V16HI V8SI V4DI V16HF V8= SF V4DF */ > +VLS_MODES (64); /* V64QI V32HI V16SI V8DI V32HF V16= SF V8DF */ > +VLS_MODES (128); /* V128QI V64HI V32SI V16DI V64HF V32SF V16= DF */ > +VLS_MODES (256); /* V256QI V128HI V64SI V32DI V128HF V64SF V32= DF */ > +VLS_MODES (512); /* V512QI V256HI V128SI V64DI V256HF V128SF V64= DF */ > +VLS_MODES (1024); /* V1024QI V512HI V256SI V128DI V512HF V256SF V128= DF */ > +VLS_MODES (2048); /* V2048QI V1024HI V512SI V256DI V1024HF V512SF V256= DF */ > +VLS_MODES (4096); /* V4096QI V2048HI V1024SI V512DI V2048HF V1024SF V512= DF */ > + > /* TODO: According to RISC-V 'V' ISA spec, the maximun vector length can > be 65536 for a single vector register which means the vector mode in > GCC can be maximum =3D 65536 * 8 bits (LMUL=3D8). > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.= h > index beee241aa1b..6f3f4c116e0 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -291,4 +291,8 @@ enum riscv_entity > #define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR)= !=3D 0) > #define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != =3D 0) > > +/* We only enable VLS modes for VLA vectorization since fixed length VLM= AX mode > + is the highest priority choice and should not conflict with VLS modes= . */ > +#define TARGET_VECTOR_VLS (riscv_autovec_preference =3D=3D RVV_SCALABLE) > + > #endif /* ! GCC_RISCV_OPTS_H */ > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-pro= tos.h > index 16fb8dabca0..9024dbc487a 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -127,6 +127,7 @@ extern void riscv_reinit (void); > extern poly_uint64 riscv_regmode_natural_size (machine_mode); > extern bool riscv_v_ext_vector_mode_p (machine_mode); > extern bool riscv_v_ext_tuple_mode_p (machine_mode); > +extern bool riscv_v_ext_vls_mode_p (machine_mode); > extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); > extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); > extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index 31575428ecb..19bddf10e1f 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -198,7 +198,17 @@ public: > rtx len =3D m_vl_op; > if (m_vlmax_p) > { > - if (const_vlmax_p (m_dest_mode)) > + if (riscv_v_ext_vls_mode_p (m_dest_mode)) > + { > + /* VLS modes always set VSETVL by > + "vsetvl zero, rs1/imm". */ > + poly_uint64 nunits =3D GET_MODE_NUNITS (m_dest_mode); > + len =3D gen_int_mode (nunits, Pmode); > + if (!satisfies_constraint_K (len)) > + len =3D force_reg (Pmode, len); > + m_vlmax_p =3D false; /* It has became NONVLMAX now. */ > + } > + else if (const_vlmax_p (m_dest_mode)) > { > /* Optimize VLS-VLMAX code gen, we can use vsetivli inste= ad of > the vsetvli to obtain the value of vlmax. */ > @@ -1497,27 +1507,51 @@ legitimize_move (rtx dest, rtx src) > return true; > } > > - /* In order to decrease the memory traffic, we don't use whole registe= r > - * load/store for the LMUL less than 1 and mask mode, so those case wi= ll > - * require one extra general purpose register, but it's not allowed du= ring LRA > - * process, so we have a special move pattern used for LRA, which will= defer > - * the expansion after LRA. */ > - if ((known_lt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR) > - || GET_MODE_CLASS (mode) =3D=3D MODE_VECTOR_BOOL) > - && lra_in_progress) > + if (riscv_v_ext_vls_mode_p (mode)) > { > - emit_insn (gen_mov_lra (mode, Pmode, dest, src)); > - return true; > - } > + if (GET_MODE_NUNITS (mode).to_constant () <=3D 31) > + { > + /* For NUNITS <=3D 31 VLS modes, we don't need extrac > + scalar regisers so we apply the naive (set (op0) (op1)) patt= ern. */ > + if (can_create_pseudo_p ()) > + { > + /* Need to force register if mem <- !reg. */ > + if (MEM_P (dest) && !REG_P (src)) > + src =3D force_reg (mode, src); > > - if (known_ge (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR) > - && GET_MODE_CLASS (mode) !=3D MODE_VECTOR_BOOL) > + return false; > + } > + } > + else if (GET_MODE_NUNITS (mode).to_constant () > 31 && lra_in_prog= ress) > + { > + emit_insn (gen_mov_lra (mode, Pmode, dest, src)); > + return true; > + } > + } > + else > { > - /* Need to force register if mem <- !reg. */ > - if (MEM_P (dest) && !REG_P (src)) > - src =3D force_reg (mode, src); > + /* In order to decrease the memory traffic, we don't use whole reg= ister > + * load/store for the LMUL less than 1 and mask mode, so those cas= e will > + * require one extra general purpose register, but it's not allowe= d during > + * LRA process, so we have a special move pattern used for LRA, wh= ich will > + * defer the expansion after LRA. */ > + if ((known_lt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR) > + || GET_MODE_CLASS (mode) =3D=3D MODE_VECTOR_BOOL) > + && lra_in_progress) > + { > + emit_insn (gen_mov_lra (mode, Pmode, dest, src)); > + return true; > + } > > - return false; > + if (known_ge (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR) > + && GET_MODE_CLASS (mode) !=3D MODE_VECTOR_BOOL) > + { > + /* Need to force register if mem <- !reg. */ > + if (MEM_P (dest) && !REG_P (src)) > + src =3D force_reg (mode, src); > + > + return false; > + } > } > > if (register_operand (src, mode) && register_operand (dest, mode)) > @@ -1576,6 +1610,61 @@ static mode_vtype_group mode_vtype_infos; > enum vlmul_type > get_vlmul (machine_mode mode) > { > + /* For VLS modes, the vlmul should be dynamically > + calculated since we need to adjust VLMUL according > + to TARGET_MIN_VLEN. */ > + if (riscv_v_ext_vls_mode_p (mode)) > + { > + int size =3D GET_MODE_BITSIZE (mode).to_constant (); > + int inner_size =3D GET_MODE_BITSIZE (GET_MODE_INNER (mode)); > + if (size < TARGET_MIN_VLEN) > + { > + int factor =3D TARGET_MIN_VLEN / size; > + if (inner_size =3D=3D 8) > + factor =3D MIN (factor, 8); > + else if (inner_size =3D=3D 16) > + factor =3D MIN (factor, 4); > + else if (inner_size =3D=3D 32) > + factor =3D MIN (factor, 2); > + else if (inner_size =3D=3D 64) > + factor =3D MIN (factor, 1); > + else > + gcc_unreachable (); > + > + switch (factor) > + { > + case 1: > + return LMUL_1; > + case 2: > + return LMUL_F2; > + case 4: > + return LMUL_F4; > + case 8: > + return LMUL_F8; > + > + default: > + gcc_unreachable (); > + } > + } > + else > + { > + int factor =3D size / TARGET_MIN_VLEN; > + switch (factor) > + { > + case 1: > + return LMUL_1; > + case 2: > + return LMUL_2; > + case 4: > + return LMUL_4; > + case 8: > + return LMUL_8; > + > + default: > + gcc_unreachable (); > + } > + } > + } > return mode_vtype_infos.vlmul[mode]; > } > > @@ -1603,6 +1692,31 @@ get_subpart_mode (machine_mode mode) > unsigned int > get_ratio (machine_mode mode) > { > + if (riscv_v_ext_vls_mode_p (mode)) > + { > + unsigned int sew =3D get_sew (mode); > + vlmul_type vlmul =3D get_vlmul (mode); > + switch (vlmul) > + { > + case LMUL_1: > + return sew; > + case LMUL_2: > + return sew / 2; > + case LMUL_4: > + return sew / 4; > + case LMUL_8: > + return sew / 8; > + case LMUL_F8: > + return sew * 8; > + case LMUL_F4: > + return sew * 4; > + case LMUL_F2: > + return sew * 2; > + > + default: > + gcc_unreachable (); > + } > + } > return mode_vtype_infos.ratio[mode]; > } > > @@ -1689,7 +1803,8 @@ get_vector_mode (scalar_mode inner_mode, poly_uint6= 4 nunits) > FOR_EACH_MODE_IN_CLASS (mode, mclass) > if (inner_mode =3D=3D GET_MODE_INNER (mode) > && known_eq (nunits, GET_MODE_NUNITS (mode)) > - && riscv_v_ext_vector_mode_p (mode)) > + && (riscv_v_ext_vector_mode_p (mode) > + || riscv_v_ext_vls_mode_p (mode))) > return mode; > return opt_machine_mode (); > } > diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/= riscv-vector-switch.def > index c83e2eff6b6..c035dc3558b 100644 > --- a/gcc/config/riscv/riscv-vector-switch.def > +++ b/gcc/config/riscv/riscv-vector-switch.def > @@ -286,5 +286,107 @@ TUPLE_ENTRY (RVVM4x2DF, TARGET_VECTOR_ELEN_FP_64, R= VVM4DF, 2, LMUL_4, 4) > TUPLE_ENTRY (RVVM2x2DF, TARGET_VECTOR_ELEN_FP_64, RVVM2DF, 2, LMUL_2, 8) > TUPLE_ENTRY (RVVM1x2DF, TARGET_VECTOR_ELEN_FP_64, RVVM1DF, 2, LMUL_1, 16= ) > > +#ifndef VLS_ENTRY > +#define VLS_ENTRY(MODE, REQUIREMENT) > +#endif > + > +/* This following VLS modes should satisfy the constraint: > + GET_MODE_BITSIZE (MODE) <=3D TARGET_MIN_VLEN * 8. */ > +VLS_ENTRY (V1BI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V2BI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V4BI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V8BI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V16BI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V32BI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V64BI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64) > +VLS_ENTRY (V128BI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128) > +VLS_ENTRY (V256BI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256) > +VLS_ENTRY (V512BI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512) > +VLS_ENTRY (V1024BI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024) > +VLS_ENTRY (V2048BI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048) > +VLS_ENTRY (V4096BI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096) > + > +VLS_ENTRY (V1QI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V2QI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V4QI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V8QI, TARGET_VECTOR_VLS && TARGET_64BIT) > +VLS_ENTRY (V16QI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V32QI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V64QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64) > +VLS_ENTRY (V128QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128) > +VLS_ENTRY (V256QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256) > +VLS_ENTRY (V512QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512) > +VLS_ENTRY (V1024QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024) > +VLS_ENTRY (V2048QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048) > +VLS_ENTRY (V4096QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096) > +VLS_ENTRY (V1HI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V2HI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V4HI, TARGET_VECTOR_VLS && TARGET_64BIT) > +VLS_ENTRY (V8HI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V16HI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V32HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64) > +VLS_ENTRY (V64HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128) > +VLS_ENTRY (V128HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256) > +VLS_ENTRY (V256HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512) > +VLS_ENTRY (V512HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024) > +VLS_ENTRY (V1024HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048) > +VLS_ENTRY (V2048HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096) > +VLS_ENTRY (V1SI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V2SI, TARGET_VECTOR_VLS && TARGET_64BIT) > +VLS_ENTRY (V4SI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V8SI, TARGET_VECTOR_VLS) > +VLS_ENTRY (V16SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64) > +VLS_ENTRY (V32SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128) > +VLS_ENTRY (V64SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256) > +VLS_ENTRY (V128SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512) > +VLS_ENTRY (V256SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024) > +VLS_ENTRY (V512SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048) > +VLS_ENTRY (V1024SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096) > +VLS_ENTRY (V1DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_64= BIT) > +VLS_ENTRY (V2DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64) > +VLS_ENTRY (V4DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64) > +VLS_ENTRY (V8DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MI= N_VLEN >=3D 64) > +VLS_ENTRY (V16DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_M= IN_VLEN >=3D 128) > +VLS_ENTRY (V32DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_M= IN_VLEN >=3D 256) > +VLS_ENTRY (V64DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_M= IN_VLEN >=3D 512) > +VLS_ENTRY (V128DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_= MIN_VLEN >=3D 1024) > +VLS_ENTRY (V256DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_= MIN_VLEN >=3D 2048) > +VLS_ENTRY (V512DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_= MIN_VLEN >=3D 4096) > + > +VLS_ENTRY (V1HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16) > +VLS_ENTRY (V2HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16) > +VLS_ENTRY (V4HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16) > +VLS_ENTRY (V8HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16) > +VLS_ENTRY (V16HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16) > +VLS_ENTRY (V32HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGE= T_MIN_VLEN >=3D 64) > +VLS_ENTRY (V64HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGE= T_MIN_VLEN >=3D 128) > +VLS_ENTRY (V128HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARG= ET_MIN_VLEN >=3D 256) > +VLS_ENTRY (V256HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARG= ET_MIN_VLEN >=3D 512) > +VLS_ENTRY (V512HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARG= ET_MIN_VLEN >=3D 1024) > +VLS_ENTRY (V1024HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TAR= GET_MIN_VLEN >=3D 2048) > +VLS_ENTRY (V2048HF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TAR= GET_MIN_VLEN >=3D 4096) > +VLS_ENTRY (V1SF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32) > +VLS_ENTRY (V2SF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32) > +VLS_ENTRY (V4SF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32) > +VLS_ENTRY (V8SF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32) > +VLS_ENTRY (V16SF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGE= T_MIN_VLEN >=3D 64) > +VLS_ENTRY (V32SF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGE= T_MIN_VLEN >=3D 128) > +VLS_ENTRY (V64SF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGE= T_MIN_VLEN >=3D 256) > +VLS_ENTRY (V128SF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARG= ET_MIN_VLEN >=3D 512) > +VLS_ENTRY (V256SF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARG= ET_MIN_VLEN >=3D 1024) > +VLS_ENTRY (V512SF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARG= ET_MIN_VLEN >=3D 2048) > +VLS_ENTRY (V1024SF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TAR= GET_MIN_VLEN >=3D 4096) > +VLS_ENTRY (V1DF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64) > +VLS_ENTRY (V2DF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64) > +VLS_ENTRY (V4DF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64) > +VLS_ENTRY (V8DF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET= _MIN_VLEN >=3D 64) > +VLS_ENTRY (V16DF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGE= T_MIN_VLEN >=3D 128) > +VLS_ENTRY (V32DF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGE= T_MIN_VLEN >=3D 256) > +VLS_ENTRY (V64DF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGE= T_MIN_VLEN >=3D 512) > +VLS_ENTRY (V128DF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARG= ET_MIN_VLEN >=3D 1024) > +VLS_ENTRY (V256DF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARG= ET_MIN_VLEN >=3D 2048) > +VLS_ENTRY (V512DF, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARG= ET_MIN_VLEN >=3D 4096) > + > +#undef VLS_ENTRY > #undef TUPLE_ENTRY > #undef ENTRY > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 332fa720f01..3a450d6bf91 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -1009,12 +1009,31 @@ riscv_v_ext_tuple_mode_p (machine_mode mode) > return false; > } > > +/* Return true if mode is the RVV enabled vls mode. */ > + > +bool > +riscv_v_ext_vls_mode_p (machine_mode mode) > +{ > +#define VLS_ENTRY(MODE, REQUIREMENT) = \ > + case MODE##mode: = \ > + return REQUIREMENT; > + switch (mode) > + { > +#include "riscv-vector-switch.def" > + default: > + return false; > + } > + > + return false; > +} > + > /* Return true if it is either RVV vector mode or RVV tuple mode. */ > > static bool > riscv_v_ext_mode_p (machine_mode mode) > { > - return riscv_v_ext_vector_mode_p (mode) || riscv_v_ext_tuple_mode_p (m= ode); > + return riscv_v_ext_vector_mode_p (mode) || riscv_v_ext_tuple_mode_p (m= ode) > + || riscv_v_ext_vls_mode_p (mode); > } > > /* Call from ADJUST_NUNITS in riscv-modes.def. Return the correct > @@ -4554,6 +4573,32 @@ riscv_memmodel_needs_amo_release (enum memmodel mo= del) > } > } > > +/* Get REGNO alignment of vector mode. > + The alignment =3D LMUL when the LMUL >=3D 1. > + Otherwise, alignment =3D 1. */ > +static int > +riscv_get_v_regno_alignment (machine_mode mode) > +{ > + /* 3.3.2. LMUL =3D 2,4,8, register numbers should be multiple of 2,4,8= . > + but for mask vector register, register numbers can be any number. *= / > + int lmul =3D 1; > + machine_mode rvv_mode =3D mode; > + if (riscv_v_ext_vls_mode_p (rvv_mode)) > + { > + int size =3D GET_MODE_BITSIZE (rvv_mode).to_constant (); > + if (size < TARGET_MIN_VLEN) > + return 1; > + else > + return size / TARGET_MIN_VLEN; > + } > + if (riscv_v_ext_tuple_mode_p (rvv_mode)) > + rvv_mode =3D riscv_vector::get_subpart_mode (rvv_mode); > + poly_int64 size =3D GET_MODE_SIZE (rvv_mode); > + if (known_gt (size, UNITS_PER_V_REG)) > + lmul =3D exact_div (size, UNITS_PER_V_REG).to_constant (); > + return lmul; > +} > + > /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are= : > > 'h' Print the high-part relocation associated with OP, after strippin= g > @@ -4641,15 +4686,10 @@ riscv_print_operand (FILE *file, rtx op, int lett= er) > break; > } > case 'm': { > - if (riscv_v_ext_vector_mode_p (mode)) > + if (riscv_v_ext_mode_p (mode)) > { > /* Calculate lmul according to mode and print the value. */ > - poly_int64 size =3D GET_MODE_SIZE (mode); > - unsigned int lmul; > - if (known_lt (size, BYTES_PER_RISCV_VECTOR)) > - lmul =3D 1; > - else > - lmul =3D exact_div (size, BYTES_PER_RISCV_VECTOR).to_consta= nt (); > + int lmul =3D riscv_get_v_regno_alignment (mode); > asm_fprintf (file, "%d", lmul); > } > else if (code =3D=3D CONST_INT) > @@ -6237,6 +6277,16 @@ riscv_hard_regno_nregs (unsigned int regno, machin= e_mode mode) > } > } > > + /* For VLS modes, we allocate registers according to TARGET_MIN_VLEN. = */ > + if (riscv_v_ext_vls_mode_p (mode)) > + { > + int size =3D GET_MODE_SIZE (mode).to_constant (); > + if (size < TARGET_MIN_VLEN) > + return 1; > + else > + return size / TARGET_MIN_VLEN; > + } > + > /* mode for VL or VTYPE are just a marker, not holding value, > so it always consume one register. */ > if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno) > @@ -6296,17 +6346,9 @@ riscv_hard_regno_mode_ok (unsigned int regno, mach= ine_mode mode) > if (!V_REG_P (regno + nregs - 1)) > return false; > > - /* 3.3.2. LMUL =3D 2,4,8, register numbers should be multiple of 2= ,4,8. > - but for mask vector register, register numbers can be any number= . */ > - int lmul =3D 1; > - machine_mode rvv_mode =3D mode; > - if (riscv_v_ext_tuple_mode_p (rvv_mode)) > - rvv_mode =3D riscv_vector::get_subpart_mode (rvv_mode); > - poly_int64 size =3D GET_MODE_SIZE (rvv_mode); > - if (known_gt (size, UNITS_PER_V_REG)) > - lmul =3D exact_div (size, UNITS_PER_V_REG).to_constant (); > - if (lmul !=3D 1) > - return ((regno % lmul) =3D=3D 0); > + int regno_alignment =3D riscv_get_v_regno_alignment (mode); > + if (regno_alignment !=3D 1) > + return ((regno % regno_alignment) =3D=3D 0); > } > else if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno) > || FRM_REG_P (regno)) > @@ -7392,11 +7434,7 @@ riscv_regmode_natural_size (machine_mode mode) > /* ??? For now, only do this for variable-width RVV registers. > Doing it for constant-sized registers breaks lower-subreg.c. */ > > - /* RVV mask modes always consume a single register. */ > - if (GET_MODE_CLASS (mode) =3D=3D MODE_VECTOR_BOOL) > - return BYTES_PER_RISCV_VECTOR; > - > - if (!riscv_vector_chunks.is_constant () && riscv_v_ext_mode_p (mode)) > + if (riscv_v_ext_mode_p (mode)) > { > if (riscv_v_ext_tuple_mode_p (mode)) > { > @@ -7405,7 +7443,14 @@ riscv_regmode_natural_size (machine_mode mode) > if (known_lt (size, BYTES_PER_RISCV_VECTOR)) > return size; > } > - return BYTES_PER_RISCV_VECTOR; > + else if (riscv_v_ext_vector_mode_p (mode)) > + { > + /* RVV mask modes always consume a single register. */ > + if (GET_MODE_CLASS (mode) =3D=3D MODE_VECTOR_BOOL) > + return BYTES_PER_RISCV_VECTOR; > + } > + if (!GET_MODE_SIZE (mode).is_constant ()) > + return BYTES_PER_RISCV_VECTOR; > } > return UNITS_PER_WORD; > } > @@ -7679,7 +7724,7 @@ riscv_preferred_simd_mode (scalar_mode mode) > static poly_uint64 > riscv_vectorize_preferred_vector_alignment (const_tree type) > { > - if (riscv_v_ext_vector_mode_p (TYPE_MODE (type))) > + if (riscv_v_ext_mode_p (TYPE_MODE (type))) > return TYPE_ALIGN (TREE_TYPE (type)); > return TYPE_ALIGN (type); > } > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 4615e811947..b24a48b801c 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -216,7 +216,15 @@ > RVVM4x2DI,RVVM2x2DI,RVVM1x2DI,RVVM1x8DF, > RVVM1x7DF,RVVM1x6DF,RVVM1x5DF,RVVM2x4DF, > RVVM1x4DF,RVVM2x3DF,RVVM1x3DF,RVVM4x2DF, > - RVVM2x2DF,RVVM1x2DF" > + RVVM2x2DF,RVVM1x2DF, > + VNx2x1DF,VNx3x1DF,VNx4x1DF,VNx5x1DF,VNx6x1DF,VNx7x1DF,VNx8x1DF, > + V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V20= 48QI,V4096QI, > + V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V256HI,V512HI,V1024HI,V20= 48HI, > + V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V256SI,V512SI,V1024SI, > + V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V256DI,V512DI, > + V1HF,V2HF,V4HF,V8HF,V16HF,V32HF,V64HF,V128HF,V256HF,V512HF,V1024HF,V20= 48HF, > + V1SF,V2SF,V4SF,V8SF,V16SF,V32SF,V64SF,V128SF,V256SF,V512SF,V1024SF, > + V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V256DF,V512DF" > (const_string "unknown")) > > ;; True if the main data type is twice the size of a word. > diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vect= or-iterators.md > index e277e8785cf..e64cd4535d2 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -108,6 +108,108 @@ > (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_6= 4") > ]) > > +(define_mode_iterator V_VLS [ > + RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MI= N_VLEN > 32") > + > + RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > = 32") > + > + (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_1= 6") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") > + (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_= 16") > + (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > + > + RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") > + > + (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_3= 2") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") > + (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_= 32 && TARGET_MIN_VLEN > 32") > + > + (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") > + (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > + > + (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_6= 4") > + (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_6= 4") > + > + ;; VLS modes. > + (V1QI "TARGET_VECTOR_VLS") > + (V2QI "TARGET_VECTOR_VLS") > + (V4QI "TARGET_VECTOR_VLS") > + (V8QI "TARGET_VECTOR_VLS") > + (V16QI "TARGET_VECTOR_VLS") > + (V32QI "TARGET_VECTOR_VLS") > + (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V1HI "TARGET_VECTOR_VLS") > + (V2HI "TARGET_VECTOR_VLS") > + (V4HI "TARGET_VECTOR_VLS") > + (V8HI "TARGET_VECTOR_VLS") > + (V16HI "TARGET_VECTOR_VLS") > + (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V1SI "TARGET_VECTOR_VLS") > + (V2SI "TARGET_VECTOR_VLS") > + (V4SI "TARGET_VECTOR_VLS") > + (V8SI "TARGET_VECTOR_VLS") > + (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= =3D 64") > + (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 128") > + (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 256") > + (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 512") > + (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 1024") > + (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 2048") > + (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 4096") > + (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VL= EN >=3D 64") > + (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VL= EN >=3D 128") > + (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 256") > + (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 512") > + (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 1024") > + (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_= VLEN >=3D 2048") > + (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_= VLEN >=3D 4096") > + (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 64") > + (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 128") > + (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 256") > + (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 512") > + (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 1024") > + (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 2048") > + (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_= VLEN >=3D 4096") > + (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") > + (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") > + (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") > + (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLE= N >=3D 64") > + (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 128") > + (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 256") > + (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 512") > + (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 1024") > + (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 2048") > + (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 4096") > +]) > + > (define_mode_iterator VEEWEXT2 [ > RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > = 32") > > @@ -285,6 +387,64 @@ > (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > ]) > > +(define_mode_iterator V_VLSI [ > + RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MI= N_VLEN > 32") > + > + RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > = 32") > + > + RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") > + > + (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") > + (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > + > + (V1QI "TARGET_VECTOR_VLS") > + (V2QI "TARGET_VECTOR_VLS") > + (V4QI "TARGET_VECTOR_VLS") > + (V8QI "TARGET_VECTOR_VLS") > + (V16QI "TARGET_VECTOR_VLS") > + (V32QI "TARGET_VECTOR_VLS") > + (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V1HI "TARGET_VECTOR_VLS") > + (V2HI "TARGET_VECTOR_VLS") > + (V4HI "TARGET_VECTOR_VLS") > + (V8HI "TARGET_VECTOR_VLS") > + (V16HI "TARGET_VECTOR_VLS") > + (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V1SI "TARGET_VECTOR_VLS") > + (V2SI "TARGET_VECTOR_VLS") > + (V4SI "TARGET_VECTOR_VLS") > + (V8SI "TARGET_VECTOR_VLS") > + (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= =3D 64") > + (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 128") > + (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 256") > + (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 512") > + (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 1024") > + (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 2048") > + (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 4096") > +]) > + > (define_mode_iterator VF_ZVFHMIN [ > (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_1= 6") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") > (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_= 16") > @@ -297,6 +457,49 @@ > (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_6= 4") > ]) > > +(define_mode_iterator V_VLSF_ZVFHMIN [ > + (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_1= 6") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") > + (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_= 16") > + (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > + > + (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_3= 2") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") > + (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_= 32 && TARGET_MIN_VLEN > 32") > + > + (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_6= 4") > + (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_6= 4") > + > + (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VL= EN >=3D 64") > + (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VL= EN >=3D 128") > + (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 256") > + (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 512") > + (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 1024") > + (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_= VLEN >=3D 2048") > + (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_= VLEN >=3D 4096") > + (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 64") > + (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 128") > + (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 256") > + (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 512") > + (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 1024") > + (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 2048") > + (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_= VLEN >=3D 4096") > + (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") > + (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") > + (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLE= N >=3D 64") > + (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 128") > + (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 256") > + (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 512") > + (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 1024") > + (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 2048") > + (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 4096") > +]) > + > ;; This iterator is the same as above but with TARGET_VECTOR_ELEN_FP_16 > ;; changed to TARGET_ZVFH. TARGET_VECTOR_ELEN_FP_16 is also true for > ;; TARGET_ZVFHMIN while we actually want to disable all instructions apa= rt > @@ -345,6 +548,21 @@ > (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > ]) > > +(define_mode_iterator V_VLSI_D [ > + (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") > + (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > + > + (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= =3D 64") > + (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 128") > + (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 256") > + (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 512") > + (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 1024") > + (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 2048") > + (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 4096") > +]) > + > (define_mode_iterator VFULLI_D [ > (RVVM8DI "TARGET_FULL_V") (RVVM4DI "TARGET_FULL_V") > (RVVM2DI "TARGET_FULL_V") (RVVM1DI "TARGET_FULL_V") > @@ -966,6 +1184,27 @@ > (RVVM4x2DF "RVVMF16BI") > (RVVM2x2DF "RVVMF32BI") > (RVVM1x2DF "RVVMF64BI") > + > + ;; VLS modes. > + (V1QI "V1BI") (V2QI "V2BI") (V4QI "V4BI") (V8QI "V8BI") (V16QI "V16BI"= ) (V32QI "V32BI") > + (V64QI "V64BI") (V128QI "V128BI") (V256QI "V256BI") (V512QI "V512BI") > + (V1024QI "V1024BI") (V2048QI "V2048BI") (V4096QI "V4096BI") > + (V1HI "V1BI") (V2HI "V2BI") (V4HI "V4BI") (V8HI "V8BI") (V16HI "V16BI"= ) > + (V32HI "V32BI") (V64HI "V64BI") (V128HI "V128BI") (V256HI "V256BI") > + (V512HI "V512BI") (V1024HI "V1024BI") (V2048HI "V2048BI") > + (V1SI "V1BI") (V2SI "V2BI") (V4SI "V4BI") (V8SI "V8BI") > + (V16SI "V16BI") (V32SI "V32BI") (V64SI "V64BI") > + (V128SI "V128BI") (V256SI "V256BI") (V512SI "V512BI") (V1024SI "V1024B= I") > + (V1DI "V1BI") (V2DI "V2BI") (V4DI "V4BI") (V8DI "V8BI") (V16DI "V16BI"= ) (V32DI "V32BI") > + (V64DI "V64BI") (V128DI "V128BI") (V256DI "V256BI") (V512DI "V512BI") > + (V1HF "V1BI") (V2HF "V2BI") (V4HF "V4BI") (V8HF "V8BI") (V16HF "V16BI"= ) > + (V32HF "V32BI") (V64HF "V64BI") (V128HF "V128BI") (V256HF "V256BI") > + (V512HF "V512BI") (V1024HF "V1024BI") (V2048HF "V2048BI") > + (V1SF "V1BI") (V2SF "V2BI") (V4SF "V4BI") (V8SF "V8BI") > + (V16SF "V16BI") (V32SF "V32BI") (V64SF "V64BI") > + (V128SF "V128BI") (V256SF "V256BI") (V512SF "V512BI") (V1024SF "V1024B= I") > + (V1DF "V1BI") (V2DF "V2BI") (V4DF "V4BI") (V8DF "V8BI") (V16DF "V16BI"= ) (V32DF "V32BI") > + (V64DF "V64BI") (V128DF "V128BI") (V256DF "V256BI") (V512DF "V512BI") > ]) > > (define_mode_attr vm [ > @@ -1046,6 +1285,27 @@ > (RVVM4x2DF "rvvmf16bi") > (RVVM2x2DF "rvvmf32bi") > (RVVM1x2DF "rvvmf64bi") > + > + ;; VLS modes. > + (V1QI "v1bi") (V2QI "v2bi") (V4QI "v4bi") (V8QI "v8bi") (V16QI "v16bi"= ) (V32QI "v32bi") > + (V64QI "v64bi") (V128QI "v128bi") (V256QI "v256bi") (V512QI "v512bi") > + (V1024QI "v1024bi") (V2048QI "v2048bi") (V4096QI "v4096bi") > + (V1HI "v1bi") (V2HI "v2bi") (V4HI "v4bi") (V8HI "v8bi") (V16HI "v16bi"= ) > + (V32HI "v32bi") (V64HI "v64bi") (V128HI "v128bi") (V256HI "v256bi") > + (V512HI "v512bi") (V1024HI "v1024bi") (V2048HI "v2048bi") > + (V1SI "v1bi") (V2SI "v2bi") (V4SI "v4bi") (V8SI "v8bi") > + (V16SI "v16bi") (V32SI "v32bi") (V64SI "v64bi") > + (V128SI "v128bi") (V256SI "v256bi") (V512SI "v512bi") (V1024SI "v1024b= i") > + (V1DI "v1bi") (V2DI "v2bi") (V4DI "v4bi") (V8DI "v8bi") (V16DI "v16bi"= ) (V32DI "v32bi") > + (V64DI "v64bi") (V128DI "v128bi") (V256DI "v256bi") (V512DI "v512bi") > + (V1HF "v1bi") (V2HF "v2bi") (V4HF "v4bi") (V8HF "v8bi") (V16HF "v16bi"= ) > + (V32HF "v32bi") (V64HF "v64bi") (V128HF "v128bi") (V256HF "v256bi") > + (V512HF "v512bi") (V1024HF "v1024bi") (V2048HF "v2048bi") > + (V1SF "v1bi") (V2SF "v2bi") (V4SF "v4bi") (V8SF "v8bi") > + (V16SF "v16bi") (V32SF "v32bi") (V64SF "v64bi") > + (V128SF "v128bi") (V256SF "v256bi") (V512SF "v512bi") (V1024SF "v1024b= i") > + (V1DF "v1bi") (V2DF "v2bi") (V4DF "v4bi") (V8DF "v8bi") (V16DF "v16bi"= ) (V32DF "v32bi") > + (V64DF "v64bi") (V128DF "v128bi") (V256DF "v256bi") (V512DF "v512bi") > ]) > > (define_mode_attr VEL [ > @@ -1062,6 +1322,20 @@ > (RVVM8DI "DI") (RVVM4DI "DI") (RVVM2DI "DI") (RVVM1DI "DI") > > (RVVM8DF "DF") (RVVM4DF "DF") (RVVM2DF "DF") (RVVM1DF "DF") > + > + ;; VLS modes. > + (V1QI "QI") (V2QI "QI") (V4QI "QI") (V8QI "QI") (V16QI "QI") (V32QI "Q= I") (V64QI "QI") (V128QI "QI") (V256QI "QI") (V512QI "QI") > + (V1024QI "QI") (V2048QI "QI") (V4096QI "QI") > + (V1HI "HI") (V2HI "HI") (V4HI "HI") (V8HI "HI") (V16HI "HI") (V32HI "H= I") (V64HI "HI") (V128HI "HI") (V256HI "HI") > + (V512HI "HI") (V1024HI "HI") (V2048HI "HI") > + (V1SI "SI") (V2SI "SI") (V4SI "SI") (V8SI "SI") (V16SI "SI") (V32SI "S= I") (V64SI "SI") (V128SI "SI") (V256SI "SI") > + (V512SI "SI") (V1024SI "SI") > + (V1DI "DI") (V2DI "DI") (V4DI "DI") (V8DI "DI") (V16DI "DI") (V32DI "D= I") (V64DI "DI") (V128DI "DI") (V256DI "DI") (V512DI "DI") > + (V1HF "HF") (V2HF "HF") (V4HF "HF") (V8HF "HF") (V16HF "HF") (V32HF "H= F") (V64HF "HF") (V128HF "HF") (V256HF "HF") > + (V512HF "HF") (V1024HF "HF") (V2048HF "HF") > + (V1SF "SF") (V2SF "SF") (V4SF "SF") (V8SF "SF") (V16SF "SF") (V32SF "S= F") (V64SF "SF") (V128SF "SF") (V256SF "SF") > + (V512SF "SF") (V1024SF "SF") > + (V1DF "DF") (V2DF "DF") (V4DF "DF") (V8DF "DF") (V16DF "DF") (V32DF "D= F") (V64DF "DF") (V128DF "DF") (V256DF "DF") (V512DF "DF") > ]) > > (define_mode_attr vel [ > @@ -1078,6 +1352,20 @@ > (RVVM8DI "di") (RVVM4DI "di") (RVVM2DI "di") (RVVM1DI "di") > > (RVVM8DF "df") (RVVM4DF "df") (RVVM2DF "df") (RVVM1DF "df") > + > + ;; VLS modes. > + (V1QI "qi") (V2QI "qi") (V4QI "qi") (V8QI "qi") (V16QI "qi") (V32QI "q= i") (V64QI "qi") (V128QI "qi") (V256QI "qi") (V512QI "qi") > + (V1024QI "qi") (V2048QI "qi") (V4096QI "qi") > + (V1HI "hi") (V2HI "hi") (V4HI "hi") (V8HI "hi") (V16HI "hi") (V32HI "h= i") (V64HI "hi") (V128HI "hi") (V256HI "hi") > + (V512HI "hi") (V1024HI "hi") (V2048HI "hi") > + (V1SI "si") (V2SI "si") (V4SI "si") (V8SI "si") (V16SI "si") (V32SI "s= i") (V64SI "si") (V128SI "si") (V256SI "si") > + (V512SI "si") (V1024SI "si") > + (V1DI "di") (V2DI "di") (V4DI "di") (V8DI "di") (V16DI "di") (V32DI "d= i") (V64DI "di") (V128DI "di") (V256DI "di") (V512DI "di") > + (V1HF "hf") (V2HF "hf") (V4HF "hf") (V8HF "hf") (V16HF "hf") (V32HF "h= f") (V64HF "hf") (V128HF "hf") (V256HF "hf") > + (V512HF "hf") (V1024HF "hf") (V2048HF "hf") > + (V1SF "sf") (V2SF "sf") (V4SF "sf") (V8SF "sf") (V16SF "sf") (V32SF "s= f") (V64SF "sf") (V128SF "sf") (V256SF "sf") > + (V512SF "sf") (V1024SF "sf") > + (V1DF "df") (V2DF "df") (V4DF "df") (V8DF "df") (V16DF "df") (V32DF "d= f") (V64DF "df") (V128DF "df") (V256DF "df") (V512DF "df") > ]) > > (define_mode_attr VSUBEL [ > @@ -1090,6 +1378,13 @@ > (RVVM8DI "SI") (RVVM4DI "SI") (RVVM2DI "SI") (RVVM1DI "SI") > > (RVVM8DF "SF") (RVVM4DF "SF") (RVVM2DF "SF") (RVVM1DF "SF") > + > + ;; VLS modes. > + (V2HI "QI") (V4HI "QI") (V8HI "QI") (V16HI "QI") (V32HI "QI") (V64HI "= QI") (V128HI "QI") (V256HI "QI") > + (V512HI "QI") (V1024HI "QI") (V2048HI "QI") > + (V2SI "HI") (V4SI "HI") (V8SI "HI") (V16SI "HI") (V32SI "HI") (V64SI "= HI") (V128SI "HI") (V256SI "HI") > + (V512SI "HI") (V1024SI "HI") > + (V2DI "SI") (V4DI "SI") (V8DI "SI") (V16DI "SI") (V32DI "SI") (V64DI "= SI") (V128DI "SI") (V256DI "SI") (V512DI "SI") > ]) > > (define_mode_attr nf [ > @@ -1236,6 +1531,20 @@ > (RVVM4x2DF "64") > (RVVM2x2DF "64") > (RVVM1x2DF "64") > + > + ;; VLS modes. > + (V1QI "8") (V2QI "8") (V4QI "8") (V8QI "8") (V16QI "8") (V32QI "8") (V= 64QI "8") (V128QI "8") (V256QI "8") (V512QI "8") > + (V1024QI "8") (V2048QI "8") (V4096QI "8") > + (V1HI "16") (V2HI "16") (V4HI "16") (V8HI "16") (V16HI "16") (V32HI "1= 6") (V64HI "16") (V128HI "16") (V256HI "16") > + (V512HI "16") (V1024HI "16") (V2048HI "16") > + (V1SI "32") (V2SI "32") (V4SI "32") (V8SI "32") (V16SI "32") (V32SI "3= 2") (V64SI "32") (V128SI "32") (V256SI "32") > + (V512SI "32") (V1024SI "32") > + (V1DI "64") (V2DI "64") (V4DI "64") (V8DI "64") (V16DI "64") (V32DI "6= 4") (V64DI "64") (V128DI "64") (V256DI "64") (V512DI "64") > + (V1HF "16") (V2HF "16") (V4HF "16") (V8HF "16") (V16HF "16") (V32HF "1= 6") (V64HF "16") (V128HF "16") (V256HF "16") > + (V512HF "16") (V1024HF "16") (V2048HF "16") > + (V1SF "32") (V2SF "32") (V4SF "32") (V8SF "32") (V16SF "32") (V32SF "3= 2") (V64SF "32") (V128SF "32") (V256SF "32") > + (V512SF "32") (V1024SF "32") > + (V1DF "64") (V2DF "64") (V4DF "64") (V8DF "64") (V16DF "64") (V32DF "6= 4") (V64DF "64") (V128DF "64") (V256DF "64") (V512DF "64") > ]) > > (define_mode_attr double_trunc_sew [ > @@ -1815,3 +2124,170 @@ > (mult "%3,%4")]) > > (define_code_attr sz [(sign_extend "s") (zero_extend "z")]) > + > +;; VLS modes. > +(define_mode_iterator VLS [ > + (V1QI "TARGET_VECTOR_VLS") > + (V2QI "TARGET_VECTOR_VLS") > + (V4QI "TARGET_VECTOR_VLS") > + (V8QI "TARGET_VECTOR_VLS") > + (V16QI "TARGET_VECTOR_VLS") > + (V32QI "TARGET_VECTOR_VLS") > + (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V1HI "TARGET_VECTOR_VLS") > + (V2HI "TARGET_VECTOR_VLS") > + (V4HI "TARGET_VECTOR_VLS") > + (V8HI "TARGET_VECTOR_VLS") > + (V16HI "TARGET_VECTOR_VLS") > + (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V1SI "TARGET_VECTOR_VLS") > + (V2SI "TARGET_VECTOR_VLS") > + (V4SI "TARGET_VECTOR_VLS") > + (V8SI "TARGET_VECTOR_VLS") > + (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= =3D 64") > + (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 128") > + (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 256") > + (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 512") > + (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 1024") > + (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 2048") > + (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 4096") > + (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VL= EN >=3D 64") > + (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VL= EN >=3D 128") > + (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 256") > + (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 512") > + (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 1024") > + (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_= VLEN >=3D 2048") > + (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_= VLEN >=3D 4096") > + (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 64") > + (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 128") > + (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 256") > + (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 512") > + (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 1024") > + (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 2048") > + (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_= VLEN >=3D 4096") > + (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") > + (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") > + (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") > + (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLE= N >=3D 64") > + (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 128") > + (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 256") > + (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 512") > + (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 1024") > + (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 2048") > + (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 4096")]) > + > +;; VLS modes that has NUNITS < 32. > +(define_mode_iterator VLS_AVL_IMM [ > + (V1QI "TARGET_VECTOR_VLS") > + (V2QI "TARGET_VECTOR_VLS") > + (V4QI "TARGET_VECTOR_VLS") > + (V8QI "TARGET_VECTOR_VLS") > + (V16QI "TARGET_VECTOR_VLS") > + (V1HI "TARGET_VECTOR_VLS") > + (V2HI "TARGET_VECTOR_VLS") > + (V4HI "TARGET_VECTOR_VLS") > + (V8HI "TARGET_VECTOR_VLS") > + (V16HI "TARGET_VECTOR_VLS") > + (V1SI "TARGET_VECTOR_VLS") > + (V2SI "TARGET_VECTOR_VLS") > + (V4SI "TARGET_VECTOR_VLS") > + (V8SI "TARGET_VECTOR_VLS") > + (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64") > + (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= =3D 64") > + (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 128") > + (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") > + (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") > + (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 64") > + (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") > + (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") > + (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") > + (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLE= N >=3D 64") > + (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 128")]) > + > +;; VLS modes that has NUNITS >=3D 32. > +(define_mode_iterator VLS_AVL_REG [ > + (V32QI "TARGET_VECTOR_VLS") > + (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 64") > + (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 128") > + (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 256") > + (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 512") > + (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 1024") > + (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 2048") > + (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >=3D 4096") > + (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 256") > + (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN = >=3D 512") > + (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 1024") > + (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 2048") > + (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN= >=3D 4096") > + (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VL= EN >=3D 64") > + (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VL= EN >=3D 128") > + (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 256") > + (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 512") > + (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V= LEN >=3D 1024") > + (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_= VLEN >=3D 2048") > + (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_= VLEN >=3D 4096") > + (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 128") > + (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VL= EN >=3D 256") > + (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 512") > + (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 1024") > + (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_V= LEN >=3D 2048") > + (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_= VLEN >=3D 4096") > + (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 256") > + (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VL= EN >=3D 512") > + (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 1024") > + (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 2048") > + (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_V= LEN >=3D 4096")]) > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index f745888127c..9c2c3a4dee1 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -25,6 +25,7 @@ > ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc) > ;; - Auto-vectorization (autovec.md) > ;; - Optimization (autovec-opt.md) > +;; - VLS patterns (autovec-vls.md) > > (include "vector-iterators.md") > > @@ -91,7 +92,8 @@ > RVVM1x5QI,RVVMF2x5QI,RVVMF4x5QI,RVVMF8x5QI,\ > RVVM2x4QI,RVVM1x4QI,RVVMF2x4QI,RVVMF4x4QI,RVVMF= 8x4QI,\ > RVVM2x3QI,RVVM1x3QI,RVVMF2x3QI,RVVMF4x3QI,RVVMF= 8x3QI,\ > - RVVM4x2QI,RVVM2x2QI,RVVM1x2QI,RVVMF2x2QI,RVVMF4= x2QI,RVVMF8x2QI") > + RVVM4x2QI,RVVM2x2QI,RVVM1x2QI,RVVMF2x2QI,RVVMF4= x2QI,RVVMF8x2QI,\ > + V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V2= 56QI,V512QI,V1024QI,V2048QI,V4096QI") > (const_int 8) > (eq_attr "mode" "RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4= HI,\ > RVVM1x8HI,RVVMF2x8HI,RVVMF4x8HI,\ > @@ -108,7 +110,9 @@ > RVVM1x5HF,RVVMF2x5HF,RVVMF4x5HF,\ > RVVM2x4HF,RVVM1x4HF,RVVMF2x4HF,RVVMF4x4HF,\ > RVVM2x3HF,RVVM1x3HF,RVVMF2x3HF,RVVMF4x3HF,\ > - RVVM4x2HF,RVVM2x2HF,RVVM1x2HF,RVVMF2x2HF,RVVMF4= x2HF") > + RVVM4x2HF,RVVM2x2HF,RVVM1x2HF,RVVMF2x2HF,RVVMF4= x2HF,\ > + V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V2= 56HI,V512HI,V1024HI,V2048HI,\ > + V1HF,V2HF,V4HF,V8HF,V16HF,V32HF,V64HF,V128HF,V2= 56HF,V512HF,V1024HF,V2048HF") > (const_int 16) > (eq_attr "mode" "RVVM8SI,RVVM4SI,RVVM2SI,RVVM1SI,RVVMF2SI,\ > RVVM8SF,RVVM4SF,RVVM2SF,RVVM1SF,RVVMF2SF,\ > @@ -125,7 +129,9 @@ > RVVM1x5SF,RVVMF2x5SF,\ > RVVM2x4SF,RVVM1x4SF,RVVMF2x4SF,\ > RVVM2x3SF,RVVM1x3SF,RVVMF2x3SF,\ > - RVVM4x2SF,RVVM2x2SF,RVVM1x2SF,RVVMF2x2SF") > + RVVM4x2SF,RVVM2x2SF,RVVM1x2SF,RVVMF2x2SF,\ > + V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V2= 56SI,V512SI,V1024SI,\ > + V1SF,V2SF,V4SF,V8SF,V16SF,V32SF,V64SF,V128SF,V2= 56SF,V512SF,V1024SF") > (const_int 32) > (eq_attr "mode" "RVVM8DI,RVVM4DI,RVVM2DI,RVVM1DI,\ > RVVM8DF,RVVM4DF,RVVM2DF,RVVM1DF,\ > @@ -136,7 +142,9 @@ > RVVM1x8DF,RVVM1x7DF,RVVM1x6DF,RVVM1x5DF,\ > RVVM2x4DF,RVVM1x4DF,\ > RVVM2x3DF,RVVM1x3DF,\ > - RVVM4x2DF,RVVM2x2DF,RVVM1x2DF") > + RVVM4x2DF,RVVM2x2DF,RVVM1x2DF,\ > + V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V2= 56DI,V512DI,\ > + V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V2= 56DF,V512DF") > (const_int 64)] > (const_int INVALID_ATTRIBUTE))) > > @@ -318,7 +326,88 @@ > (eq_attr "mode" "RVVM1x3DF") (symbol_ref "riscv_vector::LMUL_1") > (eq_attr "mode" "RVVM4x2DF") (symbol_ref "riscv_vector::LMUL_4") > (eq_attr "mode" "RVVM2x2DF") (symbol_ref "riscv_vector::LMUL_2") > - (eq_attr "mode" "RVVM1x2DF") (symbol_ref "riscv_vector::LMUL_1")= ] > + (eq_attr "mode" "RVVM1x2DF") (symbol_ref "riscv_vector::LMUL_1") > + > + ;; VLS modes. > + (eq_attr "mode" "V1QI") (symbol_ref "riscv_vector::get_vlmul(E_V= 1QImode)") > + (eq_attr "mode" "V2QI") (symbol_ref "riscv_vector::get_vlmul(E_V= 2QImode)") > + (eq_attr "mode" "V4QI") (symbol_ref "riscv_vector::get_vlmul(E_V= 4QImode)") > + (eq_attr "mode" "V8QI") (symbol_ref "riscv_vector::get_vlmul(E_V= 8QImode)") > + (eq_attr "mode" "V16QI") (symbol_ref "riscv_vector::get_vlmul(E_= V16QImode)") > + (eq_attr "mode" "V32QI") (symbol_ref "riscv_vector::get_vlmul(E_= V32QImode)") > + (eq_attr "mode" "V64QI") (symbol_ref "riscv_vector::get_vlmul(E_= V64QImode)") > + (eq_attr "mode" "V128QI") (symbol_ref "riscv_vector::get_vlmul(E= _V128QImode)") > + (eq_attr "mode" "V256QI") (symbol_ref "riscv_vector::get_vlmul(E= _V256QImode)") > + (eq_attr "mode" "V512QI") (symbol_ref "riscv_vector::get_vlmul(E= _V512QImode)") > + (eq_attr "mode" "V1024QI") (symbol_ref "riscv_vector::get_vlmul(= E_V1024QImode)") > + (eq_attr "mode" "V2048QI") (symbol_ref "riscv_vector::get_vlmul(= E_V2048QImode)") > + (eq_attr "mode" "V4096QI") (symbol_ref "riscv_vector::get_vlmul(= E_V4096QImode)") > + (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_vlmul(E_V= 1HImode)") > + (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_vlmul(E_V= 2HImode)") > + (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_vlmul(E_V= 4HImode)") > + (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_vlmul(E_V= 8HImode)") > + (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_vlmul(E_= V16HImode)") > + (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_vlmul(E_= V32HImode)") > + (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_vlmul(E_= V64HImode)") > + (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_vlmul(E= _V128HImode)") > + (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_vlmul(E= _V256HImode)") > + (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_vlmul(E= _V512HImode)") > + (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_vlmul(= E_V1024HImode)") > + (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_vlmul(= E_V2048HImode)") > + (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_vlmul(E_V= 1SImode)") > + (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_vlmul(E_V= 2SImode)") > + (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_vlmul(E_V= 4SImode)") > + (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_vlmul(E_V= 8SImode)") > + (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_vlmul(E_= V16SImode)") > + (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_vlmul(E_= V32SImode)") > + (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_vlmul(E_= V64SImode)") > + (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_vlmul(E= _V128SImode)") > + (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_vlmul(E= _V256SImode)") > + (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_vlmul(E= _V512SImode)") > + (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_vlmul(= E_V1024SImode)") > + (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_vlmul(E_V= 1DImode)") > + (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_vlmul(E_V= 2DImode)") > + (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_vlmul(E_V= 4DImode)") > + (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_vlmul(E_V= 8DImode)") > + (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_vlmul(E_= V16DImode)") > + (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_vlmul(E_= V32DImode)") > + (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_vlmul(E_= V64DImode)") > + (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_vlmul(E= _V128DImode)") > + (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_vlmul(E= _V256DImode)") > + (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_vlmul(E= _V512DImode)") > + (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_vlmul(E_V= 1HFmode)") > + (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_vlmul(E_V= 2HFmode)") > + (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_vlmul(E_V= 4HFmode)") > + (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_vlmul(E_V= 8HFmode)") > + (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_vlmul(E_= V16HFmode)") > + (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_vlmul(E_= V32HFmode)") > + (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_vlmul(E_= V64HFmode)") > + (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_vlmul(E= _V128HFmode)") > + (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_vlmul(E= _V256HFmode)") > + (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_vlmul(E= _V512HFmode)") > + (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_vlmul(= E_V1024HFmode)") > + (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_vlmul(= E_V2048HFmode)") > + (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_vlmul(E_V= 1SFmode)") > + (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_vlmul(E_V= 2SFmode)") > + (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_vlmul(E_V= 4SFmode)") > + (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_vlmul(E_V= 8SFmode)") > + (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_vlmul(E_= V16SFmode)") > + (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_vlmul(E_= V32SFmode)") > + (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_vlmul(E_= V64SFmode)") > + (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_vlmul(E= _V128SFmode)") > + (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_vlmul(E= _V256SFmode)") > + (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_vlmul(E= _V512SFmode)") > + (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_vlmul(= E_V1024SFmode)") > + (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_vlmul(E_V= 1DFmode)") > + (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_vlmul(E_V= 2DFmode)") > + (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_vlmul(E_V= 4DFmode)") > + (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_vlmul(E_V= 8DFmode)") > + (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_vlmul(E_= V16DFmode)") > + (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_vlmul(E_= V32DFmode)") > + (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_vlmul(E_= V64DFmode)") > + (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_vlmul(E= _V128DFmode)") > + (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_vlmul(E= _V256DFmode)") > + (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_vlmul(E= _V512DFmode)")] > (const_int INVALID_ATTRIBUTE))) > > ;; It is valid for instruction that require sew/lmul ratio. > @@ -514,7 +603,88 @@ > (eq_attr "mode" "RVVM1x3DF") (const_int 64) > (eq_attr "mode" "RVVM4x2DF") (const_int 16) > (eq_attr "mode" "RVVM2x2DF") (const_int 32) > - (eq_attr "mode" "RVVM1x2DF") (const_int 64)] > + (eq_attr "mode" "RVVM1x2DF") (const_int 64) > + > + ;; VLS modes. > + (eq_attr "mode" "V1QI") (symbol_ref "riscv_vector::get_ratio(E_V= 1QImode)") > + (eq_attr "mode" "V2QI") (symbol_ref "riscv_vector::get_ratio(E_V= 2QImode)") > + (eq_attr "mode" "V4QI") (symbol_ref "riscv_vector::get_ratio(E_V= 4QImode)") > + (eq_attr "mode" "V8QI") (symbol_ref "riscv_vector::get_ratio(E_V= 8QImode)") > + (eq_attr "mode" "V16QI") (symbol_ref "riscv_vector::get_ratio(E_= V16QImode)") > + (eq_attr "mode" "V32QI") (symbol_ref "riscv_vector::get_ratio(E_= V32QImode)") > + (eq_attr "mode" "V64QI") (symbol_ref "riscv_vector::get_ratio(E_= V64QImode)") > + (eq_attr "mode" "V128QI") (symbol_ref "riscv_vector::get_ratio(E= _V128QImode)") > + (eq_attr "mode" "V256QI") (symbol_ref "riscv_vector::get_ratio(E= _V256QImode)") > + (eq_attr "mode" "V512QI") (symbol_ref "riscv_vector::get_ratio(E= _V512QImode)") > + (eq_attr "mode" "V1024QI") (symbol_ref "riscv_vector::get_ratio(= E_V1024QImode)") > + (eq_attr "mode" "V2048QI") (symbol_ref "riscv_vector::get_ratio(= E_V2048QImode)") > + (eq_attr "mode" "V4096QI") (symbol_ref "riscv_vector::get_ratio(= E_V4096QImode)") > + (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_ratio(E_V= 1HImode)") > + (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_ratio(E_V= 2HImode)") > + (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_ratio(E_V= 4HImode)") > + (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_ratio(E_V= 8HImode)") > + (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_ratio(E_= V16HImode)") > + (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_ratio(E_= V32HImode)") > + (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_ratio(E_= V64HImode)") > + (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_ratio(E= _V128HImode)") > + (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_ratio(E= _V256HImode)") > + (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_ratio(E= _V512HImode)") > + (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_ratio(= E_V1024HImode)") > + (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_ratio(= E_V2048HImode)") > + (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_ratio(E_V= 1SImode)") > + (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_ratio(E_V= 2SImode)") > + (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_ratio(E_V= 4SImode)") > + (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_ratio(E_V= 8SImode)") > + (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_ratio(E_= V16SImode)") > + (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_ratio(E_= V32SImode)") > + (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_ratio(E_= V64SImode)") > + (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_ratio(E= _V128SImode)") > + (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_ratio(E= _V256SImode)") > + (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_ratio(E= _V512SImode)") > + (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_ratio(= E_V1024SImode)") > + (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_ratio(E_V= 1DImode)") > + (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_ratio(E_V= 2DImode)") > + (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_ratio(E_V= 4DImode)") > + (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_ratio(E_V= 8DImode)") > + (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_ratio(E_= V16DImode)") > + (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_ratio(E_= V32DImode)") > + (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_ratio(E_= V64DImode)") > + (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_ratio(E= _V128DImode)") > + (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_ratio(E= _V256DImode)") > + (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_ratio(E= _V512DImode)") > + (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_ratio(E_V= 1HFmode)") > + (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_ratio(E_V= 2HFmode)") > + (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_ratio(E_V= 4HFmode)") > + (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_ratio(E_V= 8HFmode)") > + (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_ratio(E_= V16HFmode)") > + (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_ratio(E_= V32HFmode)") > + (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_ratio(E_= V64HFmode)") > + (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_ratio(E= _V128HFmode)") > + (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_ratio(E= _V256HFmode)") > + (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_ratio(E= _V512HFmode)") > + (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_ratio(= E_V1024HFmode)") > + (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_ratio(= E_V2048HFmode)") > + (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_ratio(E_V= 1SFmode)") > + (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_ratio(E_V= 2SFmode)") > + (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_ratio(E_V= 4SFmode)") > + (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_ratio(E_V= 8SFmode)") > + (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_ratio(E_= V16SFmode)") > + (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_ratio(E_= V32SFmode)") > + (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_ratio(E_= V64SFmode)") > + (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_ratio(E= _V128SFmode)") > + (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_ratio(E= _V256SFmode)") > + (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_ratio(E= _V512SFmode)") > + (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_ratio(= E_V1024SFmode)") > + (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_ratio(E_V= 1DFmode)") > + (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_ratio(E_V= 2DFmode)") > + (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_ratio(E_V= 4DFmode)") > + (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_ratio(E_V= 8DFmode)") > + (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_ratio(E_= V16DFmode)") > + (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_ratio(E_= V32DFmode)") > + (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_ratio(E_= V64DFmode)") > + (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_ratio(E= _V128DFmode)") > + (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_ratio(E= _V256DFmode)") > + (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_ratio(E= _V512DFmode)")] > (const_int INVALID_ATTRIBUTE))) > > ;; The index of operand[] to get the merge op. > @@ -630,7 +800,15 @@ > > ;; The avl type value. > (define_attr "avl_type" "" > - (cond [(eq_attr "type" "vlde,vldff,vste,vimov,vimov,vimov,vfmov,vext,v= imerge,\ > + (cond [(eq_attr "mode" "V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V= 256QI,V512QI,V1024QI,V2048QI,V4096QI, > + V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V2= 56HI,V512HI,V1024HI,V2048HI, > + V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V2= 56SI,V512SI,V1024SI, > + V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V2= 56DI,V512DI, > + V1HF,V2HF,V4HF,V8HF,V16HF,V32HF,V64HF,V128HF,V2= 56HF,V512HF,V1024HF,V2048HF, > + V1SF,V2SF,V4SF,V8SF,V16SF,V32SF,V64SF,V128SF,V2= 56SF,V512SF,V1024SF, > + V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V2= 56DF,V512DF") > + (symbol_ref "riscv_vector::NONVLMAX") > + (eq_attr "type" "vlde,vldff,vste,vimov,vimov,vimov,vfmov,vext,vim= erge,\ > vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcv= titof,\ > vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfn= cvtftof,\ > vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwr= edo,\ > @@ -1318,8 +1496,8 @@ > ;; (nil))))) > ;; Since both vmv.v.v and vmv.v.i doesn't have mask operand. > (define_insn_and_split "@pred_mov" > - [(set (match_operand:V 0 "nonimmediate_operand" "=3Dvr, vr, = vd, m, vr, vr, vr, vr") > - (if_then_else:V > + [(set (match_operand:V_VLS 0 "nonimmediate_operand" "=3Dvr, vr, = vd, m, vr, vr, vr, vr") > + (if_then_else:V_VLS > (unspec: > [(match_operand: 1 "vector_mask_operand" "vmWc1, Wc1, v= m, vmWc1, Wc1, Wc1, Wc1, Wc1") > (match_operand 4 "vector_length_operand" " rK, rK, r= K, rK, rK, rK, rK, rK") > @@ -1328,8 +1506,8 @@ > (match_operand 7 "const_int_operand" " i, i, = i, i, i, i, i, i") > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > - (match_operand:V 3 "vector_move_operand" " m, m, = m, vr, vr, vr, viWc0, viWc0") > - (match_operand:V 2 "vector_merge_operand" " 0, vu, v= u, vu, vu, 0, vu, 0")))] > + (match_operand:V_VLS 3 "vector_move_operand" " m, m, = m, vr, vr, vr, viWc0, viWc0") > + (match_operand:V_VLS 2 "vector_merge_operand" " 0, vu, v= u, vu, vu, 0, vu, 0")))] > "TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3]) > || CONST_VECTOR_P (operands[1]))" > "@ > @@ -1552,8 +1730,8 @@ > ;; To use LICM optimization, we postpone generation of vlse.v to split s= tage since > ;; a memory access instruction can not be optimized by LICM (Loop invari= ant). > (define_expand "@pred_broadcast" > - [(set (match_operand:V 0 "register_operand") > - (if_then_else:V > + [(set (match_operand:V_VLS 0 "register_operand") > + (if_then_else:V_VLS > (unspec: > [(match_operand: 1 "vector_broadcast_mask_operand") > (match_operand 4 "vector_length_operand") > @@ -1562,9 +1740,9 @@ > (match_operand 7 "const_int_operand") > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > - (vec_duplicate:V > + (vec_duplicate:V_VLS > (match_operand: 3 "direct_broadcast_operand")) > - (match_operand:V 2 "vector_merge_operand")))] > + (match_operand:V_VLS 2 "vector_merge_operand")))] > "TARGET_VECTOR" > { > /* Handle vmv.s.x instruction which has memory scalar. */ > @@ -1602,8 +1780,8 @@ > }) > > (define_insn_and_split "*pred_broadcast" > - [(set (match_operand:VI 0 "register_operand" "=3Dv= r, vr, vd, vd, vr, vr, vr, vr") > - (if_then_else:VI > + [(set (match_operand:V_VLSI 0 "register_operand" "=3Dv= r, vr, vd, vd, vr, vr, vr, vr") > + (if_then_else:V_VLSI > (unspec: > [(match_operand: 1 "vector_broadcast_mask_operand" "Wc1,W= c1, vm, vm,Wc1,Wc1,Wb1,Wb1") > (match_operand 4 "vector_length_operand" " rK, = rK, rK, rK, rK, rK, rK, rK") > @@ -1612,9 +1790,9 @@ > (match_operand 7 "const_int_operand" " i, = i, i, i, i, i, i, i") > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > - (vec_duplicate:VI > + (vec_duplicate:V_VLSI > (match_operand: 3 "direct_broadcast_operand" " r, = r,Wdm,Wdm,Wdm,Wdm, r, r")) > - (match_operand:VI 2 "vector_merge_operand" "vu, = 0, vu, 0, vu, 0, vu, 0")))] > + (match_operand:V_VLSI 2 "vector_merge_operand" "vu, = 0, vu, 0, vu, 0, vu, 0")))] > "TARGET_VECTOR" > "@ > vmv.v.x\t%0,%3 > @@ -1629,10 +1807,10 @@ > || CONST_POLY_INT_P (operands[3])) > && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (Pmode)" > [(set (match_dup 0) > - (if_then_else:VI (unspec: [(match_dup 1) (match_dup 4) > + (if_then_else:V_VLSI (unspec: [(match_dup 1) (match_dup 4) > (match_dup 5) (match_dup 6) (match_dup 7) > (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > - (vec_duplicate:VI (match_dup 3)) > + (vec_duplicate:V_VLSI (match_dup 3)) > (match_dup 2)))] > { > gcc_assert (can_create_pseudo_p ()); > @@ -1663,8 +1841,8 @@ > (set_attr "mode" "")]) > > (define_insn "*pred_broadcast" > - [(set (match_operand:VF_ZVFHMIN 0 "register_operand" "=3Dv= r, vr, vr, vr, vr, vr, vr, vr") > - (if_then_else:VF_ZVFHMIN > + [(set (match_operand:V_VLSF_ZVFHMIN 0 "register_operand" "=3Dv= r, vr, vr, vr, vr, vr, vr, vr") > + (if_then_else:V_VLSF_ZVFHMIN > (unspec: > [(match_operand: 1 "vector_broadcast_mask_operand" "Wc1,W= c1, vm, vm,Wc1,Wc1,Wb1,Wb1") > (match_operand 4 "vector_length_operand" " rK, = rK, rK, rK, rK, rK, rK, rK") > @@ -1673,9 +1851,9 @@ > (match_operand 7 "const_int_operand" " i, = i, i, i, i, i, i, i") > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > - (vec_duplicate:VF_ZVFHMIN > + (vec_duplicate:V_VLSF_ZVFHMIN > (match_operand: 3 "direct_broadcast_operand" " f, = f,Wdm,Wdm,Wdm,Wdm, f, f")) > - (match_operand:VF_ZVFHMIN 2 "vector_merge_operand" "vu, = 0, vu, 0, vu, 0, vu, 0")))] > + (match_operand:V_VLSF_ZVFHMIN 2 "vector_merge_operand" "vu, = 0, vu, 0, vu, 0, vu, 0")))] > "TARGET_VECTOR" > "@ > vfmv.v.f\t%0,%3 > @@ -1690,8 +1868,8 @@ > (set_attr "mode" "")]) > > (define_insn "*pred_broadcast_extended_scalar" > - [(set (match_operand:VI_D 0 "register_operand" "=3Dv= r, vr, vr, vr") > - (if_then_else:VI_D > + [(set (match_operand:V_VLSI_D 0 "register_operand" "=3Dv= r, vr, vr, vr") > + (if_then_else:V_VLSI_D > (unspec: > [(match_operand: 1 "vector_broadcast_mask_operand" "Wc1,W= c1,Wb1,Wb1") > (match_operand 4 "vector_length_operand" " rK, = rK, rK, rK") > @@ -1700,10 +1878,10 @@ > (match_operand 7 "const_int_operand" " i, = i, i, i") > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > - (vec_duplicate:VI_D > + (vec_duplicate:V_VLSI_D > (sign_extend: > (match_operand: 3 "register_operand" " r, = r, r, r"))) > - (match_operand:VI_D 2 "vector_merge_operand" "vu, = 0, vu, 0")))] > + (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, = 0, vu, 0")))] > "TARGET_VECTOR" > "@ > vmv.v.x\t%0,%3 > @@ -8655,3 +8833,4 @@ > > (include "autovec.md") > (include "autovec-opt.md") > +(include "autovec-vls.md") > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c b= /gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c > index d410e57adbd..59b07e265e8 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c > @@ -29,3 +29,4 @@ > TEST_ALL (VEC_PERM) > > /* { dg-final { scan-assembler-times {viota.m} 2 } } */ > +/* { dg-final { scan-assembler-not {vmv\.v\.i} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/t= estsuite/gcc.target/riscv/rvv/autovec/vls/def.h > new file mode 100644 > index 00000000000..d03108ad771 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > @@ -0,0 +1,88 @@ > +#include > + > +typedef int8_t v1qi __attribute__ ((vector_size (1))); > +typedef int8_t v2qi __attribute__ ((vector_size (2))); > +typedef int8_t v4qi __attribute__ ((vector_size (4))); > +typedef int8_t v8qi __attribute__ ((vector_size (8))); > +typedef int8_t v16qi __attribute__ ((vector_size (16))); > +typedef int8_t v32qi __attribute__ ((vector_size (32))); > +typedef int8_t v64qi __attribute__ ((vector_size (64))); > +typedef int8_t v128qi __attribute__ ((vector_size (128))); > +typedef int8_t v256qi __attribute__ ((vector_size (256))); > +typedef int8_t v512qi __attribute__ ((vector_size (512))); > +typedef int8_t v1024qi __attribute__ ((vector_size (1024))); > +typedef int8_t v2048qi __attribute__ ((vector_size (2048))); > +typedef int8_t v4096qi __attribute__ ((vector_size (4096))); > +typedef int16_t v1hi __attribute__ ((vector_size (2))); > +typedef int16_t v2hi __attribute__ ((vector_size (4))); > +typedef int16_t v4hi __attribute__ ((vector_size (8))); > +typedef int16_t v8hi __attribute__ ((vector_size (16))); > +typedef int16_t v16hi __attribute__ ((vector_size (32))); > +typedef int16_t v32hi __attribute__ ((vector_size (64))); > +typedef int16_t v64hi __attribute__ ((vector_size (128))); > +typedef int16_t v128hi __attribute__ ((vector_size (256))); > +typedef int16_t v256hi __attribute__ ((vector_size (512))); > +typedef int16_t v512hi __attribute__ ((vector_size (1024))); > +typedef int16_t v1024hi __attribute__ ((vector_size (2048))); > +typedef int16_t v2048hi __attribute__ ((vector_size (4096))); > +typedef int32_t v1si __attribute__ ((vector_size (4))); > +typedef int32_t v2si __attribute__ ((vector_size (8))); > +typedef int32_t v4si __attribute__ ((vector_size (16))); > +typedef int32_t v8si __attribute__ ((vector_size (32))); > +typedef int32_t v16si __attribute__ ((vector_size (64))); > +typedef int32_t v32si __attribute__ ((vector_size (128))); > +typedef int32_t v64si __attribute__ ((vector_size (256))); > +typedef int32_t v128si __attribute__ ((vector_size (512))); > +typedef int32_t v256si __attribute__ ((vector_size (1024))); > +typedef int32_t v512si __attribute__ ((vector_size (2048))); > +typedef int32_t v1024si __attribute__ ((vector_size (4096))); > +typedef int64_t v1di __attribute__ ((vector_size (8))); > +typedef int64_t v2di __attribute__ ((vector_size (16))); > +typedef int64_t v4di __attribute__ ((vector_size (32))); > +typedef int64_t v8di __attribute__ ((vector_size (64))); > +typedef int64_t v16di __attribute__ ((vector_size (128))); > +typedef int64_t v32di __attribute__ ((vector_size (256))); > +typedef int64_t v64di __attribute__ ((vector_size (512))); > +typedef int64_t v128di __attribute__ ((vector_size (1024))); > +typedef int64_t v256di __attribute__ ((vector_size (2048))); > +typedef int64_t v512di __attribute__ ((vector_size (4096))); > +typedef _Float16 v1hf __attribute__ ((vector_size (2))); > +typedef _Float16 v2hf __attribute__ ((vector_size (4))); > +typedef _Float16 v4hf __attribute__ ((vector_size (8))); > +typedef _Float16 v8hf __attribute__ ((vector_size (16))); > +typedef _Float16 v16hf __attribute__ ((vector_size (32))); > +typedef _Float16 v32hf __attribute__ ((vector_size (64))); > +typedef _Float16 v64hf __attribute__ ((vector_size (128))); > +typedef _Float16 v128hf __attribute__ ((vector_size (256))); > +typedef _Float16 v256hf __attribute__ ((vector_size (512))); > +typedef _Float16 v512hf __attribute__ ((vector_size (1024))); > +typedef _Float16 v1024hf __attribute__ ((vector_size (2048))); > +typedef _Float16 v2048hf __attribute__ ((vector_size (4096))); > +typedef float v1sf __attribute__ ((vector_size (4))); > +typedef float v2sf __attribute__ ((vector_size (8))); > +typedef float v4sf __attribute__ ((vector_size (16))); > +typedef float v8sf __attribute__ ((vector_size (32))); > +typedef float v16sf __attribute__ ((vector_size (64))); > +typedef float v32sf __attribute__ ((vector_size (128))); > +typedef float v64sf __attribute__ ((vector_size (256))); > +typedef float v128sf __attribute__ ((vector_size (512))); > +typedef float v256sf __attribute__ ((vector_size (1024))); > +typedef float v512sf __attribute__ ((vector_size (2048))); > +typedef float v1024sf __attribute__ ((vector_size (4096))); > +typedef double v1df __attribute__ ((vector_size (8))); > +typedef double v2df __attribute__ ((vector_size (16))); > +typedef double v4df __attribute__ ((vector_size (32))); > +typedef double v8df __attribute__ ((vector_size (64))); > +typedef double v16df __attribute__ ((vector_size (128))); > +typedef double v32df __attribute__ ((vector_size (256))); > +typedef double v64df __attribute__ ((vector_size (512))); > +typedef double v128df __attribute__ ((vector_size (1024))); > +typedef double v256df __attribute__ ((vector_size (2048))); > +typedef double v512df __attribute__ ((vector_size (4096))); > + > +#define exhaust_vector_regs() = \ > + asm volatile("#" :: = \ > + : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", = "v9", \ > + "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17"= , \ > + "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25"= , \ > + "v26", "v27", "v28", "v29", "v30", "v31"); > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c b/gcc= /testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c > new file mode 100644 > index 00000000000..aedf98819bb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c > @@ -0,0 +1,179 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** lbu\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sb\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov0 (int8_t *in, int8_t *out) > +{ > + v1qi v =3D *(v1qi*)in; > + *(v1qi*)out =3D v; > +} > + > +/* > +** mov1: > +** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov1 (int8_t *in, int8_t *out) > +{ > + v2qi v =3D *(v2qi*)in; > + *(v2qi*)out =3D v; > +} > + > +/* > +** mov2: > +** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov2 (int8_t *in, int8_t *out) > +{ > + v4qi v =3D *(v4qi*)in; > + *(v4qi*)out =3D v; > +} > + > +/* > +** mov3: > +** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov3 (int8_t *in, int8_t *out) > +{ > + v8qi v =3D *(v8qi*)in; > + *(v8qi*)out =3D v; > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov4 (int8_t *in, int8_t *out) > +{ > + v16qi v =3D *(v16qi*)in; > + *(v16qi*)out =3D v; > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov5 (int8_t *in, int8_t *out) > +{ > + v32qi v =3D *(v32qi*)in; > + *(v32qi*)out =3D v; > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov6 (int8_t *in, int8_t *out) > +{ > + v64qi v =3D *(v64qi*)in; > + *(v64qi*)out =3D v; > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au] > +** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov7 (int8_t *in, int8_t *out) > +{ > + v128qi v =3D *(v128qi*)in; > + *(v128qi*)out =3D v; > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au] > +** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov8 (int8_t *in, int8_t *out) > +{ > + v256qi v =3D *(v256qi*)in; > + *(v256qi*)out =3D v; > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au] > +** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov9 (int8_t *in, int8_t *out) > +{ > + v512qi v =3D *(v512qi*)in; > + *(v512qi*)out =3D v; > +} > + > +/* > +** mov10: > +** li\s+[a-x0-9]+,1024 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au] > +** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov10 (int8_t *in, int8_t *out) > +{ > + v1024qi v =3D *(v1024qi*)in; > + *(v1024qi*)out =3D v; > +} > + > +/* > +** mov11: > +** li\s+[a-x0-9]+,4096 > +** addi\s+[a-x0-9]+,[a-x0-9]+,-2048 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au] > +** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov11 (int8_t *in, int8_t *out) > +{ > + v2048qi v =3D *(v2048qi*)in; > + *(v2048qi*)out =3D v; > +} > + > +/* > +** mov12: > +** li\s+[a-x0-9]+,4096 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au] > +** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov12 (int8_t *in, int8_t *out) > +{ > + v4096qi v =3D *(v4096qi*)in; > + *(v4096qi*)out =3D v; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c b/gc= c/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c > new file mode 100644 > index 00000000000..5e9615412b7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c > @@ -0,0 +1,139 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov0 (double *in, double *out) > +{ > + v1df v =3D *(v1df*)in; > + *(v1df*)out =3D v; > +} > + > +/* > +** mov1: > +** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov1 (double *in, double *out) > +{ > + v2df v =3D *(v2df*)in; > + *(v2df*)out =3D v; > +} > + > +/* > +** mov2: > +** vsetivli\s+zero,\s*4,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov2 (double *in, double *out) > +{ > + v4df v =3D *(v4df*)in; > + *(v4df*)out =3D v; > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov3 (double *in, double *out) > +{ > + v8df v =3D *(v8df*)in; > + *(v8df*)out =3D v; > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov4 (double *in, double *out) > +{ > + v16df v =3D *(v16df*)in; > + *(v16df*)out =3D v; > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov5 (double *in, double *out) > +{ > + v32df v =3D *(v32df*)in; > + *(v32df*)out =3D v; > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov6 (double *in, double *out) > +{ > + v64df v =3D *(v64df*)in; > + *(v64df*)out =3D v; > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov7 (double *in, double *out) > +{ > + v128df v =3D *(v128df*)in; > + *(v128df*)out =3D v; > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov8 (double *in, double *out) > +{ > + v256df v =3D *(v256df*)in; > + *(v256df*)out =3D v; > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov9 (double *in, double *out) > +{ > + v512df v =3D *(v512df*)in; > + *(v512df*)out =3D v; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c b/gc= c/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c > new file mode 100644 > index 00000000000..e2ca21e2d5b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c > @@ -0,0 +1,248 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** vsetivli\s+zero,\s*1,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vle8\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov0 (int8_t *in, int8_t *out) > +{ > + register v1qi v1 asm("v1") =3D *(v1qi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v1qi v2 asm("v2") =3D v1; > + *(v1qi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov1: > +** vsetivli\s+zero,\s*2,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vle8\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov1 (int8_t *in, int8_t *out) > +{ > + register v2qi v1 asm("v1") =3D *(v2qi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v2qi v2 asm("v2") =3D v1; > + *(v2qi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov2: > +** vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vle8\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov2 (int8_t *in, int8_t *out) > +{ > + register v4qi v1 asm("v1") =3D *(v4qi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v4qi v2 asm("v2") =3D v1; > + *(v4qi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vle8\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov3 (int8_t *in, int8_t *out) > +{ > + register v8qi v1 asm("v1") =3D *(v8qi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v8qi v2 asm("v2") =3D v1; > + *(v8qi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vle8\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov4 (int8_t *in, int8_t *out) > +{ > + register v16qi v1 asm("v1") =3D *(v16qi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v16qi v2 asm("v2") =3D v1; > + *(v16qi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vle8\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov5 (int8_t *in, int8_t *out) > +{ > + register v32qi v1 asm("v1") =3D *(v32qi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v32qi v2 asm("v2") =3D v1; > + *(v32qi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vle8\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov6 (int8_t *in, int8_t *out) > +{ > + register v64qi v1 asm("v1") =3D *(v64qi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v64qi v2 asm("v2") =3D v1; > + *(v64qi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au] > +** vle8\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov7 (int8_t *in, int8_t *out) > +{ > + register v128qi v1 asm("v1") =3D *(v128qi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v128qi v2 asm("v2") =3D v1; > + *(v128qi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au] > +** vle8\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov8 (int8_t *in, int8_t *out) > +{ > + register v256qi v1 asm("v1") =3D *(v256qi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v256qi v2 asm("v2") =3D v1; > + *(v256qi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au] > +** vle8\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov9 (int8_t *in, int8_t *out) > +{ > + register v512qi v1 asm("v1") =3D *(v512qi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v512qi v2 asm("v2") =3D v1; > + *(v512qi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov10: > +** li\s+[a-x0-9]+,1024 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au] > +** vle8\.v\tv2,0\s*\([a-x0-9]+\) > +** ... > +** vmv2r\.v\tv4,v2 > +** ... > +** ret > +*/ > +void mov10 (uint8_t *in, uint8_t *out) > +{ > + register v1024qi v2 asm("v2") =3D *(v1024qi*)in; > + asm volatile ("# %0"::"vr"(v2)); > + register v1024qi v4 asm("v4") =3D v2; > + *(v1024qi*)out =3D v4; > + asm volatile ("# %0"::"vr"(v4)); > +} > + > +/* > +** mov11: > +** li\s+[a-x0-9]+,4096 > +** addi\s+[a-x0-9]+,[a-x0-9]+,-2048 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au] > +** vle8\.v\tv4,0\s*\([a-x0-9]+\) > +** ... > +** vmv4r\.v\tv8,v4 > +** ... > +** ret > +*/ > +void mov11 (uint8_t *in, uint8_t *out) > +{ > + register v2048qi v4 asm("v4") =3D *(v2048qi*)in; > + asm volatile ("# %0"::"vr"(v4)); > + register v2048qi v8 asm("v8") =3D v4; > + *(v2048qi*)out =3D v8; > + asm volatile ("# %0"::"vr"(v8)); > +} > + > +/* > +** mov12: > +** li\s+[a-x0-9]+,4096 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au] > +** vle8\.v\tv8,0\s*\([a-x0-9]+\) > +** ... > +** vmv8r\.v\tv16,v8 > +** ... > +** ret > +*/ > +void mov12 (uint8_t *in, uint8_t *out) > +{ > + register v4096qi v8 asm("v8") =3D *(v4096qi*)in; > + asm volatile ("# %0"::"vr"(v8)); > + register v4096qi v16 asm("v16") =3D v8; > + *(v4096qi*)out =3D v16; > + asm volatile ("# %0"::"vr"(v16)); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c b/gc= c/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c > new file mode 100644 > index 00000000000..fc38e791ecf > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c > @@ -0,0 +1,229 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov0 (int16_t *in, int16_t *out) > +{ > + register v1hi v1 asm("v1") =3D *(v1hi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v1hi v2 asm("v2") =3D v1; > + *(v1hi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov1: > +** vsetivli\s+zero,\s*2,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov1 (int16_t *in, int16_t *out) > +{ > + register v2hi v1 asm("v1") =3D *(v2hi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v2hi v2 asm("v2") =3D v1; > + *(v2hi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov2: > +** vsetivli\s+zero,\s*4,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov2 (int16_t *in, int16_t *out) > +{ > + register v4hi v1 asm("v1") =3D *(v4hi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v4hi v2 asm("v2") =3D v1; > + *(v4hi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov3 (int16_t *in, int16_t *out) > +{ > + register v8hi v1 asm("v1") =3D *(v8hi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v8hi v2 asm("v2") =3D v1; > + *(v8hi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov4 (int16_t *in, int16_t *out) > +{ > + register v16hi v1 asm("v1") =3D *(v16hi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v16hi v2 asm("v2") =3D v1; > + *(v16hi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov5 (int16_t *in, int16_t *out) > +{ > + register v32hi v1 asm("v1") =3D *(v32hi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v32hi v2 asm("v2") =3D v1; > + *(v32hi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov6 (int16_t *in, int16_t *out) > +{ > + register v64hi v1 asm("v1") =3D *(v64hi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v64hi v2 asm("v2") =3D v1; > + *(v64hi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov7 (int16_t *in, int16_t *out) > +{ > + register v128hi v1 asm("v1") =3D *(v128hi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v128hi v2 asm("v2") =3D v1; > + *(v128hi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov8 (int16_t *in, int16_t *out) > +{ > + register v256hi v1 asm("v1") =3D *(v256hi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v256hi v2 asm("v2") =3D v1; > + *(v256hi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au] > +** vle16\.v\tv2,0\s*\([a-x0-9]+\) > +** ... > +** vmv2r\.v\tv4,v2 > +** ... > +** ret > +*/ > +void mov9 (int16_t *in, int16_t *out) > +{ > + register v512hi v1 asm("v2") =3D *(v512hi*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v512hi v2 asm("v4") =3D v1; > + *(v512hi*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov10: > +** li\s+[a-x0-9]+,1024 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au] > +** vle16\.v\tv4,0\s*\([a-x0-9]+\) > +** ... > +** vmv4r\.v\tv8,v4 > +** ... > +** ret > +*/ > +void mov10 (uint16_t *in, uint16_t *out) > +{ > + register v1024hi v2 asm("v4") =3D *(v1024hi*)in; > + asm volatile ("# %0"::"vr"(v2)); > + register v1024hi v4 asm("v8") =3D v2; > + *(v1024hi*)out =3D v4; > + asm volatile ("# %0"::"vr"(v4)); > +} > + > +/* > +** mov11: > +** li\s+[a-x0-9]+,4096 > +** addi\s+[a-x0-9]+,[a-x0-9]+,-2048 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au] > +** vle16\.v\tv8,0\s*\([a-x0-9]+\) > +** ... > +** vmv8r\.v\tv16,v8 > +** ... > +** ret > +*/ > +void mov11 (uint16_t *in, uint16_t *out) > +{ > + register v2048hi v4 asm("v8") =3D *(v2048hi*)in; > + asm volatile ("# %0"::"vr"(v4)); > + register v2048hi v8 asm("v16") =3D v4; > + *(v2048hi*)out =3D v8; > + asm volatile ("# %0"::"vr"(v8)); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c b/gc= c/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c > new file mode 100644 > index 00000000000..d51922efdc9 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c > @@ -0,0 +1,209 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** vsetivli\s+zero,\s*1,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov0 (int32_t *in, int32_t *out) > +{ > + register v1si v1 asm("v1") =3D *(v1si*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v1si v2 asm("v2") =3D v1; > + *(v1si*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov1: > +** vsetivli\s+zero,\s*2,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov1 (int32_t *in, int32_t *out) > +{ > + register v2si v1 asm("v1") =3D *(v2si*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v2si v2 asm("v2") =3D v1; > + *(v2si*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov2: > +** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov2 (int32_t *in, int32_t *out) > +{ > + register v4si v1 asm("v1") =3D *(v4si*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v4si v2 asm("v2") =3D v1; > + *(v4si*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov3 (int32_t *in, int32_t *out) > +{ > + register v8si v1 asm("v1") =3D *(v8si*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v8si v2 asm("v2") =3D v1; > + *(v8si*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov4 (int32_t *in, int32_t *out) > +{ > + register v16si v1 asm("v1") =3D *(v16si*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v16si v2 asm("v2") =3D v1; > + *(v16si*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov5 (int32_t *in, int32_t *out) > +{ > + register v32si v1 asm("v1") =3D *(v32si*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v32si v2 asm("v2") =3D v1; > + *(v32si*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov6 (int32_t *in, int32_t *out) > +{ > + register v64si v1 asm("v1") =3D *(v64si*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v64si v2 asm("v2") =3D v1; > + *(v64si*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov7 (int32_t *in, int32_t *out) > +{ > + register v128si v1 asm("v1") =3D *(v128si*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v128si v2 asm("v2") =3D v1; > + *(v128si*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au] > +** vle32\.v\tv2,0\s*\([a-x0-9]+\) > +** ... > +** vmv2r\.v\tv4,v2 > +** ... > +** ret > +*/ > +void mov8 (int32_t *in, int32_t *out) > +{ > + register v256si v1 asm("v2") =3D *(v256si*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v256si v2 asm("v4") =3D v1; > + *(v256si*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au] > +** vle32\.v\tv4,0\s*\([a-x0-9]+\) > +** ... > +** vmv4r\.v\tv8,v4 > +** ... > +** ret > +*/ > +void mov9 (int32_t *in, int32_t *out) > +{ > + register v512si v1 asm("v4") =3D *(v512si*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v512si v2 asm("v8") =3D v1; > + *(v512si*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov10: > +** li\s+[a-x0-9]+,1024 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au] > +** vle32\.v\tv8,0\s*\([a-x0-9]+\) > +** ... > +** vmv8r\.v\tv16,v8 > +** ... > +** ret > +*/ > +void mov10 (int32_t *in, int32_t *out) > +{ > + register v1024si v2 asm("v8") =3D *(v1024si*)in; > + asm volatile ("# %0"::"vr"(v2)); > + register v1024si v4 asm("v16") =3D v2; > + *(v1024si*)out =3D v4; > + asm volatile ("# %0"::"vr"(v4)); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c b/gc= c/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c > new file mode 100644 > index 00000000000..8ed8f6be19e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c > @@ -0,0 +1,190 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov0 (int64_t *in, int64_t *out) > +{ > + register v1di v1 asm("v1") =3D *(v1di*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v1di v2 asm("v2") =3D v1; > + *(v1di*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov1: > +** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov1 (int64_t *in, int64_t *out) > +{ > + register v2di v1 asm("v1") =3D *(v2di*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v2di v2 asm("v2") =3D v1; > + *(v2di*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov2: > +** vsetivli\s+zero,\s*4,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov2 (int64_t *in, int64_t *out) > +{ > + register v4di v1 asm("v1") =3D *(v4di*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v4di v2 asm("v2") =3D v1; > + *(v4di*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov3 (int64_t *in, int64_t *out) > +{ > + register v8di v1 asm("v1") =3D *(v8di*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v8di v2 asm("v2") =3D v1; > + *(v8di*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov4 (int64_t *in, int64_t *out) > +{ > + register v16di v1 asm("v1") =3D *(v16di*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v16di v2 asm("v2") =3D v1; > + *(v16di*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov5 (int64_t *in, int64_t *out) > +{ > + register v32di v1 asm("v1") =3D *(v32di*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v32di v2 asm("v2") =3D v1; > + *(v32di*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov6 (int64_t *in, int64_t *out) > +{ > + register v64di v1 asm("v1") =3D *(v64di*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v64di v2 asm("v2") =3D v1; > + *(v64di*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au] > +** vle64\.v\tv2,0\s*\([a-x0-9]+\) > +** ... > +** vmv2r\.v\tv4,v2 > +** ... > +** ret > +*/ > +void mov7 (int64_t *in, int64_t *out) > +{ > + register v128di v1 asm("v2") =3D *(v128di*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v128di v2 asm("v4") =3D v1; > + *(v128di*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au] > +** vle64\.v\tv4,0\s*\([a-x0-9]+\) > +** ... > +** vmv4r\.v\tv8,v4 > +** ... > +** ret > +*/ > +void mov8 (int64_t *in, int64_t *out) > +{ > + register v256di v1 asm("v4") =3D *(v256di*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v256di v2 asm("v8") =3D v1; > + *(v256di*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au] > +** vle64\.v\tv8,0\s*\([a-x0-9]+\) > +** ... > +** vmv8r\.v\tv16,v8 > +** ... > +** ret > +*/ > +void mov9 (int64_t *in, int64_t *out) > +{ > + register v512di v1 asm("v8") =3D *(v512di*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v512di v2 asm("v16") =3D v1; > + *(v512di*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c b/gc= c/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c > new file mode 100644 > index 00000000000..f4ce5b3c0a6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c > @@ -0,0 +1,229 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov0 (_Float16 *in, _Float16 *out) > +{ > + register v1hf v1 asm("v1") =3D *(v1hf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v1hf v2 asm("v2") =3D v1; > + *(v1hf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov1: > +** vsetivli\s+zero,\s*2,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov1 (_Float16 *in, _Float16 *out) > +{ > + register v2hf v1 asm("v1") =3D *(v2hf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v2hf v2 asm("v2") =3D v1; > + *(v2hf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov2: > +** vsetivli\s+zero,\s*4,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov2 (_Float16 *in, _Float16 *out) > +{ > + register v4hf v1 asm("v1") =3D *(v4hf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v4hf v2 asm("v2") =3D v1; > + *(v4hf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov3 (_Float16 *in, _Float16 *out) > +{ > + register v8hf v1 asm("v1") =3D *(v8hf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v8hf v2 asm("v2") =3D v1; > + *(v8hf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov4 (_Float16 *in, _Float16 *out) > +{ > + register v16hf v1 asm("v1") =3D *(v16hf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v16hf v2 asm("v2") =3D v1; > + *(v16hf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov5 (_Float16 *in, _Float16 *out) > +{ > + register v32hf v1 asm("v1") =3D *(v32hf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v32hf v2 asm("v2") =3D v1; > + *(v32hf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov6 (_Float16 *in, _Float16 *out) > +{ > + register v64hf v1 asm("v1") =3D *(v64hf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v64hf v2 asm("v2") =3D v1; > + *(v64hf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov7 (_Float16 *in, _Float16 *out) > +{ > + register v128hf v1 asm("v1") =3D *(v128hf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v128hf v2 asm("v2") =3D v1; > + *(v128hf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au] > +** vle16\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov8 (_Float16 *in, _Float16 *out) > +{ > + register v256hf v1 asm("v1") =3D *(v256hf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v256hf v2 asm("v2") =3D v1; > + *(v256hf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au] > +** vle16\.v\tv2,0\s*\([a-x0-9]+\) > +** ... > +** vmv2r\.v\tv4,v2 > +** ... > +** ret > +*/ > +void mov9 (_Float16 *in, _Float16 *out) > +{ > + register v512hf v1 asm("v2") =3D *(v512hf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v512hf v2 asm("v4") =3D v1; > + *(v512hf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov10: > +** li\s+[a-x0-9]+,1024 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au] > +** vle16\.v\tv4,0\s*\([a-x0-9]+\) > +** ... > +** vmv4r\.v\tv8,v4 > +** ... > +** ret > +*/ > +void mov10 (_Float16 *in, _Float16 *out) > +{ > + register v1024hf v2 asm("v4") =3D *(v1024hf*)in; > + asm volatile ("# %0"::"vr"(v2)); > + register v1024hf v4 asm("v8") =3D v2; > + *(v1024hf*)out =3D v4; > + asm volatile ("# %0"::"vr"(v4)); > +} > + > +/* > +** mov11: > +** li\s+[a-x0-9]+,4096 > +** addi\s+[a-x0-9]+,[a-x0-9]+,-2048 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au] > +** vle16\.v\tv8,0\s*\([a-x0-9]+\) > +** ... > +** vmv8r\.v\tv16,v8 > +** ... > +** ret > +*/ > +void mov11 (_Float16 *in, _Float16 *out) > +{ > + register v2048hf v4 asm("v8") =3D *(v2048hf*)in; > + asm volatile ("# %0"::"vr"(v4)); > + register v2048hf v8 asm("v16") =3D v4; > + *(v2048hf*)out =3D v8; > + asm volatile ("# %0"::"vr"(v8)); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c b/gc= c/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c > new file mode 100644 > index 00000000000..ff36d785bc6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c > @@ -0,0 +1,209 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** vsetivli\s+zero,\s*1,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov0 (float *in, float *out) > +{ > + register v1sf v1 asm("v1") =3D *(v1sf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v1sf v2 asm("v2") =3D v1; > + *(v1sf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov1: > +** vsetivli\s+zero,\s*2,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov1 (float *in, float *out) > +{ > + register v2sf v1 asm("v1") =3D *(v2sf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v2sf v2 asm("v2") =3D v1; > + *(v2sf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov2: > +** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov2 (float *in, float *out) > +{ > + register v4sf v1 asm("v1") =3D *(v4sf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v4sf v2 asm("v2") =3D v1; > + *(v4sf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov3 (float *in, float *out) > +{ > + register v8sf v1 asm("v1") =3D *(v8sf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v8sf v2 asm("v2") =3D v1; > + *(v8sf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov4 (float *in, float *out) > +{ > + register v16sf v1 asm("v1") =3D *(v16sf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v16sf v2 asm("v2") =3D v1; > + *(v16sf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov5 (float *in, float *out) > +{ > + register v32sf v1 asm("v1") =3D *(v32sf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v32sf v2 asm("v2") =3D v1; > + *(v32sf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov6 (float *in, float *out) > +{ > + register v64sf v1 asm("v1") =3D *(v64sf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v64sf v2 asm("v2") =3D v1; > + *(v64sf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au] > +** vle32\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov7 (float *in, float *out) > +{ > + register v128sf v1 asm("v1") =3D *(v128sf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v128sf v2 asm("v2") =3D v1; > + *(v128sf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au] > +** vle32\.v\tv2,0\s*\([a-x0-9]+\) > +** ... > +** vmv2r\.v\tv4,v2 > +** ... > +** ret > +*/ > +void mov8 (float *in, float *out) > +{ > + register v256sf v1 asm("v2") =3D *(v256sf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v256sf v2 asm("v4") =3D v1; > + *(v256sf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au] > +** vle32\.v\tv4,0\s*\([a-x0-9]+\) > +** ... > +** vmv4r\.v\tv8,v4 > +** ... > +** ret > +*/ > +void mov9 (float *in, float *out) > +{ > + register v512sf v1 asm("v4") =3D *(v512sf*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v512sf v2 asm("v8") =3D v1; > + *(v512sf*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov10: > +** li\s+[a-x0-9]+,1024 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au] > +** vle32\.v\tv8,0\s*\([a-x0-9]+\) > +** ... > +** vmv8r\.v\tv16,v8 > +** ... > +** ret > +*/ > +void mov10 (float *in, float *out) > +{ > + register v1024sf v2 asm("v8") =3D *(v1024sf*)in; > + asm volatile ("# %0"::"vr"(v2)); > + register v1024sf v4 asm("v16") =3D v2; > + *(v1024sf*)out =3D v4; > + asm volatile ("# %0"::"vr"(v4)); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c b/gc= c/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c > new file mode 100644 > index 00000000000..754771aa69d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c > @@ -0,0 +1,190 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov0 (double *in, double *out) > +{ > + register v1df v1 asm("v1") =3D *(v1df*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v1df v2 asm("v2") =3D v1; > + *(v1df*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov1: > +** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov1 (double *in, double *out) > +{ > + register v2df v1 asm("v1") =3D *(v2df*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v2df v2 asm("v2") =3D v1; > + *(v2df*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov2: > +** vsetivli\s+zero,\s*4,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov2 (double *in, double *out) > +{ > + register v4df v1 asm("v1") =3D *(v4df*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v4df v2 asm("v2") =3D v1; > + *(v4df*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov3 (double *in, double *out) > +{ > + register v8df v1 asm("v1") =3D *(v8df*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v8df v2 asm("v2") =3D v1; > + *(v8df*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov4 (double *in, double *out) > +{ > + register v16df v1 asm("v1") =3D *(v16df*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v16df v2 asm("v2") =3D v1; > + *(v16df*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov5 (double *in, double *out) > +{ > + register v32df v1 asm("v1") =3D *(v32df*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v32df v2 asm("v2") =3D v1; > + *(v32df*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\tv1,0\s*\([a-x0-9]+\) > +** ... > +** vmv1r\.v\tv2,v1 > +** ... > +** ret > +*/ > +void mov6 (double *in, double *out) > +{ > + register v64df v1 asm("v1") =3D *(v64df*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v64df v2 asm("v2") =3D v1; > + *(v64df*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au] > +** vle64\.v\tv2,0\s*\([a-x0-9]+\) > +** ... > +** vmv2r\.v\tv4,v2 > +** ... > +** ret > +*/ > +void mov7 (double *in, double *out) > +{ > + register v128df v1 asm("v2") =3D *(v128df*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v128df v2 asm("v4") =3D v1; > + *(v128df*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au] > +** vle64\.v\tv4,0\s*\([a-x0-9]+\) > +** ... > +** vmv4r\.v\tv8,v4 > +** ... > +** ret > +*/ > +void mov8 (double *in, double *out) > +{ > + register v256df v1 asm("v4") =3D *(v256df*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v256df v2 asm("v8") =3D v1; > + *(v256df*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au] > +** vle64\.v\tv8,0\s*\([a-x0-9]+\) > +** ... > +** vmv8r\.v\tv16,v8 > +** ... > +** ret > +*/ > +void mov9 (double *in, double *out) > +{ > + register v512df v1 asm("v8") =3D *(v512df*)in; > + asm volatile ("# %0"::"vr"(v1)); > + register v512df v2 asm("v16") =3D v1; > + *(v512df*)out =3D v2; > + asm volatile ("# %0"::"vr"(v2)); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c b/gcc= /testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c > new file mode 100644 > index 00000000000..10ae1972db7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv_zvfh_zvl4096b -mabi=3Dilp32d -O3 -fno-= schedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov: > +** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) > +** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov (int8_t *in, int8_t *out) > +{ > + v8qi v =3D *(v8qi*)in; > + *(v8qi*)out =3D v; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c b/gcc= /testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c > new file mode 100644 > index 00000000000..f2880ae5e77 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c > @@ -0,0 +1,166 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov0 (int16_t *in, int16_t *out) > +{ > + v1hi v =3D *(v1hi*)in; > + *(v1hi*)out =3D v; > +} > + > +/* > +** mov1: > +** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov1 (int16_t *in, int16_t *out) > +{ > + v2hi v =3D *(v2hi*)in; > + *(v2hi*)out =3D v; > +} > + > +/* > +** mov2: > +** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov2 (int16_t *in, int16_t *out) > +{ > + v4hi v =3D *(v4hi*)in; > + *(v4hi*)out =3D v; > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov3 (int16_t *in, int16_t *out) > +{ > + v8hi v =3D *(v8hi*)in; > + *(v8hi*)out =3D v; > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov4 (int16_t *in, int16_t *out) > +{ > + v16hi v =3D *(v16hi*)in; > + *(v16hi*)out =3D v; > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov5 (int16_t *in, int16_t *out) > +{ > + v32hi v =3D *(v32hi*)in; > + *(v32hi*)out =3D v; > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov6 (int16_t *in, int16_t *out) > +{ > + v64hi v =3D *(v64hi*)in; > + *(v64hi*)out =3D v; > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov7 (int16_t *in, int16_t *out) > +{ > + v128hi v =3D *(v128hi*)in; > + *(v128hi*)out =3D v; > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov8 (int16_t *in, int16_t *out) > +{ > + v256hi v =3D *(v256hi*)in; > + *(v256hi*)out =3D v; > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov9 (int16_t *in, int16_t *out) > +{ > + v512hi v =3D *(v512hi*)in; > + *(v512hi*)out =3D v; > +} > + > +/* > +** mov10: > +** li\s+[a-x0-9]+,1024 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov10 (int16_t *in, int16_t *out) > +{ > + v1024hi v =3D *(v1024hi*)in; > + *(v1024hi*)out =3D v; > +} > + > +/* > +** mov11: > +** li\s+[a-x0-9]+,4096 > +** addi\s+[a-x0-9]+,[a-x0-9]+,-2048 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov11 (int16_t *in, int16_t *out) > +{ > + v2048hi v =3D *(v2048hi*)in; > + *(v2048hi*)out =3D v; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c b/gcc= /testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c > new file mode 100644 > index 00000000000..f81f1697d65 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv_zvfh_zvl4096b -mabi=3Dilp32d -O3 -fno-= schedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov: > +** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) > +** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov (int16_t *in, int16_t *out) > +{ > + v4hi v =3D *(v4hi*)in; > + *(v4hi*)out =3D v; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c b/gcc= /testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c > new file mode 100644 > index 00000000000..c30ed8f76f5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c > @@ -0,0 +1,152 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov0 (int32_t *in, int32_t *out) > +{ > + v1si v =3D *(v1si*)in; > + *(v1si*)out =3D v; > +} > + > +/* > +** mov1: > +** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov1 (int32_t *in, int32_t *out) > +{ > + v2si v =3D *(v2si*)in; > + *(v2si*)out =3D v; > +} > + > +/* > +** mov2: > +** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov2 (int32_t *in, int32_t *out) > +{ > + v4si v =3D *(v4si*)in; > + *(v4si*)out =3D v; > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov3 (int32_t *in, int32_t *out) > +{ > + v8si v =3D *(v8si*)in; > + *(v8si*)out =3D v; > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov4 (int32_t *in, int32_t *out) > +{ > + v16si v =3D *(v16si*)in; > + *(v16si*)out =3D v; > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov5 (int32_t *in, int32_t *out) > +{ > + v32si v =3D *(v32si*)in; > + *(v32si*)out =3D v; > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov6 (int32_t *in, int32_t *out) > +{ > + v64si v =3D *(v64si*)in; > + *(v64si*)out =3D v; > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov7 (int32_t *in, int32_t *out) > +{ > + v128si v =3D *(v128si*)in; > + *(v128si*)out =3D v; > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov8 (int32_t *in, int32_t *out) > +{ > + v256si v =3D *(v256si*)in; > + *(v256si*)out =3D v; > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov9 (int32_t *in, int32_t *out) > +{ > + v512si v =3D *(v512si*)in; > + *(v512si*)out =3D v; > +} > + > +/* > +** mov10: > +** li\s+[a-x0-9]+,1024 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov10 (int32_t *in, int32_t *out) > +{ > + v1024si v =3D *(v1024si*)in; > + *(v1024si*)out =3D v; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c b/gcc= /testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c > new file mode 100644 > index 00000000000..d6dbff1caa9 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv_zvfh_zvl4096b -mabi=3Dilp32d -O3 -fno-= schedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov: > +** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) > +** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov (int32_t *in, int32_t *out) > +{ > + v2si v =3D *(v2si*)in; > + *(v2si*)out =3D v; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c b/gcc= /testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c > new file mode 100644 > index 00000000000..46509e367c3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c > @@ -0,0 +1,139 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov0 (int64_t *in, int64_t *out) > +{ > + v1di v =3D *(v1di*)in; > + *(v1di*)out =3D v; > +} > + > +/* > +** mov1: > +** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov1 (int64_t *in, int64_t *out) > +{ > + v2di v =3D *(v2di*)in; > + *(v2di*)out =3D v; > +} > + > +/* > +** mov2: > +** vsetivli\s+zero,\s*4,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov2 (int64_t *in, int64_t *out) > +{ > + v4di v =3D *(v4di*)in; > + *(v4di*)out =3D v; > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov3 (int64_t *in, int64_t *out) > +{ > + v8di v =3D *(v8di*)in; > + *(v8di*)out =3D v; > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov4 (int64_t *in, int64_t *out) > +{ > + v16di v =3D *(v16di*)in; > + *(v16di*)out =3D v; > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov5 (int64_t *in, int64_t *out) > +{ > + v32di v =3D *(v32di*)in; > + *(v32di*)out =3D v; > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov6 (int64_t *in, int64_t *out) > +{ > + v64di v =3D *(v64di*)in; > + *(v64di*)out =3D v; > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov7 (int64_t *in, int64_t *out) > +{ > + v128di v =3D *(v128di*)in; > + *(v128di*)out =3D v; > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov8 (int64_t *in, int64_t *out) > +{ > + v256di v =3D *(v256di*)in; > + *(v256di*)out =3D v; > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au] > +** vle64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov9 (int64_t *in, int64_t *out) > +{ > + v512di v =3D *(v512di*)in; > + *(v512di*)out =3D v; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c b/gcc= /testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c > new file mode 100644 > index 00000000000..1cba7ddad94 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c > @@ -0,0 +1,166 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** flh\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** fsh\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov0 (_Float16 *in, _Float16 *out) > +{ > + v1hf v =3D *(v1hf*)in; > + *(v1hf*)out =3D v; > +} > + > +/* > +** mov1: > +** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov1 (_Float16 *in, _Float16 *out) > +{ > + v2hf v =3D *(v2hf*)in; > + *(v2hf*)out =3D v; > +} > + > +/* > +** mov2: > +** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov2 (_Float16 *in, _Float16 *out) > +{ > + v4hf v =3D *(v4hf*)in; > + *(v4hf*)out =3D v; > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov3 (_Float16 *in, _Float16 *out) > +{ > + v8hf v =3D *(v8hf*)in; > + *(v8hf*)out =3D v; > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov4 (_Float16 *in, _Float16 *out) > +{ > + v16hf v =3D *(v16hf*)in; > + *(v16hf*)out =3D v; > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov5 (_Float16 *in, _Float16 *out) > +{ > + v32hf v =3D *(v32hf*)in; > + *(v32hf*)out =3D v; > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov6 (_Float16 *in, _Float16 *out) > +{ > + v64hf v =3D *(v64hf*)in; > + *(v64hf*)out =3D v; > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov7 (_Float16 *in, _Float16 *out) > +{ > + v128hf v =3D *(v128hf*)in; > + *(v128hf*)out =3D v; > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov8 (_Float16 *in, _Float16 *out) > +{ > + v256hf v =3D *(v256hf*)in; > + *(v256hf*)out =3D v; > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov9 (_Float16 *in, _Float16 *out) > +{ > + v512hf v =3D *(v512hf*)in; > + *(v512hf*)out =3D v; > +} > + > +/* > +** mov10: > +** li\s+[a-x0-9]+,1024 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov10 (_Float16 *in, _Float16 *out) > +{ > + v1024hf v =3D *(v1024hf*)in; > + *(v1024hf*)out =3D v; > +} > + > +/* > +** mov11: > +** li\s+[a-x0-9]+,4096 > +** addi\s+[a-x0-9]+,[a-x0-9]+,-2048 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au] > +** vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov11 (_Float16 *in, _Float16 *out) > +{ > + v2048hf v =3D *(v2048hf*)in; > + *(v2048hf*)out =3D v; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c b/gcc= /testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c > new file mode 100644 > index 00000000000..0773f6a70f3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c > @@ -0,0 +1,152 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "def.h" > + > +/* > +** mov0: > +** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov0 (float *in, float *out) > +{ > + v1sf v =3D *(v1sf*)in; > + *(v1sf*)out =3D v; > +} > + > +/* > +** mov1: > +** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov1 (float *in, float *out) > +{ > + v2sf v =3D *(v2sf*)in; > + *(v2sf*)out =3D v; > +} > + > +/* > +** mov2: > +** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov2 (float *in, float *out) > +{ > + v4sf v =3D *(v4sf*)in; > + *(v4sf*)out =3D v; > +} > + > +/* > +** mov3: > +** vsetivli\s+zero,\s*8,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov3 (float *in, float *out) > +{ > + v8sf v =3D *(v8sf*)in; > + *(v8sf*)out =3D v; > +} > + > +/* > +** mov4: > +** vsetivli\s+zero,\s*16,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov4 (float *in, float *out) > +{ > + v16sf v =3D *(v16sf*)in; > + *(v16sf*)out =3D v; > +} > + > +/* > +** mov5: > +** li\s+[a-x0-9]+,32 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov5 (float *in, float *out) > +{ > + v32sf v =3D *(v32sf*)in; > + *(v32sf*)out =3D v; > +} > + > +/* > +** mov6: > +** li\s+[a-x0-9]+,64 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov6 (float *in, float *out) > +{ > + v64sf v =3D *(v64sf*)in; > + *(v64sf*)out =3D v; > +} > + > +/* > +** mov7: > +** li\s+[a-x0-9]+,128 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov7 (float *in, float *out) > +{ > + v128sf v =3D *(v128sf*)in; > + *(v128sf*)out =3D v; > +} > + > +/* > +** mov8: > +** li\s+[a-x0-9]+,256 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov8 (float *in, float *out) > +{ > + v256sf v =3D *(v256sf*)in; > + *(v256sf*)out =3D v; > +} > + > +/* > +** mov9: > +** li\s+[a-x0-9]+,512 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov9 (float *in, float *out) > +{ > + v512sf v =3D *(v512sf*)in; > + *(v512sf*)out =3D v; > +} > + > +/* > +** mov10: > +** li\s+[a-x0-9]+,1024 > +** vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au] > +** vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\) > +** ret > +*/ > +void mov10 (float *in, float *out) > +{ > + v1024sf v =3D *(v1024sf*)in; > + *(v1024sf*)out =3D v; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c b/g= cc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c > new file mode 100644 > index 00000000000..753fa254002 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c > @@ -0,0 +1,133 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > + > +#include "def.h" > + > +void > +spill_0 (int8_t *in, int8_t *out) > +{ > + v1qi v1 =3D *(v1qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1qi*)out =3D v1; > +} > + > +void > +spill_1 (int8_t *in, int8_t *out) > +{ > + v2qi v1 =3D *(v2qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v2qi*)out =3D v1; > +} > + > +void > +spill_2 (int8_t *in, int8_t *out) > +{ > + v4qi v1 =3D *(v4qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v4qi*)out =3D v1; > +} > + > +void > +spill_3 (int8_t *in, int8_t *out) > +{ > + v8qi v1 =3D *(v8qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v8qi*)out =3D v1; > +} > + > +void > +spill_4 (int8_t *in, int8_t *out) > +{ > + v16qi v1 =3D *(v16qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v16qi*)out =3D v1; > +} > + > +void > +spill_5 (int8_t *in, int8_t *out) > +{ > + v32qi v1 =3D *(v32qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v32qi*)out =3D v1; > +} > + > +void > +spill_6 (int8_t *in, int8_t *out) > +{ > + v64qi v1 =3D *(v64qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v64qi*)out =3D v1; > +} > + > +void > +spill_7 (int8_t *in, int8_t *out) > +{ > + v128qi v1 =3D *(v128qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v128qi*)out =3D v1; > +} > + > +void > +spill_8 (int8_t *in, int8_t *out) > +{ > + v256qi v1 =3D *(v256qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v256qi*)out =3D v1; > +} > + > +void > +spill_9 (int8_t *in, int8_t *out) > +{ > + v512qi v1 =3D *(v512qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v512qi*)out =3D v1; > +} > + > +void > +spill_10 (int8_t *in, int8_t *out) > +{ > + v1024qi v1 =3D *(v1024qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1024qi*)out =3D v1; > +} > + > +void > +spill_11 (int8_t *in, int8_t *out) > +{ > + v2048qi v1 =3D *(v2048qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v2048qi*)out =3D v1; > +} > + > +void > +spill_12 (int8_t *in, int8_t *out) > +{ > + v4096qi v1 =3D *(v4096qi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v4096qi*)out =3D v1; > +} > + > +/* { dg-final { scan-assembler-times {vle8\.v\tv[0-9]+,0\s*\([a-x0-9]+\)= } 26 } } */ > +/* { dg-final { scan-assembler-times {vse8\.v\tv[0-9]+,0\s*\([a-x0-9]+\)= } 26 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-16} 5 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-32} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-64} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-128} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ > +/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[= a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c b/g= cc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c > new file mode 100644 > index 00000000000..e8fa54c1c12 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c > @@ -0,0 +1,124 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > + > +#include "def.h" > + > +void > +spill_0 (int16_t *in, int16_t *out) > +{ > + v1hi v1 =3D *(v1hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1hi*)out =3D v1; > +} > + > +void > +spill_1 (int16_t *in, int16_t *out) > +{ > + v2hi v1 =3D *(v2hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v2hi*)out =3D v1; > +} > + > +void > +spill_2 (int16_t *in, int16_t *out) > +{ > + v4hi v1 =3D *(v4hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v4hi*)out =3D v1; > +} > + > +void > +spill_3 (int16_t *in, int16_t *out) > +{ > + v8hi v1 =3D *(v8hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v8hi*)out =3D v1; > +} > + > +void > +spill_4 (int16_t *in, int16_t *out) > +{ > + v16hi v1 =3D *(v16hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v16hi*)out =3D v1; > +} > + > +void > +spill_5 (int16_t *in, int16_t *out) > +{ > + v32hi v1 =3D *(v32hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v32hi*)out =3D v1; > +} > + > +void > +spill_6 (int16_t *in, int16_t *out) > +{ > + v64hi v1 =3D *(v64hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v64hi*)out =3D v1; > +} > + > +void > +spill_7 (int16_t *in, int16_t *out) > +{ > + v128hi v1 =3D *(v128hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v128hi*)out =3D v1; > +} > + > +void > +spill_8 (int16_t *in, int16_t *out) > +{ > + v256hi v1 =3D *(v256hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v256hi*)out =3D v1; > +} > + > +void > +spill_9 (int16_t *in, int16_t *out) > +{ > + v512hi v1 =3D *(v512hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v512hi*)out =3D v1; > +} > + > +void > +spill_10 (int16_t *in, int16_t *out) > +{ > + v1024hi v1 =3D *(v1024hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1024hi*)out =3D v1; > +} > + > +void > +spill_11 (int16_t *in, int16_t *out) > +{ > + v2048hi v1 =3D *(v2048hi*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v2048hi*)out =3D v1; > +} > + > +/* { dg-final { scan-assembler-times {vle16\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 24 } } */ > +/* { dg-final { scan-assembler-times {vse16\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 24 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-16} 4 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-32} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-64} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-128} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ > +/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[= a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c b/g= cc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c > new file mode 100644 > index 00000000000..86a404cc2a4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c > @@ -0,0 +1,115 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > + > +#include "def.h" > + > +void > +spill_0 (int32_t *in, int32_t *out) > +{ > + v1si v1 =3D *(v1si*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1si*)out =3D v1; > +} > + > +void > +spill_1 (int32_t *in, int32_t *out) > +{ > + v2si v1 =3D *(v2si*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v2si*)out =3D v1; > +} > + > +void > +spill_2 (int32_t *in, int32_t *out) > +{ > + v4si v1 =3D *(v4si*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v4si*)out =3D v1; > +} > + > +void > +spill_3 (int32_t *in, int32_t *out) > +{ > + v8si v1 =3D *(v8si*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v8si*)out =3D v1; > +} > + > +void > +spill_4 (int32_t *in, int32_t *out) > +{ > + v16si v1 =3D *(v16si*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v16si*)out =3D v1; > +} > + > +void > +spill_5 (int32_t *in, int32_t *out) > +{ > + v32si v1 =3D *(v32si*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v32si*)out =3D v1; > +} > + > +void > +spill_6 (int32_t *in, int32_t *out) > +{ > + v64si v1 =3D *(v64si*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v64si*)out =3D v1; > +} > + > +void > +spill_7 (int32_t *in, int32_t *out) > +{ > + v128si v1 =3D *(v128si*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v128si*)out =3D v1; > +} > + > +void > +spill_8 (int32_t *in, int32_t *out) > +{ > + v256si v1 =3D *(v256si*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v256si*)out =3D v1; > +} > + > +void > +spill_9 (int32_t *in, int32_t *out) > +{ > + v512si v1 =3D *(v512si*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v512si*)out =3D v1; > +} > + > +void > +spill_10 (int32_t *in, int32_t *out) > +{ > + v1024si v1 =3D *(v1024si*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1024si*)out =3D v1; > +} > + > +/* { dg-final { scan-assembler-times {vle32\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 22 } } */ > +/* { dg-final { scan-assembler-times {vse32\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 22 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-16} 3 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-32} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-64} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-128} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ > +/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[= a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c b/g= cc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c > new file mode 100644 > index 00000000000..ef61d9a2c0c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c > @@ -0,0 +1,106 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > + > +#include "def.h" > + > +void > +spill_0 (int64_t *in, int64_t *out) > +{ > + v1di v1 =3D *(v1di*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1di*)out =3D v1; > +} > + > +void > +spill_1 (int64_t *in, int64_t *out) > +{ > + v2di v1 =3D *(v2di*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v2di*)out =3D v1; > +} > + > +void > +spill_2 (int64_t *in, int64_t *out) > +{ > + v4di v1 =3D *(v4di*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v4di*)out =3D v1; > +} > + > +void > +spill_3 (int64_t *in, int64_t *out) > +{ > + v8di v1 =3D *(v8di*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v8di*)out =3D v1; > +} > + > +void > +spill_4 (int64_t *in, int64_t *out) > +{ > + v16di v1 =3D *(v16di*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v16di*)out =3D v1; > +} > + > +void > +spill_5 (int64_t *in, int64_t *out) > +{ > + v32di v1 =3D *(v32di*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v32di*)out =3D v1; > +} > + > +void > +spill_6 (int64_t *in, int64_t *out) > +{ > + v64di v1 =3D *(v64di*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v64di*)out =3D v1; > +} > + > +void > +spill_7 (int64_t *in, int64_t *out) > +{ > + v128di v1 =3D *(v128di*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v128di*)out =3D v1; > +} > + > +void > +spill_8 (int64_t *in, int64_t *out) > +{ > + v256di v1 =3D *(v256di*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v256di*)out =3D v1; > +} > + > +void > +spill_9 (int64_t *in, int64_t *out) > +{ > + v512di v1 =3D *(v512di*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v512di*)out =3D v1; > +} > + > +/* { dg-final { scan-assembler-times {vle64\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 20 } } */ > +/* { dg-final { scan-assembler-times {vse64\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 20 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-16} 2 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-32} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-64} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-128} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ > +/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[= a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c b/g= cc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c > new file mode 100644 > index 00000000000..7bff6e3cae8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c > @@ -0,0 +1,124 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > + > +#include "def.h" > + > +void > +spill_0 (_Float16 *in, _Float16 *out) > +{ > + v1hf v1 =3D *(v1hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1hf*)out =3D v1; > +} > + > +void > +spill_1 (_Float16 *in, _Float16 *out) > +{ > + v2hf v1 =3D *(v2hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v2hf*)out =3D v1; > +} > + > +void > +spill_2 (_Float16 *in, _Float16 *out) > +{ > + v4hf v1 =3D *(v4hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v4hf*)out =3D v1; > +} > + > +void > +spill_3 (_Float16 *in, _Float16 *out) > +{ > + v8hf v1 =3D *(v8hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v8hf*)out =3D v1; > +} > + > +void > +spill_4 (_Float16 *in, _Float16 *out) > +{ > + v16hf v1 =3D *(v16hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v16hf*)out =3D v1; > +} > + > +void > +spill_5 (_Float16 *in, _Float16 *out) > +{ > + v32hf v1 =3D *(v32hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v32hf*)out =3D v1; > +} > + > +void > +spill_6 (_Float16 *in, _Float16 *out) > +{ > + v64hf v1 =3D *(v64hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v64hf*)out =3D v1; > +} > + > +void > +spill_7 (_Float16 *in, _Float16 *out) > +{ > + v128hf v1 =3D *(v128hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v128hf*)out =3D v1; > +} > + > +void > +spill_8 (_Float16 *in, _Float16 *out) > +{ > + v256hf v1 =3D *(v256hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v256hf*)out =3D v1; > +} > + > +void > +spill_9 (_Float16 *in, _Float16 *out) > +{ > + v512hf v1 =3D *(v512hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v512hf*)out =3D v1; > +} > + > +void > +spill_10 (_Float16 *in, _Float16 *out) > +{ > + v1024hf v1 =3D *(v1024hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1024hf*)out =3D v1; > +} > + > +void > +spill_11 (_Float16 *in, _Float16 *out) > +{ > + v2048hf v1 =3D *(v2048hf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v2048hf*)out =3D v1; > +} > + > +/* { dg-final { scan-assembler-times {vle16\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 24 } } */ > +/* { dg-final { scan-assembler-times {vse16\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 24 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-16} 4 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-32} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-64} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-128} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ > +/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[= a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c b/g= cc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c > new file mode 100644 > index 00000000000..1e4eca3aac6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c > @@ -0,0 +1,115 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > + > +#include "def.h" > + > +void > +spill_0 (float *in, float *out) > +{ > + v1sf v1 =3D *(v1sf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1sf*)out =3D v1; > +} > + > +void > +spill_1 (float *in, float *out) > +{ > + v2sf v1 =3D *(v2sf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v2sf*)out =3D v1; > +} > + > +void > +spill_2 (float *in, float *out) > +{ > + v4sf v1 =3D *(v4sf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v4sf*)out =3D v1; > +} > + > +void > +spill_3 (float *in, float *out) > +{ > + v8sf v1 =3D *(v8sf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v8sf*)out =3D v1; > +} > + > +void > +spill_4 (float *in, float *out) > +{ > + v16sf v1 =3D *(v16sf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v16sf*)out =3D v1; > +} > + > +void > +spill_5 (float *in, float *out) > +{ > + v32sf v1 =3D *(v32sf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v32sf*)out =3D v1; > +} > + > +void > +spill_6 (float *in, float *out) > +{ > + v64sf v1 =3D *(v64sf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v64sf*)out =3D v1; > +} > + > +void > +spill_7 (float *in, float *out) > +{ > + v128sf v1 =3D *(v128sf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v128sf*)out =3D v1; > +} > + > +void > +spill_8 (float *in, float *out) > +{ > + v256sf v1 =3D *(v256sf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v256sf*)out =3D v1; > +} > + > +void > +spill_9 (float *in, float *out) > +{ > + v512sf v1 =3D *(v512sf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v512sf*)out =3D v1; > +} > + > +void > +spill_10 (float *in, float *out) > +{ > + v1024sf v1 =3D *(v1024sf*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1024sf*)out =3D v1; > +} > + > +/* { dg-final { scan-assembler-times {vle32\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 22 } } */ > +/* { dg-final { scan-assembler-times {vse32\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 22 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-16} 3 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-32} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-64} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-128} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ > +/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[= a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c b/g= cc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c > new file mode 100644 > index 00000000000..70ca683908d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c > @@ -0,0 +1,106 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2" } */ > + > +#include "def.h" > + > +void > +spill_0 (int64_t *in, int64_t *out) > +{ > + v1df v1 =3D *(v1df*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v1df*)out =3D v1; > +} > + > +void > +spill_1 (int64_t *in, int64_t *out) > +{ > + v2df v1 =3D *(v2df*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v2df*)out =3D v1; > +} > + > +void > +spill_2 (int64_t *in, int64_t *out) > +{ > + v4df v1 =3D *(v4df*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v4df*)out =3D v1; > +} > + > +void > +spill_3 (int64_t *in, int64_t *out) > +{ > + v8df v1 =3D *(v8df*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v8df*)out =3D v1; > +} > + > +void > +spill_4 (int64_t *in, int64_t *out) > +{ > + v16df v1 =3D *(v16df*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v16df*)out =3D v1; > +} > + > +void > +spill_5 (int64_t *in, int64_t *out) > +{ > + v32df v1 =3D *(v32df*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v32df*)out =3D v1; > +} > + > +void > +spill_6 (int64_t *in, int64_t *out) > +{ > + v64df v1 =3D *(v64df*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v64df*)out =3D v1; > +} > + > +void > +spill_7 (int64_t *in, int64_t *out) > +{ > + v128df v1 =3D *(v128df*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v128df*)out =3D v1; > +} > + > +void > +spill_8 (int64_t *in, int64_t *out) > +{ > + v256df v1 =3D *(v256df*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v256df*)out =3D v1; > +} > + > +void > +spill_9 (int64_t *in, int64_t *out) > +{ > + v512df v1 =3D *(v512df*)in; > + exhaust_vector_regs (); > + asm volatile ("" ::: "memory"); > + *(v512df*)out =3D v1; > +} > + > +/* { dg-final { scan-assembler-times {vle64\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 20 } } */ > +/* { dg-final { scan-assembler-times {vse64\.v\tv[0-9]+,0\s*\([a-x0-9]+\= )} 20 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-16} 2 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-32} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-64} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-128} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ > +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ > +/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[= a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/g= cc.target/riscv/rvv/rvv.exp > index 532c17c4065..b41553bc2f5 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > @@ -48,6 +48,8 @@ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir= /vsetvl/*.\[cS\]]] \ > "" $CFLAGS > dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ > "-O3 -ftree-vectorize" $CFLAGS > +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls/*.\[cS\]= ]] \ > + "-O3 -ftree-vectorize --param riscv-autovec-preference=3Dscalable= " $CFLAGS > > set AUTOVEC_TEST_OPTS [list \ > {-ftree-vectorize -O3 --param riscv-autovec-lmul=3Dm1} \ > -- > 2.36.1 >