From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by sourceware.org (Postfix) with ESMTPS id 8A2C53858D33 for ; Wed, 26 Apr 2023 03:29:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8A2C53858D33 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2a8ba23a2abso63177351fa.2 for ; Tue, 25 Apr 2023 20:29:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1682479784; x=1685071784; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=VSF0jq8j9xgpM9y3/lAt4VimOE4Femwbs6EIwDjxiOk=; b=hUuVaKIs4g9eeHlxC+SKmPOeR3AZoCeoWvdIq5gDxxVm8be6TNXd3JkvPJYgMO2hYp 81wQgRAxf/n+yWcbFdzvFcec5rIjhRFoHKIlshfn99ovXNqHqGYn2/OiSL1Ryw8XbQPY lYA4wz/Th1uuQ3grLhKCNUh0JoNZNPLyogveAONy0sqb0U+4YRQ0VfwgHF6sO6tBYtkt A0zxFnSPw2anQH23hZXV1uFCFZY7Fedr7QUSYILNzXHj9FCMNAsml8Jn7xq6OVZc6QL3 ZBDJwg3anaDAwviCxF/YypBy9Zuv2uRYZyChHO+COBzVE0UvoRNAYzS72gzARlhhZ2CZ P9AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682479784; x=1685071784; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=VSF0jq8j9xgpM9y3/lAt4VimOE4Femwbs6EIwDjxiOk=; b=X62jq5cmNLszHHL6rBaZ7QVSzt5X7dPh0JOwIbEZdoMsA7Dv4fCRGsFWPAwlFefauN Du7T/rVBh2qd3lxUoJ9UerCYeHknzsB+o+yapLrv4lX/vZM+ORuxPGQxnMFB8BpERy+j awgXCQMb6oEvD6/DQoPkl78TkgjL/phUvatSaUfsyP8DmKFIcysWkUNswP4kTccO1N2g MAawkqQDXk8OgS+w6kWhgpI500uNXsTz/IczmZb/7SSexQxFj7gYaE5aGzReJ7PKy9O+ 7bN7VSlfWphG5Pj1XECslrt39Pv9i/zdXqNUULmySB1n7gL7mt4kJFatTzafQIz2hHJ8 TECQ== X-Gm-Message-State: AAQBX9deUEZNIeTirAUv+pqS16IZtgMAONtBm82662tsunSz84DGGSt0 5zvNVrMCS1mwvIvXT3H7TZzciRwfNw4DVLrLULWnEg== X-Google-Smtp-Source: AKy350byAMqkLIOpxIivV3m72gxqxn4AFUrdrkp/LjNy9sDKNHgkdAKNGjlf+wS5nbujF7OIrPn1rpgbBk3nEKEspb8= X-Received: by 2002:a2e:9c05:0:b0:2a8:a5fc:d0cd with SMTP id s5-20020a2e9c05000000b002a8a5fcd0cdmr4059065lji.47.1682479784564; Tue, 25 Apr 2023 20:29:44 -0700 (PDT) MIME-Version: 1.0 References: <20230329075222.2888608-1-pan2.li@intel.com> <20230425142904.133137-1-pan2.li@intel.com> In-Reply-To: <20230425142904.133137-1-pan2.li@intel.com> From: Kito Cheng Date: Wed, 26 Apr 2023 11:29:33 +0800 Message-ID: Subject: Re: [PATCH v3] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal To: pan2.li@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, yanzhang.wang@intel.com Content-Type: multipart/alternative; boundary="000000000000e6bc3105fa34d9c2" X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SCC_10_SHORT_WORD_LINES,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000e6bc3105fa34d9c2 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Committed, thanks! On Tue, Apr 25, 2023 at 10:29=E2=80=AFPM wrote: > From: Pan Li > > In most architecture the precision_size of vbool*_t types are caculated > like as the multiple of the type size. For example: > precision_size =3D type_size * 8 (aka, bit count per bytes). > > Unfortunately, some architecture like RISC-V will adjust the > precision_size > for the vbool*_t in order to align the ISA. For example as below. > type_size =3D [1, 1, 1, 1, 2, 4, 8] > precision_size =3D [1, 2, 4, 8, 16, 32, 64] > > Then the precision_size of RISC-V vbool*_t will not be the multiple of > the > type_size. This PATCH try to enrich this case when comparing the > vn_reference. > > Given we have the below code: > void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict > out) { > vbool8_t v1 =3D *(vbool8_t*)in; > vbool16_t v2 =3D *(vbool16_t*)in; > > *(vbool8_t*)(out + 100) =3D v1; > *(vbool16_t*)(out + 200) =3D v2; > } > > Before this PATCH: > csrr t0,vlenb > slli t1,t0,1 > csrr a3,vlenb > sub sp,sp,t1 > slli a4,a3,1 > add a4,a4,sp > addi a2,a1,100 > vsetvli a5,zero,e8,m1,ta,ma > sub a3,a4,a3 > vlm.v v24,0(a0) > vsm.v v24,0(a2) > vsm.v v24,0(a3) > addi a1,a1,200 > csrr t0,vlenb > vsetvli a4,zero,e8,mf2,ta,ma > slli t1,t0,1 > vlm.v v24,0(a3) > vsm.v v24,0(a1) > add sp,sp,t1 > jr ra > > After this PATCH: > addi a3,a1,100 > vsetvli a4,zero,e8,m1,ta,ma > addi a1,a1,200 > vlm.v v24,0(a0) > vsm.v v24,0(a3) > vsetvli a5,zero,e8,mf2,ta,ma > vlm.v v24,0(a0) > vsm.v v24,0(a1) > ret > > PR 109272 > > gcc/ChangeLog: > > * tree-ssa-sccvn.cc (vn_reference_eq): add type vector subparts > check for vn_reference equal. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/pr108185-4.c: Update test check > condition. > * gcc.target/riscv/rvv/base/pr108185-5.c: Likewise. > * gcc.target/riscv/rvv/base/pr108185-6.c: Likewise. > > Signed-off-by: Pan Li > --- > .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +- > .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +- > .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +- > gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++ > 4 files changed, 23 insertions(+), 3 deletions(-) > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c > index 6e4d1cb1e44..321cd5c818e 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c > @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * > restrict out) { > /* { dg-final { scan-assembler-times > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ > -/* { dg-final { scan-assembler-times > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */ > +/* { dg-final { scan-assembler-times > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c > index 9fc659d2402..575a7842cdf 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c > @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * > restrict out) { > /* { dg-final { scan-assembler-times > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ > -/* { dg-final { scan-assembler-times > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */ > +/* { dg-final { scan-assembler-times > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c > index 98275e5267d..95a11d37016 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c > @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * > restrict out) { > /* { dg-final { scan-assembler-times > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ > -/* { dg-final { scan-assembler-times > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */ > +/* { dg-final { scan-assembler-times > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ > diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc > index 94b793e1caf..94d6163e6ae 100644 > --- a/gcc/tree-ssa-sccvn.cc > +++ b/gcc/tree-ssa-sccvn.cc > @@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, > const_vn_reference_t const vr2) > && (TYPE_PRECISION (vr2->type) > !=3D TREE_INT_CST_LOW (TYPE_SIZE (vr2->type)))) > return false; > + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type) > + && VECTOR_BOOLEAN_TYPE_P (vr2->type)) > + { > + /* Vector boolean types can have padding, verify we are dealing wi= th > + the same number of elements, aka the precision of the types. > + For example, In most architecture the precision_size of vbool*_t > + types are caculated like below: > + precision_size =3D type_size * 8 > + > + Unfortunately, the RISC-V will adjust the precision_size for the > + vbool*_t in order to align the ISA as below: > + type_size =3D [1, 1, 1, 1, 2, 4, 8] > + precision_size =3D [1, 2, 4, 8, 16, 32, 64] > + > + Then the precision_size of RISC-V vbool*_t will not be the > multiple > + of the type_size. We take care of this case consolidated here. > */ > + if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type), > + TYPE_VECTOR_SUBPARTS (vr2->type))) > + return false; > + } > > i =3D 0; > j =3D 0; > -- > 2.34.1 > > --000000000000e6bc3105fa34d9c2--