From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by sourceware.org (Postfix) with ESMTPS id DC51B3858D32 for ; Wed, 28 Jun 2023 03:16:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC51B3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-262e839647eso2513352a91.2 for ; Tue, 27 Jun 2023 20:16:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1687922194; x=1690514194; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=VvC539pIA3AcEexNY2gU9qRXvEGCH04j70n0MULDHG8=; b=Ut31wqC7zgBbknsTx4QjcLI+FNiai23WEWJJSXWCbd8td0BwU+J95DpdXyBONVf4GA asfR+HktQcz0q0sCs0hCxda0YTsCeOZ9FreNp9DDC+oVN59LlvBfwjqocxe+bCAmqEv1 Rzs5m2MDHgvuQdSaqHAPjbd0ryiaBY0MjBz5vjkCPaaSnG7y62K120xsFSAwwuLKE4IH rVuhqGyEj5NMvQiF8irTcPhalVzwvnYJMzX6p4LD+JYDJoYGN6WpuIUtav0c/EFXsFYV 9bkEG04QnYePTDbyf2Pc1uW5ADcFicuAgqlZhRCqqe+1c4dXNoqiO3BUfdSwJvdjt5aS qvQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687922194; x=1690514194; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VvC539pIA3AcEexNY2gU9qRXvEGCH04j70n0MULDHG8=; b=YB8EoBQlF4CGpYzZCC4aeB7S4utHh3RiIE1dfGl+wJjyyGIJnJDdqiZS9JuExfYW+9 d0XktW6Ag/v+FTyOxlBE8sfc3do7vb1nMCLGrvDKFD20nQJIvuPj5SqHRt78I42OtomW pDwgTPKrWWIapVSNGGxkeyzaNC5U2KubgntEOkD2W4RCUHJmTeLuP036HvGiTVqeMLhW 82cn+Q335JkY9neJTdUHOwgoWiUaeSehN/iXWPWh+Uh6vOoCVmZ8S2YlHvj6gEo/VBcO n32mQk62JcYXmb4VFPWnEQ9toHcVaWcnglotp27KaZNLqhp6I7c5NBfeNeWAgWFUnmUS UsiA== X-Gm-Message-State: AC+VfDw1QzT9C/bHE7BoSgm7A5qJiosThalQNLZdBehNR/0mzPp/tfkU r3LmaV1hC5YDpF84amq7rCNyTzYJ+ircFKJQatnz3w== X-Google-Smtp-Source: ACHHUZ4SKBwNVqLloPBv/eg6xAJM/BtCldLXdIIgdgXst4OLB5e+AS87WgcDw3n25/isyvSPTdnzvHtcmkEfhUcyD5Q= X-Received: by 2002:a17:90a:199b:b0:260:de07:c656 with SMTP id 27-20020a17090a199b00b00260de07c656mr22484920pji.25.1687922193608; Tue, 27 Jun 2023 20:16:33 -0700 (PDT) MIME-Version: 1.0 References: <20230628015944.112659-1-juzhe.zhong@rivai.ai> In-Reply-To: From: Kito Cheng Date: Wed, 28 Jun 2023 11:16:22 +0800 Message-ID: Subject: Re: [PATCH V2] RISC-V: Fix bug of pre-calculated const vector mask To: "juzhe.zhong@rivai.ai" Cc: gcc-patches , "kito.cheng" , palmer , palmer , jeffreyalaw , Robin Dapp Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SCC_10_SHORT_WORD_LINES,SCC_20_SHORT_WORD_LINES,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Do you mind giving some comments about what the difference between the two versions? On Wed, Jun 28, 2023 at 11:14=E2=80=AFAM juzhe.zhong@rivai.ai wrote: > > This patch is the critical patch for following patches since it is a bug = which I already address in rvv-next. > > ________________________________ > juzhe.zhong@rivai.ai > > > From: Juzhe-Zhong > Date: 2023-06-28 09:59 > To: gcc-patches > CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe= -Zhong > Subject: [PATCH V2] RISC-V: Fix bug of pre-calculated const vector mask > This bug blocks the following patches. > > GCC doesn't know RVV is using compact mask model. > Consider this following case: > > #define N 16 > > int > main () > { > int8_t mask[N] =3D {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; > int8_t out[N] =3D {0}; > for (int8_t i =3D 0; i < N; ++i) > if (mask[i]) > out[i] =3D i; > for (int8_t i =3D 0; i < N; ++i) > { > if (mask[i]) > assert (out[i] =3D=3D i); > else > assert (out[i] =3D=3D 0); > } > } > > Before this patch, the pre-calculated mask in constant memory pool: > .LC1: > .byte 68 =3D=3D=3D=3D> 0b01000100 > > This is incorrect, such case failed in execution. > > After this patch: > .LC1: > .byte 10 =3D=3D=3D=3D> 0b1010 > > Pass on exection. > > gcc/ChangeLog: > > * config/riscv/riscv-v.cc (rvv_builder::get_compact_mask): New fu= nction. > (expand_const_vector): Ditto. > * config/riscv/riscv.cc (riscv_const_insns): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: New test. > * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: New test. > * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: New test. > * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: New test. > * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: New test. > * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: New test. > * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: New test. > * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: New test. > * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: New test. > > --- > gcc/config/riscv/riscv-v.cc | 64 +++++++++++++++++-- > gcc/config/riscv/riscv.cc | 6 ++ > .../riscv/rvv/autovec/vls-vlmax/bitmask-1.c | 23 +++++++ > .../riscv/rvv/autovec/vls-vlmax/bitmask-2.c | 23 +++++++ > .../riscv/rvv/autovec/vls-vlmax/bitmask-3.c | 23 +++++++ > .../riscv/rvv/autovec/vls-vlmax/bitmask-4.c | 23 +++++++ > .../riscv/rvv/autovec/vls-vlmax/bitmask-5.c | 25 ++++++++ > .../riscv/rvv/autovec/vls-vlmax/bitmask-6.c | 27 ++++++++ > .../riscv/rvv/autovec/vls-vlmax/bitmask-7.c | 30 +++++++++ > .../riscv/rvv/autovec/vls-vlmax/bitmask-8.c | 30 +++++++++ > .../riscv/rvv/autovec/vls-vlmax/bitmask-9.c | 30 +++++++++ > 11 files changed, 299 insertions(+), 5 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/b= itmask-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/b= itmask-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/b= itmask-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/b= itmask-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/b= itmask-5.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/b= itmask-6.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/b= itmask-7.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/b= itmask-8.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/b= itmask-9.c > > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index adb8d7d36a5..5da0dc5e998 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -291,6 +291,7 @@ public: > bool single_step_npatterns_p () const; > bool npatterns_all_equal_p () const; > + rtx get_compact_mask () const; > machine_mode new_mode () const { return m_new_mode; } > scalar_mode inner_mode () const { return m_inner_mode; } > @@ -505,6 +506,47 @@ rvv_builder::npatterns_all_equal_p () const > return true; > } > +/* Generate the compact mask. > + > + E.g: mask =3D { 0, -1 }, mode =3D VNx2BI, bitsize =3D 128bits. > + > + GCC by default will generate the mask =3D 0b00000001xxxxx. > + > + However, it's not expected mask for RVV since RVV > + prefers the compact mask =3D 0b10xxxxx. > +*/ > +rtx > +rvv_builder::get_compact_mask () const > +{ > + /* If TARGET_MIN_VLEN =3D=3D 32, the minimum LMUL =3D 1/4. > + Otherwise, the minimum LMUL =3D 1/8. */ > + unsigned min_lmul =3D TARGET_MIN_VLEN =3D=3D 32 ? 4 : 8; > + unsigned min_container_size > + =3D BYTES_PER_RISCV_VECTOR.to_constant () / min_lmul; > + unsigned container_size =3D MAX (CEIL (npatterns (), 8), min_container= _size); > + machine_mode container_mode > + =3D get_vector_mode (QImode, container_size).require (); > + > + unsigned nunits =3D GET_MODE_NUNITS (container_mode).to_constant (); > + rtvec v =3D rtvec_alloc (nunits); > + for (unsigned i =3D 0; i < nunits; i++) > + RTVEC_ELT (v, i) =3D const0_rtx; > + > + unsigned char b =3D 0; > + for (unsigned i =3D 0; i < npatterns (); i++) > + { > + if (INTVAL (elt (i))) > + b =3D b | (1 << (i % 8)); > + > + if ((i > 0 && (i % 8) =3D=3D 7) || (i =3D=3D (npatterns () - 1))) > + { > + RTVEC_ELT (v, ((i + 7) / 8) - 1) =3D gen_int_mode (b, QImode); > + b =3D 0; > + } > + } > + return gen_rtx_CONST_VECTOR (container_mode, v); > +} > + > static unsigned > get_sew (machine_mode mode) > { > @@ -1141,11 +1183,23 @@ expand_const_vector (rtx target, rtx src) > if (GET_MODE_CLASS (mode) =3D=3D MODE_VECTOR_BOOL) > { > rtx elt; > - gcc_assert ( > - const_vec_duplicate_p (src, &elt) > - && (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx))); > - rtx ops[] =3D {target, src}; > - emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); > + unsigned int nelts; > + if (const_vec_duplicate_p (src, &elt)) > + { > + rtx ops[] =3D {target, src}; > + emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); > + } > + else if (GET_MODE_NUNITS (mode).is_constant (&nelts)) > + { > + rvv_builder builder (mode, nelts, 1); > + for (unsigned int i =3D 0; i < nelts; i++) > + builder.quick_push (CONST_VECTOR_ELT (src, i)); > + rtx mask =3D builder.get_compact_mask (); > + rtx mem =3D validize_mem (force_const_mem (GET_MODE (mask), mask)); > + emit_move_insn (target, gen_rtx_MEM (mode, XEXP (mem, 0))); > + } > + else > + gcc_unreachable (); > return; > } > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 280aa0b33b9..86c83f0906d 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -1323,6 +1323,12 @@ riscv_const_insns (rtx x) > return 1 + 4; /*vmv.v.x + memory access. */ > } > } > + > + /* GCC doesn't known RVV is using compact model of mask, > + we should by default handle mask in mov pattern. */ > + if (GET_MODE_CLASS (GET_MODE (x)) =3D=3D MODE_VECTOR_BOOL) > + /* TODO: We can adjust it according real cost model of vlm.v. */ > + return 1; > } > /* TODO: We may support more const vector in the future. */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask= -1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c > new file mode 100644 > index 00000000000..81229fd62b9 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c > @@ -0,0 +1,23 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-options "--param riscv-autovec-preference=3Dfixed-vlmax -O3" } *= / > + > +#include > +#include > +#define N 16 > + > +int > +main () > +{ > + int mask[N] =3D {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; > + int64_t out[N] =3D {0}; > + for (int i =3D 0; i < N; ++i) > + if (mask[i]) > + out[i] =3D i; > + for (int i =3D 0; i < N; ++i) > + { > + if (mask[i]) > + assert (out[i] =3D=3D i); > + else > + assert (out[i] =3D=3D 0); > + } > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask= -2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c > new file mode 100644 > index 00000000000..a23e47171bc > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c > @@ -0,0 +1,23 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-options "--param riscv-autovec-preference=3Dfixed-vlmax -O3" } *= / > + > +#include > +#include > +#define N 16 > + > +int > +main () > +{ > + int mask[N] =3D {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; > + int out[N] =3D {0}; > + for (int i =3D 0; i < N; ++i) > + if (mask[i]) > + out[i] =3D i; > + for (int i =3D 0; i < N; ++i) > + { > + if (mask[i]) > + assert (out[i] =3D=3D i); > + else > + assert (out[i] =3D=3D 0); > + } > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask= -3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c > new file mode 100644 > index 00000000000..6ea8fdd89c0 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c > @@ -0,0 +1,23 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-options "--param riscv-autovec-preference=3Dfixed-vlmax -O3" } *= / > + > +#include > +#include > +#define N 16 > + > +int > +main () > +{ > + int16_t mask[N] =3D {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; > + int16_t out[N] =3D {0}; > + for (int16_t i =3D 0; i < N; ++i) > + if (mask[i]) > + out[i] =3D i; > + for (int16_t i =3D 0; i < N; ++i) > + { > + if (mask[i]) > + assert (out[i] =3D=3D i); > + else > + assert (out[i] =3D=3D 0); > + } > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask= -4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c > new file mode 100644 > index 00000000000..2d97c26abfd > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c > @@ -0,0 +1,23 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-options "--param riscv-autovec-preference=3Dfixed-vlmax -O3" } *= / > + > +#include > +#include > +#define N 16 > + > +int > +main () > +{ > + int8_t mask[N] =3D {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; > + int8_t out[N] =3D {0}; > + for (int8_t i =3D 0; i < N; ++i) > + if (mask[i]) > + out[i] =3D i; > + for (int8_t i =3D 0; i < N; ++i) > + { > + if (mask[i]) > + assert (out[i] =3D=3D i); > + else > + assert (out[i] =3D=3D 0); > + } > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask= -5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c > new file mode 100644 > index 00000000000..b89b70e99a6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c > @@ -0,0 +1,25 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-options "--param riscv-autovec-preference=3Dfixed-vlmax --param = riscv-autovec-lmul=3Dm2 -O3" } */ > + > +#include > +#include > + > +#define N 32 > + > +int > +main () > +{ > + int8_t mask[N] =3D {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; > + int8_t out[N] =3D {0}; > + for (int8_t i =3D 0; i < N; ++i) > + if (mask[i]) > + out[i] =3D i; > + for (int8_t i =3D 0; i < N; ++i) > + { > + if (mask[i]) > + assert (out[i] =3D=3D i); > + else > + assert (out[i] =3D=3D 0); > + } > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask= -6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c > new file mode 100644 > index 00000000000..ac8d91e793b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c > @@ -0,0 +1,27 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-options "--param riscv-autovec-preference=3Dfixed-vlmax --param = riscv-autovec-lmul=3Dm4 -O3" } */ > + > +#include > +#include > + > +#define N 64 > + > +int > +main () > +{ > + int8_t mask[N] =3D {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; > + int8_t out[N] =3D {0}; > + for (int8_t i =3D 0; i < N; ++i) > + if (mask[i]) > + out[i] =3D i; > + for (int8_t i =3D 0; i < N; ++i) > + { > + if (mask[i]) > + assert (out[i] =3D=3D i); > + else > + assert (out[i] =3D=3D 0); > + } > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask= -7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c > new file mode 100644 > index 00000000000..f538db23b1d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c > @@ -0,0 +1,30 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-options "--param riscv-autovec-preference=3Dfixed-vlmax --param = riscv-autovec-lmul=3Dm8 -O3" } */ > + > +#include > +#include > + > +#define N 128 > + > +int > +main () > +{ > + uint8_t mask[N] > + =3D {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, = 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; > + uint8_t out[N] =3D {0}; > + for (uint8_t i =3D 0; i < N; ++i) > + if (mask[i]) > + out[i] =3D i; > + for (uint8_t i =3D 0; i < N; ++i) > + { > + if (mask[i]) > + assert (out[i] =3D=3D i); > + else > + assert (out[i] =3D=3D 0); > + } > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask= -8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c > new file mode 100644 > index 00000000000..5abb34c1686 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c > @@ -0,0 +1,30 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-options "--param riscv-autovec-preference=3Dfixed-vlmax --param = riscv-autovec-lmul=3Dm8 -O3" } */ > + > +#include > +#include > + > +#define N 128 > + > +int > +main () > +{ > + int mask[N] > + =3D {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, = 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; > + int out[N] =3D {0}; > + for (int i =3D 0; i < N; ++i) > + if (mask[i]) > + out[i] =3D i; > + for (int i =3D 0; i < N; ++i) > + { > + if (mask[i]) > + assert (out[i] =3D=3D i); > + else > + assert (out[i] =3D=3D 0); > + } > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask= -9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c > new file mode 100644 > index 00000000000..6fdaa516534 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c > @@ -0,0 +1,30 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-options "--param riscv-autovec-preference=3Dfixed-vlmax --param = riscv-autovec-lmul=3Dm8 -O3" } */ > + > +#include > +#include > + > +#define N 128 > + > +int > +main () > +{ > + int64_t mask[N] > + =3D {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, = 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, > + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; > + int64_t out[N] =3D {0}; > + for (int i =3D 0; i < N; ++i) > + if (mask[i]) > + out[i] =3D i; > + for (int i =3D 0; i < N; ++i) > + { > + if (mask[i]) > + assert (out[i] =3D=3D i); > + else > + assert (out[i] =3D=3D 0); > + } > +} > -- > 2.36.1 >