Re: [PATCH 08/11] riscv: Prepare backend for index registers

[Kito Cheng <kito.cheng@sifive.com>]

OK

On Fri, Apr 28, 2023 at 2:12 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> RISC-V does currently not support index registers.
> However, there are some vendor extensions that specify them.
> Let's do the necessary changes in the backend so that we can
> add support for such a vendor extension in the future.
>
> This is a non-functional change without any intended side-effects.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-protos.h (riscv_regno_ok_for_index_p):
>         New prototype.
>         (riscv_index_reg_class): Likewise.
>         * config/riscv/riscv.cc (riscv_regno_ok_for_index_p): New function.
>         (riscv_index_reg_class): New function.
>         * config/riscv/riscv.h (INDEX_REG_CLASS): Call new function
>         riscv_index_reg_class().
>         (REGNO_OK_FOR_INDEX_P): Call new function
>         riscv_regno_ok_for_index_p().
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv-protos.h |  2 ++
>  gcc/config/riscv/riscv.cc       | 20 ++++++++++++++++++++
>  gcc/config/riscv/riscv.h        |  6 ++++--
>  3 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 628c64cf628..b7417e97d99 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -82,6 +82,8 @@ struct riscv_address_info {
>  extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
>  extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
>  extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
> +extern enum reg_class riscv_index_reg_class ();
> +extern int riscv_regno_ok_for_index_p (int);
>  extern int riscv_address_insns (rtx, machine_mode, bool);
>  extern int riscv_const_insns (rtx);
>  extern int riscv_split_const_insns (rtx);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 8388235d8cc..a33f0fff8ea 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -827,6 +827,26 @@ riscv_regno_mode_ok_for_base_p (int regno,
>    return GP_REG_P (regno);
>  }
>
> +/* Get valid index register class.
> +   The RISC-V base instructions don't support index registers,
> +   but extensions might support that.  */
> +
> +enum reg_class
> +riscv_index_reg_class ()
> +{
> +  return NO_REGS;
> +}
> +
> +/* Return true if register REGNO is a valid index register.
> +   The RISC-V base instructions don't support index registers,
> +   but extensions might support that.  */
> +
> +int
> +riscv_regno_ok_for_index_p (int regno)
> +{
> +  return 0;
> +}
> +
>  /* Return true if X is a valid base register for mode MODE.
>     STRICT_P is true if REG_OK_STRICT is in effect.  */
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 90746fe14e3..21b81c22dea 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -535,7 +535,7 @@ enum reg_class
>     factor or added to another register (as well as added to a
>     displacement).  */
>
> -#define INDEX_REG_CLASS NO_REGS
> +#define INDEX_REG_CLASS riscv_index_reg_class()
>
>  /* We generally want to put call-clobbered registers ahead of
>     call-saved ones.  (IRA expects this.)  */
> @@ -705,7 +705,9 @@ typedef struct {
>
>  /* Addressing modes, and classification of registers for them.  */
>
> -#define REGNO_OK_FOR_INDEX_P(REGNO) 0
> +#define REGNO_OK_FOR_INDEX_P(REGNO) \
> +  riscv_regno_ok_for_index_p (REGNO)
> +
>  #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
>    riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
>
> --
> 2.40.1
>