From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by sourceware.org (Postfix) with ESMTPS id 322FC3858C2B for ; Thu, 20 Jul 2023 08:24:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 322FC3858C2B Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-262e04a6f66so211118a91.0 for ; Thu, 20 Jul 2023 01:24:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1689841454; x=1690446254; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=EHLZBrd2j0y3lwP+aQwqj6XlyTx6BZOf23O/J7Nhi3A=; b=jTBU2BP08+G6Oz3M0ituNk7VpSaCBz1e6a8FZ0/xYrjf7MRF2+BdqsjwQwRy+dzAqd /6PyIsOXmHjl0TaOQz/CtVNThZe+jBmhNw39zEB1UZ5HRBwJVykIRnngdGxrA0SNp8os 9RSLg1vqhfyjIOUT+yOyP/QBE68iP+1RTNW7ogecyYWV3SaIENGlMHHy1Y4U16XIdXSf EKOqO/b/5s7T6VaRCGS8J7Q4Rxxqm8wRtx/e7MCV8w8HUlMS+wmMNb/7n9HkGTjr1vbK wfl0nYTY+lBkCRGGgCsmMchyBvvqsrg8cW6D3jJuppvfspFuauL4FwperqSyaOcZBr/H JXaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689841454; x=1690446254; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EHLZBrd2j0y3lwP+aQwqj6XlyTx6BZOf23O/J7Nhi3A=; b=aO07NKVa/gfqKNS7y8lYsK5TkG+hUmeznRPPfztBNEDo4HIxVlcXyf2uhLwoyA3dnq CsT8Td9x0jHabPH3alRTdcKB1OKLJDcOcwG6bateOjKCgtBsU+yJUl7lRnLtMDXnFGkq 5dNcv9r147fiLVnGmgU72Pb4hhYrGMRR/K1qeUFRcxDN/ihOwz4KWrjR7rijcHxVuo0u SYEtCOR4fv46MnidqXBDkn9pWAJJhUQDi+aB2SU10VubvfP1XFbWD/2OfqJA5HkGZOK9 6BEWBOibnD8CdBoZ455favXv7Pl+w9xgYCmoeV6mNBU6ZCm5bYstlJ5qoimQi/GHwytY hOkw== X-Gm-Message-State: ABy/qLbhpC5yEZwIy/oKVfNgT7y+NPUh+TuS/1/SjxuB/2wFbjvN9+i8 kUIlT+3r4pr/61b56cl/6kkPhBk43kBSEYAw9zL9wA== X-Google-Smtp-Source: APBJJlEWn4DLJTOaq1B/BeWF1KbbCvLiTO5FvF7LMZ6JZDe1ydA8TGx904d0Iq/rPRyp86sHWF5t/tHNOXK9vKxHJRA= X-Received: by 2002:a17:90a:5d82:b0:263:1720:f802 with SMTP id t2-20020a17090a5d8200b002631720f802mr15827353pji.30.1689841453643; Thu, 20 Jul 2023 01:24:13 -0700 (PDT) MIME-Version: 1.0 References: <20230720073406.239379-1-juzhe.zhong@rivai.ai> <3684FC24D86A4D06+202307201542514213108@rivai.ai> <48fab29b-bfbe-e743-f279-94c23293c983@gmail.com> <4938A9FAF509F21E+2023072016161542402420@rivai.ai> In-Reply-To: <4938A9FAF509F21E+2023072016161542402420@rivai.ai> From: Kito Cheng Date: Thu, 20 Jul 2023 16:24:02 +0800 Message-ID: Subject: Re: Re: [PATCH] RISC-V: Support in-order floating-point reduction To: "juzhe.zhong@rivai.ai" Cc: Robin Dapp , gcc-patches , "kito.cheng" , jeffreyalaw Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: reduction_type =3D reduction_type::UNORDERED On Thu, Jul 20, 2023 at 4:16=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > I have tried this: > enum class reduction_type > { > UNORDERED, > FOLD_LEFT, > MASK_LEN_FOLD_LEFT, > }; > > But fail to build..... > > /gcc/build -I../../../riscv-gcc/gcc/../include -I../../../riscv-gcc/gcc/= ../libcpp/include -g -O0 \ > -o build/gencondmd.o build/gencondmd.cc > In file included from ./tm_p.h:4:0, > from build/gencondmd.cc:29: > ../../../riscv-gcc/gcc/config/riscv/riscv-protos.h:294:36: error: could n= ot convert =E2=80=98UNORDERED=E2=80=99 from =E2=80=98rtx_code=E2=80=99 to = =E2=80=98riscv_vector::reduction_type=E2=80=99 > reduction_type =3D UNORDERED); > > ________________________________ > juzhe.zhong@rivai.ai > > > From: Kito Cheng > Date: 2023-07-20 16:03 > To: juzhe.zhong@rivai.ai > CC: Robin Dapp; gcc-patches; kito.cheng; jeffreyalaw > Subject: Re: Re: [PATCH] RISC-V: Support in-order floating-point reductio= n > Seems like because you ` using namespace riscv_vector;` so the > UNORDERED in expand_vec_cmp_float used reduction_type::UNORDERED > > Hmmm, maybe enum class? > > enum class reduction_type > { > UNORDERED, > FOLD_LEFT, > MASK_LEN_FOLD_LEFT, > }; > > and need use like this reduction_type::UNORDERED > > On Thu, Jul 20, 2023 at 3:59=E2=80=AFPM juzhe.zhong@rivai.ai > wrote: > > > > I have no ideal, just ICE comes when running regression: > > > > during RTL pass: expand > > auto.c: In function 'test_int32_t_float_unordered_var': > > auto.c:24:3: internal compiler error: in expand_vec_cmp_float, at confi= g/riscv/riscv-v.cc:2564 > > 24 | test_##TYPE1##_##TYPE2##_##CMP##_var (TYPE1 *restrict dest, = \ > > | ^~~~~ > > auto.c:41:3: note: in expansion of macro 'TEST_LOOP' > > 41 | TEST_LOOP (int32_t, float, CMP) \ > > | ^~~~~~~~~ > > auto.c:55:1: note: in expansion of macro 'TEST_CMP' > > 55 | TEST_CMP (unordered) > > | ^~~~~~~~ > > 0x1c8af0d riscv_vector::expand_vec_cmp_float(rtx_def*, rtx_code, rtx_de= f*, rtx_def*, bool) > > ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:2564 > > 0x233d200 gen_vec_cmprvvm1sfrvvmf32bi(rtx_def*, rtx_def*, rtx_def*, rtx= _def*) > > ../../../riscv-gcc/gcc/config/riscv/autovec.md:559 > > 0x14c4582 rtx_insn* insn_gen_fn::operator()(rtx_def*, rtx_def*, rtx_def*, rtx_def*) const > > ../../../riscv-gcc/gcc/recog.h:407 > > 0x14c3c02 maybe_gen_insn(insn_code, unsigned int, expand_operand*) > > ../../../riscv-gcc/gcc/optabs.cc:8197 > > 0x14c4097 maybe_expand_insn(insn_code, unsigned int, expand_operand*) > > ../../../riscv-gcc/gcc/optabs.cc:8237 > > 0x14c412b expand_insn(insn_code, unsigned int, expand_operand*) > > ../../../riscv-gcc/gcc/optabs.cc:8268 > > 0x14bfc3e expand_vec_cmp_expr(tree_node*, tree_node*, rtx_def*) > > ../../../riscv-gcc/gcc/optabs.cc:6692 > > 0x1124e4a do_store_flag > > ../../../riscv-gcc/gcc/expr.cc:13060 > > 0x1116b10 expand_expr_real_2(separate_ops*, rtx_def*, machine_mode, exp= and_modifier) > > ../../../riscv-gcc/gcc/expr.cc:10265 > > 0x1119405 expand_expr_real_1(tree_node*, rtx_def*, machine_mode, expand= _modifier, rtx_def**, bool) > > ../../../riscv-gcc/gcc/expr.cc:10810 > > 0x1110fb0 expand_expr_real(tree_node*, rtx_def*, machine_mode, expand_m= odifier, rtx_def**, bool) > > ../../../riscv-gcc/gcc/expr.cc:9015 > > 0xf2e973 expand_normal(tree_node*) > > ../../../riscv-gcc/gcc/expr.h:316 > > 0x12bb060 expand_vec_cond_mask_optab_fn > > ../../../riscv-gcc/gcc/internal-fn.cc:3059 > > 0x12c27ca expand_VCOND_MASK > > ../../../riscv-gcc/gcc/internal-fn.def:184 > > 0x12c52a5 expand_internal_call(internal_fn, gcall*) > > ../../../riscv-gcc/gcc/internal-fn.cc:4792 > > 0x12c52d0 expand_internal_call(gcall*) > > ../../../riscv-gcc/gcc/internal-fn.cc:4800 > > 0xf5e4c1 expand_call_stmt > > ../../../riscv-gcc/gcc/cfgexpand.cc:2737 > > 0xf62871 expand_gimple_stmt_1 > > ../../../riscv-gcc/gcc/cfgexpand.cc:3880 > > 0xf62f0f expand_gimple_stmt > > ../../../riscv-gcc/gcc/cfgexpand.cc:4044 > > 0xf6b8a9 expand_gimple_basic_block > > ../../../riscv-gcc/gcc/cfgexpand.cc:6096 > > > > This ICE happens when compiling vcond.cc tests > > ________________________________ > > juzhe.zhong@rivai.ai > > > > > > From: Robin Dapp > > Date: 2023-07-20 15:57 > > To: juzhe.zhong@rivai.ai; gcc-patches > > CC: rdapp.gcc; kito.cheng; Kito.cheng; jeffreyalaw > > Subject: Re: [PATCH] RISC-V: Support in-order floating-point reduction > > > The UNORDERED enum will cause ICE since we have UNORDERED in rtx_code= . > > > > > > Could you give me another enum name? > > > > I would have expected it to work when it's namespaced. > > > > Regards > > Robin > > > > >