From: Kito Cheng <kito.cheng@sifive.com>
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com,
jeffreyalaw@gmail.com, rdapp.gcc@gmail.com
Subject: Re: [PATCH V3] RISC-V: Enable basic VLS modes support
Date: Thu, 27 Jul 2023 17:19:40 +0800 [thread overview]
Message-ID: <CALLt3TjG+Lm5nfP331-LvJKdmm3ee4uoMb0h6jjPJ4xsOtQgSA@mail.gmail.com> (raw)
In-Reply-To: <20230727090640.65258-1-juzhe.zhong@rivai.ai>
Last minor thing :)
> +(define_insn_and_split "*mov<mode>"
> + [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> + (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
> + "TARGET_VECTOR"
Reject (set (mem) (mem)) by adding the check:
TARGET_VECTOR
&& (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
|| register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
next prev parent reply other threads:[~2023-07-27 9:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-27 9:06 Juzhe-Zhong
2023-07-27 9:19 ` Kito Cheng [this message]
2023-07-27 9:50 ` juzhe.zhong
2023-07-27 9:57 ` Kito Cheng
2023-07-27 10:04 ` juzhe.zhong
2023-07-27 10:35 ` juzhe.zhong
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