* [PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.
@ 2023-10-12 18:40 Kito Cheng
2023-10-12 22:36 ` 钟居哲
0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2023-10-12 18:40 UTC (permalink / raw)
To: gcc-patches, kito.cheng, palmer, jeffreyalaw, rdapp, juzhe.zhong
Cc: Kito Cheng
riscv_legitimize_poly_move was expected to ensure the poly value is at most 32
times smaller than the minimal VLEN (32 being derived from '4096 / 128').
This assumption held when our mode modeling was not so precisely defined.
However, now that we have modeled the mode size according to the correct minimal
VLEN info, the size difference between different RVV modes can be up to 64
times. For instance, comparing RVVMF64BI and RVVMF1BI, the sizes are [1, 1]
versus [64, 64] respectively.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_poly_move): Bump
max_power to 64.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/autovec/bug-01.C: New.
* g++.target/riscv/rvv/rvv.exp: Add autovec folder.
---
gcc/config/riscv/riscv.cc | 5 ++-
gcc/config/riscv/riscv.h | 5 +++
.../g++.target/riscv/rvv/autovec/bug-01.C | 33 +++++++++++++++++++
gcc/testsuite/g++.target/riscv/rvv/rvv.exp | 3 ++
4 files changed, 43 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 739fc77e785..d43bc765ce7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2411,9 +2411,8 @@ riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src)
}
else
{
- /* FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096. */
- int max_power = exact_log2 (4096 / 128);
- for (int i = 0; i < max_power; i++)
+ int max_power = exact_log2 (MAX_POLY_VARIANT);
+ for (int i = 0; i <= max_power; i++)
{
int possible_div_factor = 1 << i;
if (factor % (vlenb / possible_div_factor) == 0)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4b8d57509fb..3d2723f5339 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1197,4 +1197,9 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
+
+/* The size difference between different RVV modes can be up to 64 times.
+ e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64]. */
+#define MAX_POLY_VARIANT 64
+
#endif /* ! GCC_RISCV_H */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
new file mode 100644
index 00000000000..fd10009ddbe
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
@@ -0,0 +1,33 @@
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3" } */
+
+class c {
+public:
+ int e();
+ void j();
+};
+float *d;
+class k {
+ int f;
+
+public:
+ k(int m) : f(m) {}
+ float g;
+ float h;
+ void n(int m) {
+ for (int i; i < m; i++) {
+ d[0] = d[1] = d[2] = g;
+ d[3] = h;
+ d += f;
+ }
+ }
+};
+c l;
+void o() {
+ int b = l.e();
+ k a(b);
+ for (;;)
+ if (b == 4) {
+ l.j();
+ a.n(2);
+ }
+}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
index 249530580d7..c30d6e93144 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
@@ -40,5 +40,8 @@ set CFLAGS "-march=$gcc_march -O3"
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.C]] \
"" $CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[C\]]] \
+ "" $CFLAGS
+
# All done.
dg-finish
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.
2023-10-12 18:40 [PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512 Kito Cheng
@ 2023-10-12 22:36 ` 钟居哲
2023-10-13 3:55 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: 钟居哲 @ 2023-10-12 22:36 UTC (permalink / raw)
To: kito.cheng, gcc-patches, kito.cheng, palmer, Jeff Law, rdapp; +Cc: kito.cheng
[-- Attachment #1: Type: text/plain, Size: 3902 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: Kito Cheng
Date: 2023-10-13 02:40
To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong
CC: Kito Cheng
Subject: [PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.
riscv_legitimize_poly_move was expected to ensure the poly value is at most 32
times smaller than the minimal VLEN (32 being derived from '4096 / 128').
This assumption held when our mode modeling was not so precisely defined.
However, now that we have modeled the mode size according to the correct minimal
VLEN info, the size difference between different RVV modes can be up to 64
times. For instance, comparing RVVMF64BI and RVVMF1BI, the sizes are [1, 1]
versus [64, 64] respectively.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_poly_move): Bump
max_power to 64.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/autovec/bug-01.C: New.
* g++.target/riscv/rvv/rvv.exp: Add autovec folder.
---
gcc/config/riscv/riscv.cc | 5 ++-
gcc/config/riscv/riscv.h | 5 +++
.../g++.target/riscv/rvv/autovec/bug-01.C | 33 +++++++++++++++++++
gcc/testsuite/g++.target/riscv/rvv/rvv.exp | 3 ++
4 files changed, 43 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 739fc77e785..d43bc765ce7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2411,9 +2411,8 @@ riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src)
}
else
{
- /* FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096. */
- int max_power = exact_log2 (4096 / 128);
- for (int i = 0; i < max_power; i++)
+ int max_power = exact_log2 (MAX_POLY_VARIANT);
+ for (int i = 0; i <= max_power; i++)
{
int possible_div_factor = 1 << i;
if (factor % (vlenb / possible_div_factor) == 0)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4b8d57509fb..3d2723f5339 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1197,4 +1197,9 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
+
+/* The size difference between different RVV modes can be up to 64 times.
+ e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64]. */
+#define MAX_POLY_VARIANT 64
+
#endif /* ! GCC_RISCV_H */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
new file mode 100644
index 00000000000..fd10009ddbe
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
@@ -0,0 +1,33 @@
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3" } */
+
+class c {
+public:
+ int e();
+ void j();
+};
+float *d;
+class k {
+ int f;
+
+public:
+ k(int m) : f(m) {}
+ float g;
+ float h;
+ void n(int m) {
+ for (int i; i < m; i++) {
+ d[0] = d[1] = d[2] = g;
+ d[3] = h;
+ d += f;
+ }
+ }
+};
+c l;
+void o() {
+ int b = l.e();
+ k a(b);
+ for (;;)
+ if (b == 4) {
+ l.j();
+ a.n(2);
+ }
+}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
index 249530580d7..c30d6e93144 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
@@ -40,5 +40,8 @@ set CFLAGS "-march=$gcc_march -O3"
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.C]] \
"" $CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[C\]]] \
+ "" $CFLAGS
+
# All done.
dg-finish
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.
2023-10-12 22:36 ` 钟居哲
@ 2023-10-13 3:55 ` Kito Cheng
0 siblings, 0 replies; 3+ messages in thread
From: Kito Cheng @ 2023-10-13 3:55 UTC (permalink / raw)
To: 钟居哲; +Cc: gcc-patches, kito.cheng, palmer, Jeff Law, rdapp
Committed with few changelog tweak :P
On Thu, Oct 12, 2023 at 3:37 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
>
> LGTM
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-10-13 02:40
> To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong
> CC: Kito Cheng
> Subject: [PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.
> riscv_legitimize_poly_move was expected to ensure the poly value is at most 32
> times smaller than the minimal VLEN (32 being derived from '4096 / 128').
> This assumption held when our mode modeling was not so precisely defined.
> However, now that we have modeled the mode size according to the correct minimal
> VLEN info, the size difference between different RVV modes can be up to 64
> times. For instance, comparing RVVMF64BI and RVVMF1BI, the sizes are [1, 1]
> versus [64, 64] respectively.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_poly_move): Bump
> max_power to 64.
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/autovec/bug-01.C: New.
> * g++.target/riscv/rvv/rvv.exp: Add autovec folder.
> ---
> gcc/config/riscv/riscv.cc | 5 ++-
> gcc/config/riscv/riscv.h | 5 +++
> .../g++.target/riscv/rvv/autovec/bug-01.C | 33 +++++++++++++++++++
> gcc/testsuite/g++.target/riscv/rvv/rvv.exp | 3 ++
> 4 files changed, 43 insertions(+), 3 deletions(-)
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 739fc77e785..d43bc765ce7 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2411,9 +2411,8 @@ riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src)
> }
> else
> {
> - /* FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096. */
> - int max_power = exact_log2 (4096 / 128);
> - for (int i = 0; i < max_power; i++)
> + int max_power = exact_log2 (MAX_POLY_VARIANT);
> + for (int i = 0; i <= max_power; i++)
> {
> int possible_div_factor = 1 << i;
> if (factor % (vlenb / possible_div_factor) == 0)
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 4b8d57509fb..3d2723f5339 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -1197,4 +1197,9 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
> #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
> #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
> +
> +/* The size difference between different RVV modes can be up to 64 times.
> + e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64]. */
> +#define MAX_POLY_VARIANT 64
> +
> #endif /* ! GCC_RISCV_H */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
> new file mode 100644
> index 00000000000..fd10009ddbe
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
> @@ -0,0 +1,33 @@
> +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3" } */
> +
> +class c {
> +public:
> + int e();
> + void j();
> +};
> +float *d;
> +class k {
> + int f;
> +
> +public:
> + k(int m) : f(m) {}
> + float g;
> + float h;
> + void n(int m) {
> + for (int i; i < m; i++) {
> + d[0] = d[1] = d[2] = g;
> + d[3] = h;
> + d += f;
> + }
> + }
> +};
> +c l;
> +void o() {
> + int b = l.e();
> + k a(b);
> + for (;;)
> + if (b == 4) {
> + l.j();
> + a.n(2);
> + }
> +}
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
> index 249530580d7..c30d6e93144 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
> +++ b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
> @@ -40,5 +40,8 @@ set CFLAGS "-march=$gcc_march -O3"
> dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.C]] \
> "" $CFLAGS
> +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[C\]]] \
> + "" $CFLAGS
> +
> # All done.
> dg-finish
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-10-12 18:40 [PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512 Kito Cheng
2023-10-12 22:36 ` 钟居哲
2023-10-13 3:55 ` Kito Cheng
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