From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by sourceware.org (Postfix) with ESMTPS id 8CA8F3858284 for ; Mon, 29 May 2023 13:30:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8CA8F3858284 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-256797b5664so699547a91.2 for ; Mon, 29 May 2023 06:30:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685367018; x=1687959018; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=ltAs0FhVw7aVIaSDH2DFx9429sVJuFXXZkhUUOIftao=; b=m0VaRUtCZRGEks1K3BoBwxO1ACQ9dX7T6q3gD+DSfsth6QacneEUyCMg/jOiDx3RCL UtS+cXvTeprvrU78AevvG+K/k8EgFESQe+OEcrjW5avCu3NiR788veWnnGC4FUJlPuq7 ldtUUBXRbOZLndBIIHQyQJ9yMA4QTNBYrQaEBNlX7L478B/JvYL0V9wtIuD9CW5B94Lr 5lJ7qKTAOzM/xHVLXXKYIvMF7plRUVOZ2tDhPeVrToiG/r3R7emZ1Ham6ATqkGdMmi4C N5oagw3zWhT5+Y5dy6dsyg240PAym7j2TgRdKSExEe2kNuLcQRLC36hk5/1gBdgxvyyo VmyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685367018; x=1687959018; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ltAs0FhVw7aVIaSDH2DFx9429sVJuFXXZkhUUOIftao=; b=jO/KWYVIcXuy98IfHBekQiGmAdCM4/VTh1b/shIz8PKQtlLxP9Yv4/Bbt3qoJzPRnN /yPjsE0FAt/XNeYOheLyvu2dE1PmdLhPiU2OCEkBXhjq7bhG5q+tdS9gLtKleZBkEiWf pGb+mVNupUKDxCG/MpzRzjMkHeV/Ss3gyTedcA9C+RYtX9HDggEzNbXkASlip5czhz5D rZWevn33sCPCu9h3FUYJEwb73lIJ0FxN0RTfN+6Kv9Cz8xV+O7qp2q435FiaEAEQqMS9 vKA9RszmLm/hr65T563nFgFennwRR8BKBOZB5G7gY3j6lgFiokEhUgQbzRwQT41O62um 6k2A== X-Gm-Message-State: AC+VfDyEkgRw1KU7sLBsYgrRDrMXDXvHzW6fcOPQ0sHunxYVjuHyi3NM mZ4srBXW3tBh/LmxxuBR656aNoAWagaGffu+3B7HRg== X-Google-Smtp-Source: ACHHUZ5l4GIXMb0UbtQTPpDa48IfxvIDF7AwJOfebFKBs9mXGpGFMT7lluqg1xug/qCQAQPZ8tO/9BDuFSX8dCpSHLQ= X-Received: by 2002:a17:902:b684:b0:1ae:305f:e949 with SMTP id c4-20020a170902b68400b001ae305fe949mr10032053pls.6.1685367018451; Mon, 29 May 2023 06:30:18 -0700 (PDT) MIME-Version: 1.0 References: <20230529130336.857998-1-pan2.li@intel.com> In-Reply-To: <20230529130336.857998-1-pan2.li@intel.com> From: Kito Cheng Date: Mon, 29 May 2023 21:30:07 +0800 Message-ID: Subject: Re: [PATCH v1] RISC-V: Refactor comments and naming of riscv-v.cc. To: pan2.li@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, yanzhang.wang@intel.com, rdapp.gcc@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM On Mon, May 29, 2023 at 9:03=E2=80=AFPM wrote: > > From: Pan Li > > This patch would like to remove unnecessary comments of some self > explained parameters and try a better name to avoid misleading. > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > * config/riscv/riscv-v.cc (emit_vlmax_insn): Remove unnecessary > comments and rename local variables. > (emit_nonvlmax_insn): Diito. > (emit_vlmax_merge_insn): Ditto. > (emit_vlmax_cmp_insn): Ditto. > (emit_vlmax_cmp_mu_insn): Ditto. > (emit_scalar_move_insn): Ditto. > > Signed-off-by: Pan Li > --- > gcc/config/riscv/riscv-v.cc | 96 +++++++++++++++++++------------------ > 1 file changed, 49 insertions(+), 47 deletions(-) > > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index 20b589bf51b..6ec24dba98d 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -349,16 +349,16 @@ autovec_use_vlmax_p (void) > void > emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl) > { > - machine_mode data_mode =3D GET_MODE (ops[0]); > - machine_mode mask_mode =3D get_mask_mode (data_mode).require (); > - insn_expander e (/*OP_NUM*/ op_num, > - /*HAS_DEST_P*/ true, > - /*FULLY_UNMASKED_P*/ true, > - /*USE_REAL_MERGE_P*/ false, > - /*HAS_AVL_P*/ true, > - /*VLMAX_P*/ true, > - /*DEST_MODE*/ data_mode, > - /*MASK_MODE*/ mask_mode); > + machine_mode dest_mode =3D GET_MODE (ops[0]); > + machine_mode mask_mode =3D get_mask_mode (dest_mode).require (); > + insn_expander e (op_num, > + /* HAS_DEST_P */ true, > + /* FULLY_UNMASKED_P */ true, > + /* USE_REAL_MERGE_P */ false, > + /* HAS_AVL_P */ true, > + /* VLMAX_P */ true, > + dest_mode, > + mask_mode); > > e.set_policy (TAIL_ANY); > e.set_policy (MASK_ANY); > @@ -373,16 +373,16 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx *o= ps, rtx vl) > void > emit_nonvlmax_insn (unsigned icode, int op_num, rtx *ops, rtx avl) > { > - machine_mode data_mode =3D GET_MODE (ops[0]); > - machine_mode mask_mode =3D get_mask_mode (data_mode).require (); > - insn_expander e (/*OP_NUM*/ op_num, > - /*HAS_DEST_P*/ true, > - /*FULLY_UNMASKED_P*/ true, > - /*USE_REAL_MERGE_P*/ false, > - /*HAS_AVL_P*/ true, > - /*VLMAX_P*/ false, > - /*DEST_MODE*/ data_mode, > - /*MASK_MODE*/ mask_mode); > + machine_mode dest_mode =3D GET_MODE (ops[0]); > + machine_mode mask_mode =3D get_mask_mode (dest_mode).require (); > + insn_expander e (op_num, > + /* HAS_DEST_P */ true, > + /* FULLY_UNMASKED_P */ true, > + /* USE_REAL_MERGE_P */ false, > + /* HAS_AVL_P */ true, > + /* VLMAX_P */ false, > + dest_mode, > + mask_mode); > > e.set_policy (TAIL_ANY); > e.set_policy (MASK_ANY); > @@ -396,14 +396,14 @@ emit_vlmax_merge_insn (unsigned icode, int op_num, = rtx *ops) > { > machine_mode dest_mode =3D GET_MODE (ops[0]); > machine_mode mask_mode =3D get_mask_mode (dest_mode).require (); > - insn_expander e (/*OP_NUM*/ op_num, > - /*HAS_DEST_P*/ true, > - /*FULLY_UNMASKED_P*/ false, > - /*USE_REAL_MERGE_P*/ false, > - /*HAS_AVL_P*/ true, > - /*VLMAX_P*/ true, > - /*DEST_MODE*/ dest_mode, > - /*MASK_MODE*/ mask_mode); > + insn_expander e (op_num, > + /* HAS_DEST_P */ true, > + /* FULLY_UNMASKED_P */ false, > + /* USE_REAL_MERGE_P */ false, > + /* HAS_AVL_P */ true, > + /* VLMAX_P */ true, > + dest_mode, > + mask_mode); > > e.set_policy (TAIL_ANY); > e.emit_insn ((enum insn_code) icode, ops); > @@ -414,14 +414,14 @@ void > emit_vlmax_cmp_insn (unsigned icode, rtx *ops) > { > machine_mode mode =3D GET_MODE (ops[0]); > - insn_expander e (/*OP_NUM*/ RVV_CMP_OP, > - /*HAS_DEST_P*/ true, > - /*FULLY_UNMASKED_P*/ true, > - /*USE_REAL_MERGE_P*/ false, > - /*HAS_AVL_P*/ true, > - /*VLMAX_P*/ true, > - /*DEST_MODE*/ mode, > - /*MASK_MODE*/ mode); > + insn_expander e (RVV_CMP_OP, > + /* HAS_DEST_P */ true, > + /* FULLY_UNMASKED_P */ true, > + /* USE_REAL_MERGE_P */ false, > + /* HAS_AVL_P */ true, > + /* VLMAX_P */ true, > + mode, > + mode); > > e.set_policy (MASK_ANY); > e.emit_insn ((enum insn_code) icode, ops); > @@ -432,14 +432,14 @@ void > emit_vlmax_cmp_mu_insn (unsigned icode, rtx *ops) > { > machine_mode mode =3D GET_MODE (ops[0]); > - insn_expander e (/*OP_NUM*/ RVV_CMP_MU_OP, > - /*HAS_DEST_P*/ true, > - /*FULLY_UNMASKED_P*/ false, > - /*USE_REAL_MERGE_P*/ true, > - /*HAS_AVL_P*/ true, > - /*VLMAX_P*/ true, > - /*DEST_MODE*/ mode, > - /*MASK_MODE*/ mode); > + insn_expander e (RVV_CMP_MU_OP, > + /* HAS_DEST_P */ true, > + /* FULLY_UNMASKED_P */ false, > + /* USE_REAL_MERGE_P */ true, > + /* HAS_AVL_P */ true, > + /* VLMAX_P */ true, > + mode, > + mode); > > e.set_policy (MASK_UNDISTURBED); > e.emit_insn ((enum insn_code) icode, ops); > @@ -1450,15 +1450,17 @@ expand_vector_init_insert_elems (rtx target, cons= t rvv_builder &builder, > static void > emit_scalar_move_insn (unsigned icode, rtx *ops) > { > - machine_mode data_mode =3D GET_MODE (ops[0]); > - machine_mode mask_mode =3D get_mask_mode (data_mode).require (); > + machine_mode dest_mode =3D GET_MODE (ops[0]); > + machine_mode mask_mode =3D get_mask_mode (dest_mode).require (); > insn_expander e (riscv_vector::RVV_SCALAR_MOV_O= P, > /* HAS_DEST_P */ true, > /* FULLY_UNMASKED_P */ false, > /* USE_REAL_MERGE_P */ true, > /* HAS_AVL_P */ true, > /* VLMAX_P */ false, > - data_mode, mask_mode); > + dest_mode, > + mask_mode); > + > e.set_policy (TAIL_ANY); > e.set_policy (MASK_ANY); > e.set_vl (CONST1_RTX (Pmode)); > -- > 2.34.1 >