From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by sourceware.org (Postfix) with ESMTPS id D61373858C2B for ; Thu, 20 Jul 2023 08:04:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D61373858C2B Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-262e3c597b9so302327a91.0 for ; Thu, 20 Jul 2023 01:04:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1689840240; x=1690445040; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=ar4mZ91YouhtHrDFI8tdTX8+4+LYtV5PJ/GEfnUDohs=; b=nGYvZ0IGEua1Zhs7ZBFpvbL3yT7axKVY4xBjC9f+JshIrNj/hookO3dhFRt5KD+3gy WIgIAmbFSSbZqRLR7HQSMS2gYeKspgb4MHBVxxGi35dtVLksgRePWefcZzaKEugFcVdO PCUaoFDB924nhhDdmnQ1myz4IPYxYPnly0WBBj0YZdH0EDRSeRL8LgEJbfdBhhUq0P+j sFhbKuq7rIUQi5kY6VA9rVOSvCnFQmY+EXOvXyV5tuaGUj5ZkoaRHB9/TkJDDVjsw9J4 DTXwfECT8Yunzr/YzoSTHEai17lQH/XqiB+i3zRpgGWHufC/p/T+wJoCaFpDN1UrkK+y yuag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689840240; x=1690445040; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ar4mZ91YouhtHrDFI8tdTX8+4+LYtV5PJ/GEfnUDohs=; b=jLs0Fwruqza4+KPsBcemftB7fsek1JfKKYIUPHntsR8jLJqPC6EKquFy5cB3s1jCq3 Ns9Gm69/xgu0gtMuYx0V5+jIlnkh73oK1hqdMBerhDZqZ2Hle7ya4pYTL1YUi3mBYFiI TAijBvJc1U9smrTsh3vNeeR20YJw7tF879Y5VS7ByKll1PGO1BTP7W9kQUUYClEdM/El kmccVhKY9l43+rk8ngJk9L6hXTcbUb5CiRTacFC504zK8gDzpHpQAs50FjFJFJHEcePq l/96iVEmng7F1eZ7RCy5TuTPXbi+01ROVHQ+v2P8miiUnQf40a2KiuIjek8Y1k/bIbez H68A== X-Gm-Message-State: ABy/qLby1iKGxfIeaAhllsFA/PVnwjhaoqU9WzCdyWYlB3ALG9zMJpAj 72r04SIClEjH9MWEkcJV0VBBDHAYOZylxGACJQG7Mw== X-Google-Smtp-Source: APBJJlEK4Tr1uGpSNIujRO+/ABKpcE4Npyb6g2wx+1q87LwnoMO1OFMItkoYfWNwwTfYS7I+6E6IvQb1+2CyuCsP674= X-Received: by 2002:a17:90a:9302:b0:263:fc27:662c with SMTP id p2-20020a17090a930200b00263fc27662cmr1322416pjo.39.1689840239994; Thu, 20 Jul 2023 01:03:59 -0700 (PDT) MIME-Version: 1.0 References: <20230720073406.239379-1-juzhe.zhong@rivai.ai> <3684FC24D86A4D06+202307201542514213108@rivai.ai> <48fab29b-bfbe-e743-f279-94c23293c983@gmail.com> In-Reply-To: From: Kito Cheng Date: Thu, 20 Jul 2023 16:03:48 +0800 Message-ID: Subject: Re: Re: [PATCH] RISC-V: Support in-order floating-point reduction To: "juzhe.zhong@rivai.ai" Cc: Robin Dapp , gcc-patches , "kito.cheng" , jeffreyalaw Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Seems like because you ` using namespace riscv_vector;` so the UNORDERED in expand_vec_cmp_float used reduction_type::UNORDERED Hmmm, maybe enum class? enum class reduction_type { UNORDERED, FOLD_LEFT, MASK_LEN_FOLD_LEFT, }; and need use like this reduction_type::UNORDERED On Thu, Jul 20, 2023 at 3:59=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > I have no ideal, just ICE comes when running regression: > > during RTL pass: expand > auto.c: In function 'test_int32_t_float_unordered_var': > auto.c:24:3: internal compiler error: in expand_vec_cmp_float, at config/= riscv/riscv-v.cc:2564 > 24 | test_##TYPE1##_##TYPE2##_##CMP##_var (TYPE1 *restrict dest, \ > | ^~~~~ > auto.c:41:3: note: in expansion of macro 'TEST_LOOP' > 41 | TEST_LOOP (int32_t, float, CMP) \ > | ^~~~~~~~~ > auto.c:55:1: note: in expansion of macro 'TEST_CMP' > 55 | TEST_CMP (unordered) > | ^~~~~~~~ > 0x1c8af0d riscv_vector::expand_vec_cmp_float(rtx_def*, rtx_code, rtx_def*= , rtx_def*, bool) > ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:2564 > 0x233d200 gen_vec_cmprvvm1sfrvvmf32bi(rtx_def*, rtx_def*, rtx_def*, rtx_d= ef*) > ../../../riscv-gcc/gcc/config/riscv/autovec.md:559 > 0x14c4582 rtx_insn* insn_gen_fn::operator()(rtx_def*, rtx_def*, rtx_def*, rtx_def*) const > ../../../riscv-gcc/gcc/recog.h:407 > 0x14c3c02 maybe_gen_insn(insn_code, unsigned int, expand_operand*) > ../../../riscv-gcc/gcc/optabs.cc:8197 > 0x14c4097 maybe_expand_insn(insn_code, unsigned int, expand_operand*) > ../../../riscv-gcc/gcc/optabs.cc:8237 > 0x14c412b expand_insn(insn_code, unsigned int, expand_operand*) > ../../../riscv-gcc/gcc/optabs.cc:8268 > 0x14bfc3e expand_vec_cmp_expr(tree_node*, tree_node*, rtx_def*) > ../../../riscv-gcc/gcc/optabs.cc:6692 > 0x1124e4a do_store_flag > ../../../riscv-gcc/gcc/expr.cc:13060 > 0x1116b10 expand_expr_real_2(separate_ops*, rtx_def*, machine_mode, expan= d_modifier) > ../../../riscv-gcc/gcc/expr.cc:10265 > 0x1119405 expand_expr_real_1(tree_node*, rtx_def*, machine_mode, expand_m= odifier, rtx_def**, bool) > ../../../riscv-gcc/gcc/expr.cc:10810 > 0x1110fb0 expand_expr_real(tree_node*, rtx_def*, machine_mode, expand_mod= ifier, rtx_def**, bool) > ../../../riscv-gcc/gcc/expr.cc:9015 > 0xf2e973 expand_normal(tree_node*) > ../../../riscv-gcc/gcc/expr.h:316 > 0x12bb060 expand_vec_cond_mask_optab_fn > ../../../riscv-gcc/gcc/internal-fn.cc:3059 > 0x12c27ca expand_VCOND_MASK > ../../../riscv-gcc/gcc/internal-fn.def:184 > 0x12c52a5 expand_internal_call(internal_fn, gcall*) > ../../../riscv-gcc/gcc/internal-fn.cc:4792 > 0x12c52d0 expand_internal_call(gcall*) > ../../../riscv-gcc/gcc/internal-fn.cc:4800 > 0xf5e4c1 expand_call_stmt > ../../../riscv-gcc/gcc/cfgexpand.cc:2737 > 0xf62871 expand_gimple_stmt_1 > ../../../riscv-gcc/gcc/cfgexpand.cc:3880 > 0xf62f0f expand_gimple_stmt > ../../../riscv-gcc/gcc/cfgexpand.cc:4044 > 0xf6b8a9 expand_gimple_basic_block > ../../../riscv-gcc/gcc/cfgexpand.cc:6096 > > This ICE happens when compiling vcond.cc tests > ________________________________ > juzhe.zhong@rivai.ai > > > From: Robin Dapp > Date: 2023-07-20 15:57 > To: juzhe.zhong@rivai.ai; gcc-patches > CC: rdapp.gcc; kito.cheng; Kito.cheng; jeffreyalaw > Subject: Re: [PATCH] RISC-V: Support in-order floating-point reduction > > The UNORDERED enum will cause ICE since we have UNORDERED in rtx_code. > > > > Could you give me another enum name? > > I would have expected it to work when it's namespaced. > > Regards > Robin > >