From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by sourceware.org (Postfix) with ESMTPS id EE8FB3858C33 for ; Wed, 19 Jul 2023 14:29:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EE8FB3858C33 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1b9ecf0cb4cso43447245ad.2 for ; Wed, 19 Jul 2023 07:29:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1689776951; x=1690381751; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=CORF55FpJ9nEDOi2fbVbZ/46Ged5a+aTvOF/4MKY0Os=; b=WZfO3EFhtNXWtqM3Er79sMbnd0fus7NZJ3O1nogiENTM9HQ8e+SQ99zgkLkjRmnyqp P3XUBFfz3LhDK38CBd1uHVyv8e0DvzUgNWY08GDyasYVBqpNvgYammpz3LSnufRVh/ES eWnrXf5fgZsR/vJE/fvEU0oT1wxYgitmLmk6AMZ7CB/mOWETpnLyzSljvHEQWbxIic9R R8dMpJIslsfajO5p27bhAseBdF9HEFuSAwMrLrLvssyQL4uGczoNb8Jrn1nAq10ZsEAt i7Me4x5Qtb/msg64Y/1K5KWBvEba4aMC0KgaDWV3xsT0Wp746gGQOv39HIQlODGe8Tdo BpRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689776951; x=1690381751; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=CORF55FpJ9nEDOi2fbVbZ/46Ged5a+aTvOF/4MKY0Os=; b=OxU+XSVxBCh7tIo2HnbXr152tVSz7wpSLTfQ1ZxbZBzr2/9fFLVCkZ7MdTdS6GBzMD Xwblvp0+qbwD2WUuE56mibYuY9N76eOFOd8cYnjrGpx6eMmSVeSVT335NrSfRhhnCiQ0 Goa1qklEgGlTTaWMmgn8O73XHVMOUFYJQR30zEWgQx4X2nI7Ikck3XSt/YjY3JDeBZ8M HjJcBFxOcLTl/ff+Kn2cChvOt7HMHkzb2NKYQgxFasATPLvHtsO8TNSbdz3xuGUlC/5r LIPsovdlABznFfjNuKTvm74KuvYfXryl1Y9muEMkwG8H3StV8M8xe97QgEi/m4CHEuk3 pYjQ== X-Gm-Message-State: ABy/qLZcen9eJZHXhLT2mMLYq0m17c38vmPGH4U6gk/TXoZIxQwh4sHz 99lNCOZlNWcNqwnCtOiR5NuOJzw72e063PqXCqRxWA== X-Google-Smtp-Source: APBJJlFypT/dFssar8BfYaA1MFTrA3uVfFvMO/yYeoaBb0X4s8oYRRQy2oBeRm6M5Bx25wYnDw2NHhNcC9tqvKo7TSk= X-Received: by 2002:a17:90b:3505:b0:262:d19c:4fee with SMTP id ls5-20020a17090b350500b00262d19c4feemr1930198pjb.19.1689776950728; Wed, 19 Jul 2023 07:29:10 -0700 (PDT) MIME-Version: 1.0 References: <20230719115505.100294-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230719115505.100294-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Wed, 19 Jul 2023 22:28:59 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Refactor RVV machine modes To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Thansk, that's really awesome! One comment about mode iterator is the naming seems like still prefixed with VNX which inconsistent with new mode naming scheme. > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index cd5b19457f8..03e19259505 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -121,45 +121,30 @@ > DONE; > }) > > -(define_expand "len_mask_gather_load" > - [(match_operand:VNX16_QHSD 0 "register_operand") > +(define_expand "len_mask_gather_load" Why DI is gone? and I saw many other pattern has similar issue? > + [(match_operand:VNX16_QHS 0 "register_operand") > (match_operand 1 "pmode_reg_or_0_operand") > - (match_operand:VNX16_QHSDI 2 "register_operand") > - (match_operand 3 "") > - (match_operand 4 "") > + (match_operand:VNX16_QHSI 2 "register_operand") > + (match_operand 3 "") > + (match_operand 4 "") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, true); > DONE; > }) > > -(define_expand "len_mask_gather_load" > - [(match_operand:VNX32_QHS 0 "register_operand") > +(define_expand "len_mask_gather_load" Like this, SI is gone? > @@ -2172,7 +2145,7 @@ preferred_simd_mode (scalar_mode mode) > riscv_autovec_lmul < RVV_M2. Since GCC loop vectorizer report ICE when we > enable -march=rv64gc_zve32* and -march=rv32gc_zve64*. in the > 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have > - VNx1SImode in -march=*zve32* and VNx1DImode in -march=*zve64*, they are > + RVVM1SImode in -march=*zve32* and RVVM1DImode in -march=*zve64*, they are This comment might need to review. > enabled in targetm. vector_mode_supported_p and SLP vectorizer will try to > use them. Currently, we can support auto-vectorization in > -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or > @@ -2371,7 +2344,7 @@ autovectorize_vector_modes (vector_modes *modes, bool) > poly_uint64 full_size > = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul); > > - /* Start with a VNxYYQImode where YY is the number of units that > + /* Start with a RVVM1QImode where YY is the number of units that > fit a whole vector. > Then try YY = nunits / 2, nunits / 4 and nunits / 8 which > is guided by the extensions we have available (vf2, vf4 and vf8). We don't have YY now :P > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index f1f5a73389e..c47bcd2b412 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -972,8 +972,8 @@ riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode, > } > > /* Return true if mode is the RVV enabled mode. > - For example: 'VNx1DI' mode is disabled if MIN_VLEN == 32. > - 'VNx1SI' mode is enabled if MIN_VLEN == 32. */ > + For example: 'RVVM1DI' mode is disabled if MIN_VLEN == 32. > + 'RVVM1SI' mode is enabled if MIN_VLEN == 32. */ This comment need to updated :) > > bool > riscv_v_ext_vector_mode_p (machine_mode mode) > @@ -1023,11 +1023,36 @@ riscv_v_ext_mode_p (machine_mode mode) > poly_int64 > riscv_v_adjust_nunits (machine_mode mode, int scale) > { > + gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL); > if (riscv_v_ext_mode_p (mode)) > - return riscv_vector_chunks * scale; > + { > + if (TARGET_MIN_VLEN == 32) > + scale = scale / 2; > + return riscv_vector_chunks * scale; > + } > return scale; > } > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 19683152259..643e7ea7330 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -1040,6 +1040,7 @@ extern unsigned riscv_stack_boundary; > extern unsigned riscv_bytes_per_vector_chunk; > extern poly_uint16 riscv_vector_chunks; > extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int); > +extern poly_int64 riscv_v_adjust_nunits (machine_mode, bool, int, int); > extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int); > extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int); > /* The number of bits and bytes in a RVV vector. */ > + (cond [(eq_attr "mode" "RVVM8QI,RVVM1BI") (symbol_ref "riscv_vector::get_vlmul(E_RVVM8QImode)") This could be just using constant value rather than ask riscv_vector::get_vlmul now :) > + (eq_attr "mode" "RVVM8QI,RVVM1BI") (symbol_ref "riscv_vector::get_ratio(E_RVVM8QImode)") They are constant now too.