From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by sourceware.org (Postfix) with ESMTPS id 214E3385840B for ; Thu, 11 Apr 2024 07:21:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 214E3385840B Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 214E3385840B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::1031 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712820066; cv=none; b=iXDbNTKR51ziRGUeXU6nTtXqSnPtoGf5R0w1N+AkP2kGdivSZ2/5hZoMgFs/tnyHl5wXjDbKqyNAXx7s+gX16yFzyjZz6bxczDfZQgroh2kMlox/HIIACKSRiUhVTARzRWXnVw0EBv1TF0Vs3I2O9i2FImbAFpTJSvyCL13K+Cw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712820066; c=relaxed/simple; bh=mPv+WB0CN2YQb8qinFqpRQwrma9A8DrCIWtpLjeP3CQ=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=tnKU//SoNMHTaDLEQHiSPcP28xB/Wxwgbrj//Guv+Dz/U4luu0Z+QpyrM2UaMRrpAU4R/ir6+YlyLYK+vE7Qpyatj3ymYNJ/3utyILIaBocX1hSNBqf5Z/nvrrYF1eRsUlwIVdir0nySxy7r1fU+X7gQQ0aHbZy4u2YtJ/064Xw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-2a53a4a283eso2935983a91.0 for ; Thu, 11 Apr 2024 00:21:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1712820060; x=1713424860; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=4QdSkEzFQmHXDOi4ZvVhtRWPiX6q7tk9hckjYfsO1Fo=; b=QgJ/HZL+RP/xgxjEEN3WNXLHBJ5DpNFbMmK9b9eKkr+7cf+gNJRdv1X0Yc6Nb+57iT qV74CH3Yfinw1fQvUZUrE3P2AM2yt+SpCsc8JlbGgFRymeR0CqWmbL2YmlwPxe9tGFcA dj7Gv4nWAEdUDoc6yadv5kaJQDbKa+rXRjgH8jowuToJ5/qZ7eK1rWOiqvkvr2ev98Pa 3tD2VfK2rrsgF0dsfg6WGdEzDM4TSs1EC1OkZwh/P0jjKsdcaENc3quncBXEGoeps2gp ErzbSBHwh7SmKzDWqkTS3GxibNatgpPCMTEMsSYX1sThtlEhaMPJzzLYSqRmDFSkUaDP 3FvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712820060; x=1713424860; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4QdSkEzFQmHXDOi4ZvVhtRWPiX6q7tk9hckjYfsO1Fo=; b=K0prMHQf4dVz+OQ0bj4cBOMTLw5queYzZRemCWA5E4o8wtZZgIQrlx9MKJ8HSiPBFI kFHC00555CLXTYn6jb6Fb/Gb8ezX2IymymhIW7PwsunDjJCcDiWC/TgEAZNjwco8TQMW urV+xZ4SAyvkB1eW3cWTeKk57nMN8+VufC1Twu7uAPN3LtveDNtXdca1fEEVfxlF++ur GuxeQqV+6Rth/cudSQNzkD5AAqdbrpXvWn4j6KWr16nLS6PXj5ewdY8MK+fN/HVLFLCr e2E2d4H7xEPdRbuLB7/yTHd+QiG4IZYhiZVXk2Teq0/JFe8Z+WoMXEnh34mohW1rEBkg zp+Q== X-Gm-Message-State: AOJu0Yw9hDSPtf34uehy+x5MMXyDTN3vWHwqylaunxix9sAHrC0EPOOP j5TSTm2ZD+piHRWHqvx8Awd3+exii/QdwrmBF7yn2L5WOqhKNx2xNFeRVO7PymA3d6Xi/cZnwgI M9ZkVDWY3XsxlfK7zIwWcQgX11uHS99r2BeBufw== X-Google-Smtp-Source: AGHT+IGrttVvpnjDX9M1da+K7Pky/ozPm2kFHeQfuRUARYoiTqIhS/WOrbpMNctrZT9re63RkGsPjeP1hv04UH55is8= X-Received: by 2002:a17:90b:46ce:b0:2a5:2870:6d with SMTP id jx14-20020a17090b46ce00b002a52870006dmr4753691pjb.48.1712820060429; Thu, 11 Apr 2024 00:21:00 -0700 (PDT) MIME-Version: 1.0 References: <20240410075759.994891-1-kito.cheng@sifive.com> In-Reply-To: From: Kito Cheng Date: Thu, 11 Apr 2024 15:20:49 +0800 Message-ID: Subject: Re: [PATCH] wwwdocs: gcc-14: Add RISC-V changes To: Palmer Dabbelt Cc: gcc-patches@gcc.gnu.org, Kito Cheng , "Patrick O'Neill" , jeffreyalaw@gmail.com Content-Type: multipart/alternative; boundary="0000000000004449250615ccff1a" X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TLD_CHINA,TXREP,URIBL_SBL_A autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000004449250615ccff1a Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Committed with fixes, thanks :) On Thu, Apr 11, 2024 at 12:18=E2=80=AFAM Palmer Dabbelt wrote: > On Wed, 10 Apr 2024 00:58:00 PDT (-0700), kito.cheng@sifive.com wrote: > > --- > > htdocs/gcc-14/changes.html | 155 ++++++++++++++++++++++++++++++++++++- > > 1 file changed, 154 insertions(+), 1 deletion(-) > > > > diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html > > index 2d8968cf..6cbb2e8f 100644 > > --- a/htdocs/gcc-14/changes.html > > +++ b/htdocs/gcc-14/changes.html > > @@ -739,7 +739,160 @@ __asm (".global __flmap_lock" "\n\t" > > > > > > > > - > > +

RISC-V

> > +
    > > +
  • The SLP and loop vectorizer is now enabled for RISC-V when the > vector > > I think "are now enabled"? > > > + extension is enabled, thanks to Ju-Zhe Zhong from > > + RiVAI, > > + Pan Li from Intel, and > Robin Dapp > > + from Ventana Micro > for > > + contributing most of the implementation!
    • > > +
  • The -mrvv-max-lmul=3D option has been introduced for > > + performance tuning of the loop vectorizer. The default value is > > + -mrvv-max-lmul=3Dm1, which limits the maximum LMUL = to > 1. > > + The -mrvv-max-lmul=3Ddynamic setting can dynamically > select > > + the maximum LMUL value based on register pressure.
    • > > +
  • Atomic code generation has been improved and is now in > conformance with > > + the latest psABI specification, thanks to Patrick O'Neill from > > + Rivos.
    • > > +
  • Support for the vector intrinsics as specified in > > + https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/v1.0.x'> > > + version 1.0 of the RISC-V vector intrinsic specification. > > +
  • Support for the experimental vector crypto intrinsics as > specified in > > + https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234'> > > + RISC-V vector intrinsic specification, thanks to Feng Wang et > al. > > + from ESWIN > Computing
    • > > +
  • Support for the T-head vector intrinsics.
    • > > +
  • Support for the scalar bitmanip and scalar crypto intrinsics, > thanks to > > + Liao Shihua from PLCT.
    • > > +
  • Support for the large code model via option > -mcmodel=3Dlarge, > > + thanks to Kuan-Lin Chen from > > + Andes Technology.
    • > > +
  • Support for the standard vector calling convention variant, > thanks to > > + Lehua Ding from '>RiVAI.
    • > > +
  • Supports the target attribute, which allows users to > compile > > + a function with specific extensions.
    • > > +
  • -march=3D option no longer requires the architecture > string > > + to be in canonical order, with only a few constraints remaining: > the > > + architecture string must start with > rv[32|64][i|g|e], and > > + must use an underscore as the separator after a multi-letter > extension. > > +
    • > > +
  • -march=3Dhelp option has been introduced to dump all > > + supported extensions.
    • > > +
  • Added experimental support for the > -mrvv-vector-bits=3Dzvl > > + option and the riscv_rvv_vector_bits attribute, whi= ch > > + specify a fixed length for scalable vector types. This option is > > + optimized for specific vector core implementations; however, the > code > > + generated with this option is NOT portable, > > IIUC the code is just optimized for a specific vector length, not any > specific core. It's portable to other cores, just not portable to cores > with different vector lengths. > > So I think we can soften the language a bit there, as it's not like > we're emitting vendor-specific code on this one. > > > + thanks to Pan Li from Intel. > > +
    • > > +
  • Support for TLS descriptors has been introduced, which can be > enabled by > > + the -mtls-dialect=3Ddesc option. The default behavi= or > can be > > + configured with --with-tls=3D[trad|desc].
    • > > +
  • Support for the TLS descriptors, this can be enabled by > > + -mtls-dialect=3Ddesc and the default behavior can be > configure > > + by --with-tls=3D[trad|desc], thanks to Tatsuyuki Ishi from > > + Blue Whale > Systems > > Maybe should call out that this will require the next glibc release to > function correctly? > > > +
    • > > +
  • Support for the following standard extensions has been added: > > +
      > > +
    • Vector crypto extensions: > > +
        > > +
      • Zvbb
        • > > +
      • Zvkb
        • > > +
      • Zvbc
        • > > +
      • Zvkg
        • > > +
      • Zvkned
        • > > +
      • Zvkhna
        • > > +
      • Zvkhnb
        • > > +
      • Zvksed
        • > > +
      • Zvksh
        • > > +
      • Zvkn
        • > > +
      • Zvknc
        • > > +
      • Zvkng
        • > > +
      • Zvks
        • > > +
      • Zvksc
        • > > +
      • Zvksg
        • > > +
      • Zvkt
        • > > +
      > > +
      • > > +
    • Code size reduction extensions: > > +
        > > +
      • Zca
        • > > +
      • Zcb
        • > > +
      • Zce
        • > > +
      • Zcf
        • > > +
      • Zcd
        • > > +
      • Zcmp
        • > > +
      • Zcmt
        • > > +
      > > +
      • > > +
    • Zicond
      • > > +
    • Zfa
      • > > +
    • Ztso
      • > > +
    • Zvfbfmin
      • > > +
    • Zvfhmin
      • > > +
    • Zvfh
      • > > +
    • Za64rs
      • > > +
    • Za128rs
      • > > +
    • Ziccif
      • > > +
    • Ziccrse
      • > > +
    • Ziccamoa
      • > > +
    • Zicclsm
      • > > +
    • Zic64b
      • > > +
    • Smaia
      • > > +
    • Smepmp
      • > > +
    • Smstateen
      • > > +
    • Ssaia
      • > > +
    • Sscofpmf
      • > > +
    • Ssstateen
      • > > +
    • Sstc
      • > > +
    • Svinval
      • > > +
    • Svnapot
      • > > +
    • Svpbmt
      • > > +
    > > +
    • > > +
  • Support for the following vendor extensions has been added: > > +
      > > +
    • T-Head: > > +
        > > +
      • XTheadVector
        • > > +
      > > +
      • > > +
    • CORE-V: > > +
        > > +
      • XCVmac
        • > > +
      • XCValu
        • > > +
      • XCVelw
        • > > +
      • XCVsimd
        • > > +
      • XCVbi
        • > > +
      > > +
      • > > +
    • Ventana Micro: > > +
        > > +
      • XVentanaCondops
        • > > +
      > > +
      • > > +
    > > +
    • > > +
  • The following new CPUs are supported through the > -mcpu > > + option (GCC identifiers in parentheses). > > +
      > > +
    • SiFive's X280 (sifive-x280).
      • > > +
    • SiFive's P450 (sifive-p450).
      • > > +
    • SiFive's P670 (sifive-p670).
      • > > +
    > > +
    • > > +
  • The following new CPUs are supported through the > -mtune > > + option (GCC identifiers in parentheses). > > +
      > > +
    • Generic out-of-order core (generic-ooo).
      • > > +
    • SiFive's P400 series (sifive-p400-series).
      • > > +
    • SiFive's P600 series (sifive-p600-series).
      • > > +
    • XiangShan's Nanhu microarchitecture > (xiangshan-nanhu).
      • > > +
    > > +
    • > > +
> > > > > > Thanks for doing this. This all pretty minor wording stuff, so > > Reviewed-by: Palmer Dabbelt > Acked-by: Palmer Dabbelt > > Maybe next year we'll remember to ask submitters for these ;) > --0000000000004449250615ccff1a--