From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by sourceware.org (Postfix) with ESMTPS id 915113858C83 for ; Tue, 25 Apr 2023 13:57:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 915113858C83 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4ec9c7c6986so6096539e87.0 for ; Tue, 25 Apr 2023 06:57:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1682431027; x=1685023027; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=5qffAwQfR8zRz8X+1o8GmkqZGJ9PWBC1Nqnf4c0DeHs=; b=icZZOw8U6cKqWbDNnZR23RG6ZbRA4Zf2Mqct3LCLPiQwMiGqaVH/9gi++Fk6gWXxEm 0uUamgaumnvXTh5QToQIaERYKKVsCfyUdzusizvjTrccYiBZmcjjR1GwKozhNE2ZN/ia jU5BarwJA1CAf9A/UAH74nKsyrjWkfd9jGyGaG5vDK4POImEfp7omyDfO1KBRYwwIjsX Ug5hVX8EZrrZ2JiIW8l0OxT7PWdV9lEEAQVo/NtOIfE0Qo8mzq2oG3FNbrOj+XMoxsmM sfCIGOsOcHSm3XQqQfTvuof7u0c+VtX4pVhFs49MkDWvhRt6vniTPn7DpZSs6oI04iY4 b3xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682431027; x=1685023027; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5qffAwQfR8zRz8X+1o8GmkqZGJ9PWBC1Nqnf4c0DeHs=; b=I9vYJUK4/yTZkanqrzWSHUL6c2P5OypI4eIQyKrAH45/4ZLQgIhuFOeqpIX+sETbZE 13+Pb9EqlMBBNO5uvs9jQ/0dQo84rJ3lydszKPEqsGEnxxzwI0QeETtZ2VITiMf+wMQN bwY/ZJm5cH3ARPYc8kVAGr+ElgTpsO4SBb3tzERm93F72ih9d76J8JxRKOPf/1Kkh6MQ xnukfvvCBudZFXe8dFf6pwjLVzPQacDBwVcMyDn6KJhcylDkrE5MYvDbobODl0Zippl1 rEQ2Rnkn6Hbuts3YDEddYCT3lzF/wmsvJF+Z3euSu16NjAr/9kEQQFi/hlNlJhSJX3d8 9kVQ== X-Gm-Message-State: AAQBX9dkH2hN7NTP9xXwHCT5vl+H2wJKVeoc405eYnQqV2NTpDI1Kjnj k9hDsL8k9Qu6kgmm8VoZGFrV5UCDW0gK9HPNu2YhMA== X-Google-Smtp-Source: AKy350a4JIi97HEkN85wR43c8XauLr8vAP19FDpLmExYLrujmLXx2Ei90wAg3HmZymBBVZotLp3OiwdRycTl7hKvulk= X-Received: by 2002:ac2:561a:0:b0:4e9:9f10:b31d with SMTP id v26-20020ac2561a000000b004e99f10b31dmr4533298lfd.2.1682431026997; Tue, 25 Apr 2023 06:57:06 -0700 (PDT) MIME-Version: 1.0 References: <20230419032117.930737-1-pan2.li@intel.com> <2908B8F5933F9196+20230419174105693011142@rivai.ai> In-Reply-To: From: Kito Cheng Date: Tue, 25 Apr 2023 21:56:55 +0800 Message-ID: Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization To: "Li, Pan2" Cc: Kito Cheng , Jeff Law , "juzhe.zhong@rivai.ai" , gcc-patches , "Wang, Yanzhang" Content-Type: multipart/alternative; boundary="000000000000b9536105fa297f27" X-Spam-Status: No, score=-3.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000b9536105fa297f27 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable I would strongly prefer 2 since I believe this won't be the last optimization we did for this kind of thing, and I don't want to see we need to fix or worry about vsetvli stuff every time if possible. And the current pattern design is more reasonable to me - only defining those fields is really useful. On Tue, Apr 25, 2023 at 9:51=E2=80=AFPM Li, Pan2 wrote: > Thanks Kito. > > Actually I fixed the below ICE with all riscv tests passed, but hold the > PATCH v3 as may conflict with one of Juzhe's PATCH. > > Thus, there will be 2 options for the shortcut optimization. > > 1. Adjust existing define and let the underlying pass to perform the > optimization. > 2. Add new define_split(s) for each of the shortcut optimization. > > Personally I may prefer the option 1. But here we would like the figure > out the one and the only one right way for the implementation. Thus, it is > OK if we think option 2 is a better way for this. > > Kito and Juzhe, any idea for making the decision? Thanks in advance! > > Pan > > -----Original Message----- > From: Kito Cheng > Sent: Tuesday, April 25, 2023 9:08 PM > To: Li, Pan2 ; Jeff Law > Cc: juzhe.zhong@rivai.ai; gcc-patches ; > Kito.cheng ; Wang, Yanzhang < > yanzhang.wang@intel.com> > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut > optimization > > Second thought on this, we should just add define_split rather than > define_insn_and_split, otherwise we might hit the same issue again, and I > expect the split pattern will only used in combine pass. > > On Sat, Apr 22, 2023 at 1:34=E2=80=AFPM Li, Pan2 via Gcc-patches > > wrote: > > > > Hi Kito > > > > Thanks for the suggestion. Sorry for late response due to stuck in the > rest rvv test files auto generation. > > > > I have similar discuss with juzhe for this approach, and take Patch v2's > way due to the below concern. > > > > 1. The vector.md Is quite complicated already, the maintenance may be > out of control if we will add many new define_insn_and_split for the > shortcut. > > 2. The new added pattern may not friendly for the underlying > auto-vectorization. > > > > Juzhe can help to correct me if any misleading. > > > > Pan > > > > -----Original Message----- > > From: Kito Cheng > > Sent: Friday, April 21, 2023 9:02 PM > > To: Li, Pan2 > > Cc: juzhe.zhong@rivai.ai; gcc-patches ; > > Kito.cheng ; Wang, Yanzhang > > > > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut > > optimization > > > > Hi Pan: > > > > One idea come to my mind, maybe we should add a new > > define_insn_and_split pattern instead of change @pred_mov > > > > On Fri, Apr 21, 2023 at 7:17=E2=80=AFPM Li, Pan2 via Gcc-patches < > gcc-patches@gcc.gnu.org> wrote: > > > > > > Thanks kito, will try to reproduce this issue and keep you posted. > > > > > > Pan > > > > > > -----Original Message----- > > > From: Kito Cheng > > > Sent: Friday, April 21, 2023 6:17 PM > > > To: Li, Pan2 > > > Cc: juzhe.zhong@rivai.ai; gcc-patches ; > > > Kito.cheng ; Wang, Yanzhang > > > > > > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) > > > shortcut optimization > > > > > > I got a bunch of new fails including ICE for gcc testsuite, and some > cases are hanging there, could you take a look? > > > > > > $ riscv64-unknown-linux-gnu-gcc > > > gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=3Drv32gcv > > > -mabi=3Dilp32 > > > during RTL pass: expand > > > > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/tes= tsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c: > > > In function 'f': > > > > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/tes= tsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:8:13: > > > internal compiler error: in maybe_gen_insn, at optabs.cc:8102 > > > 8 | vbool64_t mask =3D *(vbool64_t*) (in + 1000000); > > > | ^~~~ > > > 0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*) > > > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102 > > > > > > > > > On Fri, Apr 21, 2023 at 5:47=E2=80=AFPM Li, Pan2 via Gcc-patches < > gcc-patches@gcc.gnu.org> wrote: > > > > > > > > Kindly ping for the PATCH v2. Just FYI there will be some underlying > investigation based on this PATCH like VMSEQ. > > > > > > > > Pan > > > > > > > > -----Original Message----- > > > > From: Li, Pan2 > > > > Sent: Wednesday, April 19, 2023 7:27 PM > > > > To: 'Kito Cheng' ; 'juzhe.zhong@rivai.ai' > > > > > > > > Cc: 'gcc-patches' ; 'Kito.cheng' > > > > ; Wang, Yanzhang > > > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) > > > > shortcut optimization > > > > > > > > Update the Patch v2 for more detail information for clarification. > Please help to review continuously. > > > > > > > > https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html > > > > > > > > Pan > > > > > > > > -----Original Message----- > > > > From: Li, Pan2 > > > > Sent: Wednesday, April 19, 2023 6:33 PM > > > > To: Kito Cheng ; juzhe.zhong@rivai.ai > > > > Cc: gcc-patches ; Kito.cheng > > > > ; Wang, Yanzhang > > > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) > > > > shortcut optimization > > > > > > > > Sure thing. > > > > > > > > For Changlog, I consider it was generated automatically in previous. > LOL. > > > > > > > > Pan > > > > > > > > -----Original Message----- > > > > From: Kito Cheng > > > > Sent: Wednesday, April 19, 2023 5:46 PM > > > > To: juzhe.zhong@rivai.ai > > > > Cc: Li, Pan2 ; gcc-patches > > > > ; Kito.cheng ; > > > > Wang, Yanzhang > > > > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) > > > > shortcut optimization > > > > > > > > HI JuZhe: > > > > > > > > Thanks for explaining! > > > > > > > > > > > > Hi Pan: > > > > > > > > I think that would be helpful if JuZhe's explaining that could be > written into the commit log. > > > > > > > > > > > > > gcc/ChangeLog: > > > > > > > > > > * config/riscv/riscv-v.cc (emit_pred_op): > > > > > * config/riscv/riscv-vector-builtins-bases.cc: > > > > > * config/riscv/vector.md: > > > > > > > > And don't forgot write some thing in ChangeLog...:P > --000000000000b9536105fa297f27--