From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x92a.google.com (mail-ua1-x92a.google.com [IPv6:2607:f8b0:4864:20::92a]) by sourceware.org (Postfix) with ESMTPS id ACDA53857C59 for ; Thu, 2 Dec 2021 08:36:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org ACDA53857C59 Received: by mail-ua1-x92a.google.com with SMTP id p37so54347315uae.8 for ; Thu, 02 Dec 2021 00:36:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OMrOTmRy2QWq6pJ/xnvw4qgH+znuJ9NL8Oe5R8i5+mQ=; b=aQl2NwjjRB2mnsRyHTk6vbpVCUna0TBXZF8shzzqZjPQxmndO1RkCjO28Z8WVm/3fW zbYfdnu1vvAuxnMmvP1iHY3w2miBBZQ/kchwT9tQuAnydq28mm1CnfHUps2cGiM0Qu15 aoPOfolglQKDrYAK7E19Wx7NmONCd+GxzMFzPoyrxHoGUhnah57EzGycSP4/wGrOVnl4 50b2tQbk3or0SLK4pd8+mjtR+pJ6shxYIxFCAB8LcHyiIyRuhTouI+Gs9irLH+UqgKiY RIp/HtplL1trn+9LQKlQMXkfB8CxBhcGHF7B8zV9WeFCoqxHUEkc7u5NHbHh0vZZNQ/w NZFQ== X-Gm-Message-State: AOAM531RNh2OiFjqa7YBWXl9Ydpu5LopGnz7xixTcOdyrtTqLjyHZfbL 2RrhQf15v800A3h2ORHq5P9as1U37jFDLq6aXNcAoezm X-Google-Smtp-Source: ABdhPJx+vIt6SeecK1+FmFdyJSv4732uulj0SBuXR3t36Q32RVxrs0IU0SktuU0gVUtKV6wRvTX7MT/SomnQOa6Ge+Q= X-Received: by 2002:a67:c402:: with SMTP id c2mr13285173vsk.53.1638434192198; Thu, 02 Dec 2021 00:36:32 -0800 (PST) MIME-Version: 1.0 References: <20211202082752.62388-1-hongtao.liu@intel.com> In-Reply-To: <20211202082752.62388-1-hongtao.liu@intel.com> From: Hongtao Liu Date: Thu, 2 Dec 2021 16:43:47 +0800 Message-ID: Subject: Re: [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class. To: Uros Bizjak Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Dec 2021 08:36:34 -0000 On Thu, Dec 2, 2021 at 4:27 PM liuhongt wrote: > > The patch helps reload to choose GENENRAL_REGS alternatives for > SSE_FLOAT_MODE and enabled optimization like > > - vmovd %xmm0, -4(%rsp) > - movl $1, %eax > - addl -4(%rsp), %eax > + movd %xmm0, %eax > + addl $1, %eax > > Bootstrapped anf regtested on x86_64-pc-linux-gnu{-m32,} and > x86_64-pc-linux-gnu{-m32\ march=cascadelake,\ -march=cadcadelake}. > > No big performace impact is abserved for SPEC2017 on ICX/CLX with both > Ofast -march=native -flto -funroll-loops and -O2 -mtune=generic options. > > Ok for trunk? > > gcc/ChangeLog: > > PR target/95740 > * config/i386/i386.c (ix86_preferred_reload_class): Prefer > INT_SSE_REGS for SSE_FLOAT_MODE_P. > * config/i386/i386.h (INT_SSE_CLASS_P): New. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/pr95740.c: New test. > --- > gcc/config/i386/i386.c | 5 +++-- > gcc/config/i386/i386.h | 2 ++ > gcc/testsuite/gcc.target/i386/pr95740.c | 26 +++++++++++++++++++++++++ > 3 files changed, 31 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c > index 80fee627358..977af1c31a7 100644 > --- a/gcc/config/i386/i386.c > +++ b/gcc/config/i386/i386.c > @@ -19194,9 +19194,10 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass) > return NO_REGS; > } > > - /* Prefer SSE regs only, if we can use them for math. */ > + /* Prefer INT_SSE_REGS, enable reload from SSE register to GENERAL_REGS, > + refer to PR95740. */ > if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) > - return SSE_CLASS_P (regclass) ? regclass : NO_REGS; > + return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS; > > /* Generally when we see PLUS here, it's the function invariant > (plus soft-fp const_int). Which can only be computed into general > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h > index 2fda1e0686e..ec90e47904b 100644 > --- a/gcc/config/i386/i386.h > +++ b/gcc/config/i386/i386.h > @@ -1283,6 +1283,8 @@ enum reg_class > reg_class_subset_p ((CLASS), FLOAT_REGS) > #define SSE_CLASS_P(CLASS) \ > reg_class_subset_p ((CLASS), ALL_SSE_REGS) > +#define INT_SSE_CLASS_P(CLASS) \ > + reg_class_subset_p ((CLASS), INT_SSE_REGS) > #define MMX_CLASS_P(CLASS) \ > ((CLASS) == MMX_REGS) > #define MASK_CLASS_P(CLASS) \ > diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c > new file mode 100644 > index 00000000000..9bc7b862787 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr95740.c > @@ -0,0 +1,26 @@ > +/* { dg-do compile { target { ! ia32 } } } */ > +/* { dg-options "-msse2 -O2 -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */ > +/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */ > +/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */ > +/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */ > +/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */ > + > +int > +foo (float a) > +{ > + union{ > + int b; > + float a;}u; > + u.a = a; > + return u.b + 1; > +} > + > +long long > +foo1 (double a) > +{ > + union{ > + long long b; > + double a;}u; > + u.a = a; > + return u.b + 1; > +} > -- > 2.18.1 > -- BR, Hongtao