From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112b.google.com (mail-yw1-x112b.google.com [IPv6:2607:f8b0:4864:20::112b]) by sourceware.org (Postfix) with ESMTPS id 832553893659 for ; Tue, 15 Nov 2022 08:35:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 832553893659 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-3876f88d320so2122947b3.6 for ; Tue, 15 Nov 2022 00:35:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=cx/GStJWEIfzapz+VJOIxdGEBzJf0eTrSnBPrD4tKyg=; b=IL9yv7cltfIsshNM9XXbTyZ0C5QCBlChQI6LT5JRD4nZWxtKbGsDz3+UgSrMrgl83G oMm+ylZzB4R4WS/vTcSrzk5BNOVrKkHsv0+TrGd3pBxrq5SPPDHB+cteMvfybfKD8b/O EreHzlrNhXHfu6Qz+tZcLG4n4fVYFAstusNryxfKgIb+E9214Etgjr891lOQ47NgSqKD GAN5Svd4dtYJxyAeXVzrwnBidyBFHuzL5jSBY/rKVu/02M56T4lgrJ+trh6+PQzyye60 C4aHW2azHnz3pk7zbUbswv9BZAXnIhVLs5LI+YTezw7YVaQ2DmyVLGEFclbp18bl6HYk w96A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=cx/GStJWEIfzapz+VJOIxdGEBzJf0eTrSnBPrD4tKyg=; b=PGqkrjyL0Sxha1+8PDyLuPOl7UZW1xZHSWvX/9DcrwaLs2FFCWhDMtu2JNMa9vk9Hk qsYXCs9qpIQHoXY1YrlcR6kG5nRx7tBTW1osZJwqc9wOI6y52/5RHQySAdBqErz7v+av EOLRFFmmDKvzPfx8pT1s8VN3KGrM9jiu3BXjMxYa21xzCDL+W2O9AnPSrzgBj7P7rjhY ByxLH8nxtXdLJ0YhJaaZxTsk6JovJQNrIDEl1ZhxWf2MFwZBNyHy3RvS4uIeZ9As+kRz 0Je77aiWPCOlQoCgNmdHUSN3kuWQ7OkZ/VxmBOLhX4AYILBNRWIxNgMqreszhRJHuuZY SvLQ== X-Gm-Message-State: ANoB5pkkSB2XxUYvrFuZ/8ajDCxjN7w0Ji1nJiNx0sImjcR4SCeBkvVy qcRWMPy3uqBm+oYJVkEvaFmRzYCdFd80+3OOVVM= X-Google-Smtp-Source: AA0mqf78CNFDKEl3y/qWuYpR6hvkqUvSNg/lBNCgmEyI7WJ9I5+t65lgbrDRIdd2hsea2/pHIEnbAQze1gI0XLz5YWY= X-Received: by 2002:a81:a81:0:b0:36b:999a:da62 with SMTP id 123-20020a810a81000000b0036b999ada62mr16336976ywk.249.1668501343587; Tue, 15 Nov 2022 00:35:43 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Hongtao Liu Date: Tue, 15 Nov 2022 16:35:32 +0800 Message-ID: Subject: Re: [PATCH 3/8]middle-end: Support extractions of subvectors from arbitrary element position inside a vector To: Tamar Christina Cc: Richard Sandiford , Tamar Christina via Gcc-patches , nd , "rguenther@suse.de" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi: I'm from https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606040.html. > } > > /* See if we can get a better vector mode before extracting. */ > diff --git a/gcc/optabs.cc b/gcc/optabs.cc > index cff37ccb0dfc3dd79b97d0abfd872f340855dc96..f338df410265dfe55b6896160090a453cc6a28d9 100644 > --- a/gcc/optabs.cc > +++ b/gcc/optabs.cc > @@ -6267,6 +6267,7 @@ expand_vec_perm_const (machine_mode mode, rtx v0, rtx v1, > v0_qi = gen_lowpart (qimode, v0); > v1_qi = gen_lowpart (qimode, v1); > if (targetm.vectorize.vec_perm_const != NULL > + && targetm.can_change_mode_class (mode, qimode, ALL_REGS) It looks like you want to guard gen_lowpart, shouldn't it be better to use validate_subreg or (tmp = gen_lowpart_if_possible (mode, target_qi)). IMHO, targetm.can_change_mode_class is mostly used for RA, but not to guard gen_lowpart. I did similar things in https://gcc.gnu.org/pipermail/gcc-patches/2021-September/579296.html (and ALL_REGS doesn't cover all cases for registers which are both available for qimode and mode, ALL_REGS fail doesn't mean it can't be subreg, it just means parts of ALL_REGS can't be subreg. but with a subset of ALL_REGS, there could be a reg class which return true for targetm.can_change_mode_class) > && targetm.vectorize.vec_perm_const (qimode, qimode, target_qi, v0_qi, > v1_qi, qimode_indices)) > return gen_lowpart (mode, target_qi); > @@ -6311,7 +6312,8 @@ expand_vec_perm_const (machine_mode mode, rtx v0, rtx v1, > } > > if (qimode != VOIDmode > - && selector_fits_mode_p (qimode, qimode_indices)) > + && selector_fits_mode_p (qimode, qimode_indices) > + && targetm.can_change_mode_class (mode, qimode, ALL_REGS)) > { > icode = direct_optab_handler (vec_perm_optab, qimode); > if (icode != CODE_FOR_nothing) > diff --git a/gcc/testsuite/gcc.target/aarch64/ext_1.c b/gcc/testsuite/gcc.target/aarch64/ext_1.c > new file mode 100644 > index 0000000000000000000000000000000000000000..18a10a14f1161584267a8472e571b3bc2ddf887a -- BR, Hongtao