From: Hongtao Liu <crazylht@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
Hongtao Liu <hongtao.liu@intel.com>,
Kirill Yukhin <kirill.yukhin@gmail.com>
Subject: Re: [PATCH 1/5] x86: use VPTERNLOG for further bitwise two-vector operations
Date: Sun, 25 Jun 2023 15:23:19 +0800 [thread overview]
Message-ID: <CAMZc-bwb7mkOP9bEF5-a_ZS1=04dGBdSpWJ+X0YSGA41RtPQiQ@mail.gmail.com> (raw)
In-Reply-To: <CAMZc-bw5tqZm_gfGneq-2tk9KTG-irDUzQ0rxUHibmzSWmqjHw@mail.gmail.com>
On Sun, Jun 25, 2023 at 3:13 PM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Sun, Jun 25, 2023 at 1:52 PM Jan Beulich <jbeulich@suse.com> wrote:
> >
> > On 25.06.2023 06:42, Hongtao Liu wrote:
> > > On Wed, Jun 21, 2023 at 2:26 PM Jan Beulich via Gcc-patches
> > > <gcc-patches@gcc.gnu.org> wrote:
> > >>
> > >> +(define_code_iterator andor [and ior])
> > >> +(define_code_attr nlogic [(and "nor") (ior "nand")])
> > >> +(define_code_attr ternlog_nlogic [(and "0x11") (ior "0x77")])
> > >> +
> > >> +(define_insn "*<nlogic><mode>3"
> > >> + [(set (match_operand:VI 0 "register_operand" "=v,v")
> > >> + (andor:VI
> > >> + (not:VI (match_operand:VI 1 "bcst_vector_operand" "%v,v"))
> > >> + (not:VI (match_operand:VI 2 "bcst_vector_operand" "vBr,m"))))]
> > > I'm thinking of doing it in simplify_rtx or gimple match.pd to transform
> > > (and (not op1)) (not op2)) -> (not: (ior: op1 op2))
> >
> > This wouldn't be a win (not + andn) -> (or + not), but what's
> > more important is ...
> >
> > > (ior (not op1) (not op2)) -> (not : (and op1 op2))
> > >
> > > Even w/o avx512f, the transformation should also benefit since it
> > > takes less logic operations 3 -> 2.(or 2 -> 2 for pandn).
> >
> > ... that these transformations (from the, as per the doc,
> > canonical representation of nand and nor) are already occurring
> I see, there're already such simplifications in the gimple phase, so
> the question: is there any need for and/ior:not not pattern?
> Can you provide a testcase to demonstrate that and/ior: not not
> pattern is needed?
typedef int v4si __attribute__((vector_size(16)));
v4si
foo1 (v4si a, v4si b)
{
return ~a & ~b;
}
I only gimple have optimized it to
<bb 2> [local count: 1073741824]:
# DEBUG BEGIN_STMT
_1 = a_2(D) | b_3(D);
_4 = ~_1;
return _4;
But rtl still try to match
(set (reg:V4SI 86)
(and:V4SI (not:V4SI (reg:V4SI 88))
(not:V4SI (reg:V4SI 89))))
Hmm.
> > in common code, _if_ no suitable insn can be found. That was at
> > least the conclusion I drew from looking around a lot, supported
> > by the code that's generated prior to this change.
> >
> > Jan
>
>
>
> --
> BR,
> Hongtao
--
BR,
Hongtao
next prev parent reply other threads:[~2023-06-25 7:23 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-21 6:24 [PATCH 0/5] x86: make better use of VPTERNLOG{D,Q} Jan Beulich
2023-06-21 6:25 ` [PATCH 1/5] x86: use VPTERNLOG for further bitwise two-vector operations Jan Beulich
2023-06-25 4:42 ` Hongtao Liu
2023-06-25 5:52 ` Jan Beulich
2023-06-25 7:13 ` Hongtao Liu
2023-06-25 7:23 ` Hongtao Liu [this message]
2023-06-25 7:30 ` Hongtao Liu
2023-06-25 13:35 ` Jan Beulich
2023-06-26 0:42 ` Hongtao Liu
2023-06-21 6:27 ` [PATCH 2/5] x86: use VPTERNLOG also for certain andnot forms Jan Beulich
2023-06-25 4:58 ` Hongtao Liu
2023-06-21 6:27 ` [PATCH 3/5] x86: allow memory operand for AVX2 splitter for PR target/100711 Jan Beulich
2023-06-25 4:58 ` Hongtao Liu
2023-06-21 6:27 ` [PATCH 4/5] x86: further PR target/100711-like splitting Jan Beulich
2023-06-25 5:06 ` Hongtao Liu
2023-06-25 6:16 ` Jan Beulich
2023-06-25 6:27 ` Hongtao Liu
2023-06-21 6:28 ` [PATCH 5/5] x86: yet more " Jan Beulich
2023-06-25 5:12 ` Hongtao Liu
2023-06-25 6:25 ` Jan Beulich
2023-06-25 6:35 ` Hongtao Liu
2023-06-25 6:41 ` Hongtao Liu
2023-11-06 11:10 ` Jan Beulich
2023-11-06 13:48 ` Hongtao Liu
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