From: Hongtao Liu <crazylht@gmail.com>
To: liuhongt <hongtao.liu@intel.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH 0/3] [i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512
Date: Wed, 4 Aug 2021 20:48:42 +0800 [thread overview]
Message-ID: <CAMZc-bwbk2KzCe+ASm4pOPY0568=S8T5PGfP4vY2WwT1Fwiasg@mail.gmail.com> (raw)
In-Reply-To: <20210804123928.90586-1-hongtao.liu@intel.com>
On Wed, Aug 4, 2021 at 8:39 PM liuhongt <hongtao.liu@intel.com> wrote:
>
> Hi:
> Together with the previous 3 patches, all cond_op expanders of vector
> modes are supported (if they have a corresponding avx512 mask instruction).
Oh, after double check, I realize there're still shift instructions
left, will support in another patch,
OPTAB_D (cond_ashl_optab, "cond_ashl$a")
OPTAB_D (cond_ashr_optab, "cond_ashr$a")
OPTAB_D (cond_lshr_optab, "cond_lshr$a")
>
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
>
> liuhongt (3):
> [i386] Support cond_{smax,smin,umax,umin} for vector integer modes
> under AVX512.
> [i386] Support cond_{smax,smin} for vector float/double modes under
> AVX512.
> [i386] Support cond_{xor,ior,and} for vector integer mode under
> AVX512.
>
> gcc/config/i386/sse.md | 54 +++++++++++++
> .../gcc.target/i386/cond_op_anylogic_d-1.c | 38 +++++++++
> .../gcc.target/i386/cond_op_anylogic_d-2.c | 78 +++++++++++++++++++
> .../gcc.target/i386/cond_op_anylogic_q-1.c | 10 +++
> .../gcc.target/i386/cond_op_anylogic_q-2.c | 5 ++
> .../gcc.target/i386/cond_op_maxmin_b-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_b-2.c | 6 ++
> .../gcc.target/i386/cond_op_maxmin_d-1.c | 41 ++++++++++
> .../gcc.target/i386/cond_op_maxmin_d-2.c | 67 ++++++++++++++++
> .../gcc.target/i386/cond_op_maxmin_double-1.c | 39 ++++++++++
> .../gcc.target/i386/cond_op_maxmin_double-2.c | 67 ++++++++++++++++
> .../gcc.target/i386/cond_op_maxmin_float-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_float-2.c | 5 ++
> .../gcc.target/i386/cond_op_maxmin_q-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_q-2.c | 5 ++
> .../gcc.target/i386/cond_op_maxmin_ub-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_ub-2.c | 6 ++
> .../gcc.target/i386/cond_op_maxmin_ud-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_ud-2.c | 5 ++
> .../gcc.target/i386/cond_op_maxmin_uq-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_uq-2.c | 5 ++
> .../gcc.target/i386/cond_op_maxmin_uw-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_uw-2.c | 6 ++
> .../gcc.target/i386/cond_op_maxmin_w-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_w-2.c | 6 ++
> 25 files changed, 507 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-2.c
>
> --
> 2.18.1
>
--
BR,
Hongtao
prev parent reply other threads:[~2021-08-04 12:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-04 12:39 liuhongt
2021-08-04 12:39 ` [PATCH 1/3] [i386] Support cond_{smax, smin, umax, umin} for vector integer " liuhongt
2021-08-04 12:39 ` [PATCH 2/3] [i386] Support cond_{smax, smin} for vector float/double " liuhongt
2021-08-04 12:39 ` [PATCH 3/3] [i386] Support cond_{xor, ior, and} for vector integer mode " liuhongt
2021-08-04 12:48 ` Hongtao Liu [this message]
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