* [PATCH 1/3] [i386] Support cond_{smax, smin, umax, umin} for vector integer modes under AVX512.
2021-08-04 12:39 [PATCH 0/3] [i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512 liuhongt
@ 2021-08-04 12:39 ` liuhongt
2021-08-04 12:39 ` [PATCH 2/3] [i386] Support cond_{smax, smin} for vector float/double " liuhongt
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: liuhongt @ 2021-08-04 12:39 UTC (permalink / raw)
To: gcc-patches
gcc/ChangeLog:
* config/i386/sse.md (cond_<code><mode>): New expander.
gcc/testsuite/ChangeLog:
* gcc.target/i386/cond_op_maxmin_b-1.c: New test.
* gcc.target/i386/cond_op_maxmin_b-2.c: New test.
* gcc.target/i386/cond_op_maxmin_d-1.c: New test.
* gcc.target/i386/cond_op_maxmin_d-2.c: New test.
* gcc.target/i386/cond_op_maxmin_q-1.c: New test.
* gcc.target/i386/cond_op_maxmin_q-2.c: New test.
* gcc.target/i386/cond_op_maxmin_ub-1.c: New test.
* gcc.target/i386/cond_op_maxmin_ub-2.c: New test.
* gcc.target/i386/cond_op_maxmin_ud-1.c: New test.
* gcc.target/i386/cond_op_maxmin_ud-2.c: New test.
* gcc.target/i386/cond_op_maxmin_uq-1.c: New test.
* gcc.target/i386/cond_op_maxmin_uq-2.c: New test.
* gcc.target/i386/cond_op_maxmin_uw-1.c: New test.
* gcc.target/i386/cond_op_maxmin_uw-2.c: New test.
* gcc.target/i386/cond_op_maxmin_w-1.c: New test.
* gcc.target/i386/cond_op_maxmin_w-2.c: New test.
---
gcc/config/i386/sse.md | 18 +++++
.../gcc.target/i386/cond_op_maxmin_b-1.c | 8 +++
.../gcc.target/i386/cond_op_maxmin_b-2.c | 6 ++
.../gcc.target/i386/cond_op_maxmin_d-1.c | 41 ++++++++++++
.../gcc.target/i386/cond_op_maxmin_d-2.c | 67 +++++++++++++++++++
.../gcc.target/i386/cond_op_maxmin_q-1.c | 8 +++
.../gcc.target/i386/cond_op_maxmin_q-2.c | 5 ++
.../gcc.target/i386/cond_op_maxmin_ub-1.c | 8 +++
.../gcc.target/i386/cond_op_maxmin_ub-2.c | 6 ++
.../gcc.target/i386/cond_op_maxmin_ud-1.c | 8 +++
.../gcc.target/i386/cond_op_maxmin_ud-2.c | 5 ++
.../gcc.target/i386/cond_op_maxmin_uq-1.c | 8 +++
.../gcc.target/i386/cond_op_maxmin_uq-2.c | 5 ++
.../gcc.target/i386/cond_op_maxmin_uw-1.c | 8 +++
.../gcc.target/i386/cond_op_maxmin_uw-2.c | 6 ++
.../gcc.target/i386/cond_op_maxmin_w-1.c | 8 +++
.../gcc.target/i386/cond_op_maxmin_w-2.c | 6 ++
17 files changed, 221 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-2.c
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index f5968e04669..6035411ea75 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -13070,6 +13070,24 @@ (define_insn "*avx2_<code><mode>3"
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
+(define_expand "cond_<code><mode>"
+ [(set (match_operand:VI1248_AVX512VLBW 0 "register_operand")
+ (vec_merge:VI1248_AVX512VLBW
+ (maxmin:VI1248_AVX512VLBW
+ (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand")
+ (match_operand:VI1248_AVX512VLBW 3 "nonimmediate_operand"))
+ (match_operand:VI1248_AVX512VLBW 4 "nonimm_or_0_operand")
+ (match_operand:<avx512fmaskmode> 1 "register_operand")))]
+ "TARGET_AVX512F"
+{
+ emit_insn (gen_<code><mode>3_mask (operands[0],
+ operands[2],
+ operands[3],
+ operands[4],
+ operands[1]));
+ DONE;
+})
+
(define_expand "<code><mode>3_mask"
[(set (match_operand:VI48_AVX512VL 0 "register_operand")
(vec_merge:VI48_AVX512VL
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-1.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-1.c
new file mode 100644
index 00000000000..78c6600f83b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -DTYPE=int8 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump ".COND_MAX" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_MIN" "optimized" } } */
+/* { dg-final { scan-assembler-times "vpmaxsb" 1 } } */
+/* { dg-final { scan-assembler-times "vpminsb" 1 } } */
+
+#include "cond_op_maxmin_d-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-2.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-2.c
new file mode 100644
index 00000000000..8ba7a3fe4c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-2.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw -mprefer-vector-width=256 -DTYPE=int8" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512bw } */
+
+#include "cond_op_maxmin_d-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-1.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-1.c
new file mode 100644
index 00000000000..2543d36f5a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-1.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump ".COND_MAX" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_MIN" "optimized" } } */
+/* { dg-final { scan-assembler-times "vpmaxsd" 1 } } */
+/* { dg-final { scan-assembler-times "vpminsd" 1 } } */
+
+typedef char int8;
+typedef unsigned char uint8;
+typedef short int16;
+typedef unsigned short uint16;
+typedef int int32;
+typedef unsigned int uint32;
+typedef long long int64;
+typedef unsigned long long uint64;
+
+#ifndef NUM
+#define NUM 800
+#endif
+#ifndef TYPE
+#define TYPE int
+#endif
+
+TYPE a[NUM], b[NUM], c[NUM], d[NUM], e[NUM], j[NUM];
+#define MIN(X,Y) ((X) < (Y) ? (X) : (Y))
+#define MAX(X,Y) ((X) < (Y) ? (Y) : (X))
+
+#define BIN(OPNAME, OP) \
+ void \
+ __attribute__ ((noipa,optimize ("O3"))) \
+ foo_##OPNAME () \
+ { \
+ for (int i = 0; i != NUM; i++) \
+ if (b[i] < c[i]) \
+ a[i] = OP(d[i], e[i]); \
+ else \
+ a[i] = d[i] - e[i]; \
+ }
+
+BIN (max, MAX);
+BIN (min, MIN);
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-2.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-2.c
new file mode 100644
index 00000000000..f715f54e599
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-2.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256" } */
+/* { dg-require-effective-target avx512vl } */
+
+#define AVX512VL
+#ifndef CHECK
+#define CHECK "avx512f-helper.h"
+#endif
+
+#include CHECK
+
+#include "cond_op_maxmin_d-1.c"
+#define BINO2(OPNAME, OP) \
+ void \
+ __attribute__ ((noipa,optimize ("O2"))) \
+ foo_o2_##OPNAME () \
+ { \
+ for (int i = 0; i != NUM; i++) \
+ if (b[i] < c[i]) \
+ j[i] = OP(d[i], e[i]); \
+ else \
+ j[i] = d[i] - e[i]; \
+ }
+
+BINO2 (max, MAX);
+BINO2 (min, MIN);
+
+static void
+test_256 (void)
+{
+ int sign = -1;
+ for (int i = 0; i != NUM; i++)
+ {
+ a[i] = 0;
+ d[i] = i * 2;
+ e[i] = i * i * 3 - i * 9 + 153;
+ b[i] = i * 83;
+ c[i] = b[i] + sign;
+ sign *= -1;
+ j[i] = 1;
+ }
+ foo_max ();
+ foo_o2_max ();
+ for (int i = 0; i != NUM; i++)
+ {
+ if (a[i] != j[i])
+ abort ();
+ a[i] = 0;
+ b[i] = 1;
+ }
+
+ foo_min ();
+ foo_o2_min ();
+ for (int i = 0; i != NUM; i++)
+ {
+ if (a[i] != j[i])
+ abort ();
+ a[i] = 0;
+ j[i] = 1;
+ }
+}
+
+static void
+test_128 ()
+{
+
+}
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-1.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-1.c
new file mode 100644
index 00000000000..a1925c12ee0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -DTYPE=int64 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump ".COND_MAX" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_MIN" "optimized" } } */
+/* { dg-final { scan-assembler-times "vpmaxsq" 1 } } */
+/* { dg-final { scan-assembler-times "vpminsq" 1 } } */
+
+#include "cond_op_maxmin_d-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-2.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-2.c
new file mode 100644
index 00000000000..205a65a74a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-2.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256 -DTYPE=int64" } */
+/* { dg-require-effective-target avx512vl } */
+
+#include "cond_op_maxmin_d-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-1.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-1.c
new file mode 100644
index 00000000000..117179f2109
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -DTYPE=uint8 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump ".COND_MAX" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_MIN" "optimized" } } */
+/* { dg-final { scan-assembler-times "vpmaxub" 1 } } */
+/* { dg-final { scan-assembler-times "vpminub" 1 } } */
+
+#include "cond_op_maxmin_d-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-2.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-2.c
new file mode 100644
index 00000000000..ac4a2064edc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-2.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw -mprefer-vector-width=256 -DTYPE=uint8" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512bw } */
+
+#include "cond_op_maxmin_d-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-1.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-1.c
new file mode 100644
index 00000000000..1ce0f8210bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -DTYPE=uint32 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump ".COND_MAX" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_MIN" "optimized" } } */
+/* { dg-final { scan-assembler-times "vpmaxud" 1 } } */
+/* { dg-final { scan-assembler-times "vpminud" 1 } } */
+
+#include "cond_op_maxmin_d-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-2.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-2.c
new file mode 100644
index 00000000000..d609ef07a05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-2.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256 -DTYPE=uint32" } */
+/* { dg-require-effective-target avx512vl } */
+
+#include "cond_op_maxmin_d-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-1.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-1.c
new file mode 100644
index 00000000000..82209f4b73c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -DTYPE=uint64 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump ".COND_MAX" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_MIN" "optimized" } } */
+/* { dg-final { scan-assembler-times "vpmaxuq" 1 } } */
+/* { dg-final { scan-assembler-times "vpminuq" 1 } } */
+
+#include "cond_op_maxmin_d-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-2.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-2.c
new file mode 100644
index 00000000000..c2053c0528b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-2.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256 -DTYPE=uint64" } */
+/* { dg-require-effective-target avx512vl } */
+
+#include "cond_op_maxmin_d-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-1.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-1.c
new file mode 100644
index 00000000000..43d560d6c41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -DTYPE=uint16 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump ".COND_MAX" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_MIN" "optimized" } } */
+/* { dg-final { scan-assembler-times "vpmaxuw" 1 } } */
+/* { dg-final { scan-assembler-times "vpminuw" 1 } } */
+
+#include "cond_op_maxmin_d-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-2.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-2.c
new file mode 100644
index 00000000000..463fc520823
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-2.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw -mprefer-vector-width=256 -DTYPE=uint16" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512bw } */
+
+#include "cond_op_maxmin_d-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-1.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-1.c
new file mode 100644
index 00000000000..d4d388e4915
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -DTYPE=int16 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump ".COND_MAX" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_MIN" "optimized" } } */
+/* { dg-final { scan-assembler-times "vpmaxsw" 1 } } */
+/* { dg-final { scan-assembler-times "vpminsw" 1 } } */
+
+#include "cond_op_maxmin_d-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-2.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-2.c
new file mode 100644
index 00000000000..d6e45e5653d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-2.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw -mprefer-vector-width=256 -DTYPE=int16" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512bw } */
+
+#include "cond_op_maxmin_d-2.c"
--
2.18.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 2/3] [i386] Support cond_{smax, smin} for vector float/double modes under AVX512.
2021-08-04 12:39 [PATCH 0/3] [i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512 liuhongt
2021-08-04 12:39 ` [PATCH 1/3] [i386] Support cond_{smax, smin, umax, umin} for vector integer " liuhongt
@ 2021-08-04 12:39 ` liuhongt
2021-08-04 12:39 ` [PATCH 3/3] [i386] Support cond_{xor, ior, and} for vector integer mode " liuhongt
2021-08-04 12:48 ` [PATCH 0/3] [i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes " Hongtao Liu
3 siblings, 0 replies; 5+ messages in thread
From: liuhongt @ 2021-08-04 12:39 UTC (permalink / raw)
To: gcc-patches
gcc/ChangeLog:
* config/i386/sse.md (cond_<code><mode>): New expander.
gcc/testsuite/ChangeLog:
* gcc.target/i386/cond_op_maxmin_double-1.c: New test.
* gcc.target/i386/cond_op_maxmin_double-2.c: New test.
* gcc.target/i386/cond_op_maxmin_float-1.c: New test.
* gcc.target/i386/cond_op_maxmin_float-2.c: New test.
---
gcc/config/i386/sse.md | 18 +++++
.../gcc.target/i386/cond_op_maxmin_double-1.c | 39 +++++++++++
.../gcc.target/i386/cond_op_maxmin_double-2.c | 67 +++++++++++++++++++
.../gcc.target/i386/cond_op_maxmin_float-1.c | 8 +++
.../gcc.target/i386/cond_op_maxmin_float-2.c | 5 ++
5 files changed, 137 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-2.c
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 6035411ea75..51733a3849d 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2376,6 +2376,24 @@ (define_insn "*sse_vmrsqrtv4sf2"
(set_attr "prefix" "orig,vex")
(set_attr "mode" "SF")])
+(define_expand "cond_<code><mode>"
+ [(set (match_operand:VF 0 "register_operand")
+ (vec_merge:VF
+ (smaxmin:VF
+ (match_operand:VF 2 "vector_operand")
+ (match_operand:VF 3 "vector_operand"))
+ (match_operand:VF 4 "nonimm_or_0_operand")
+ (match_operand:<avx512fmaskmode> 1 "register_operand")))]
+ "<MODE_SIZE> == 64 || TARGET_AVX512VL"
+{
+ emit_insn (gen_<code><mode>3_mask (operands[0],
+ operands[2],
+ operands[3],
+ operands[4],
+ operands[1]));
+ DONE;
+})
+
(define_expand "<code><mode>3<mask_name><round_saeonly_name>"
[(set (match_operand:VF 0 "register_operand")
(smaxmin:VF
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-1.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-1.c
new file mode 100644
index 00000000000..eda8e1974b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-1.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump ".COND_MAX" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_MIN" "optimized" } } */
+/* { dg-final { scan-assembler-times "vmaxpd" 1 } } */
+/* { dg-final { scan-assembler-times "vminpd" 1 } } */
+
+#include<math.h>
+#ifndef NUM
+#define NUM 800
+#endif
+#ifndef TYPE
+#define TYPE double
+#endif
+#ifndef FN_MAX
+#define FN_MAX fmax
+#endif
+#ifndef FN_MIN
+#define FN_MIN fmin
+#endif
+
+TYPE a[NUM], b[NUM], c[NUM], d[NUM], e[NUM], j[NUM];
+#define MAX FN_MAX
+#define MIN FN_MIN
+
+#define BIN(OPNAME, OP) \
+ void \
+ __attribute__ ((noipa,optimize ("Ofast"))) \
+ foo_##OPNAME () \
+ { \
+ for (int i = 0; i != NUM; i++) \
+ if (b[i] < c[i]) \
+ a[i] = (OP (d[i], e[i])); \
+ else \
+ a[i] = d[i] - e[i]; \
+ }
+
+BIN (max, MAX);
+BIN (min, MIN);
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-2.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-2.c
new file mode 100644
index 00000000000..c50a831000a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-2.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256 -ffast-math" } */
+/* { dg-require-effective-target avx512vl } */
+
+#define AVX512VL
+#ifndef CHECK
+#define CHECK "avx512f-helper.h"
+#endif
+
+#include CHECK
+
+#include "cond_op_maxmin_double-1.c"
+#define BINO2(OPNAME, OP) \
+ void \
+ __attribute__ ((noipa)) \
+ foo_o2_##OPNAME () \
+ { \
+ for (int i = 0; i != NUM; i++) \
+ if (b[i] < c[i]) \
+ j[i] = OP(d[i], e[i]); \
+ else \
+ j[i] = d[i] - e[i]; \
+ }
+
+BINO2 (max, MAX);
+BINO2 (min, MIN);
+
+static void
+test_256 (void)
+{
+ int sign = -1;
+ for (int i = 0; i != NUM; i++)
+ {
+ a[i] = 0;
+ d[i] = i * 2;
+ e[i] = i * i * 3 - i * 9 + 153;
+ b[i] = i * 83;
+ c[i] = b[i] + sign;
+ sign *= -1;
+ j[i] = 1;
+ }
+ foo_max ();
+ foo_o2_max ();
+ for (int i = 0; i != NUM; i++)
+ {
+ if (a[i] != j[i])
+ abort ();
+ a[i] = 0;
+ b[i] = 1;
+ }
+
+ foo_min ();
+ foo_o2_min ();
+ for (int i = 0; i != NUM; i++)
+ {
+ if (a[i] != j[i])
+ abort ();
+ a[i] = 0;
+ j[i] = 1;
+ }
+}
+
+static void
+test_128 ()
+{
+
+}
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-1.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-1.c
new file mode 100644
index 00000000000..2d2157d87a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -DTYPE=float -fdump-tree-optimized -DFN_MAX=fmaxf -DFN_MIN=fminf" } */
+/* { dg-final { scan-tree-dump ".COND_MAX" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_MIN" "optimized" } } */
+/* { dg-final { scan-assembler-times "vmaxps" 1 } } */
+/* { dg-final { scan-assembler-times "vminps" 1 } } */
+
+#include "cond_op_maxmin_double-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-2.c b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-2.c
new file mode 100644
index 00000000000..fec784e5ded
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-2.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256 -DTYPE=float -DFN_MAX=fmaxf -DFN_MIN=fminf" } */
+/* { dg-require-effective-target avx512vl } */
+
+#include "cond_op_maxmin_double-2.c"
--
2.18.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 3/3] [i386] Support cond_{xor, ior, and} for vector integer mode under AVX512.
2021-08-04 12:39 [PATCH 0/3] [i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512 liuhongt
2021-08-04 12:39 ` [PATCH 1/3] [i386] Support cond_{smax, smin, umax, umin} for vector integer " liuhongt
2021-08-04 12:39 ` [PATCH 2/3] [i386] Support cond_{smax, smin} for vector float/double " liuhongt
@ 2021-08-04 12:39 ` liuhongt
2021-08-04 12:48 ` [PATCH 0/3] [i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes " Hongtao Liu
3 siblings, 0 replies; 5+ messages in thread
From: liuhongt @ 2021-08-04 12:39 UTC (permalink / raw)
To: gcc-patches
gcc/ChangeLog:
* config/i386/sse.md (cond_<code><mode>): New expander.
gcc/testsuite/ChangeLog:
* gcc.target/i386/cond_op_anylogic_d-1.c: New test.
* gcc.target/i386/cond_op_anylogic_d-2.c: New test.
* gcc.target/i386/cond_op_anylogic_q-1.c: New test.
* gcc.target/i386/cond_op_anylogic_q-2.c: New test.
---
gcc/config/i386/sse.md | 18 +++++
.../gcc.target/i386/cond_op_anylogic_d-1.c | 38 +++++++++
.../gcc.target/i386/cond_op_anylogic_d-2.c | 78 +++++++++++++++++++
.../gcc.target/i386/cond_op_anylogic_q-1.c | 10 +++
.../gcc.target/i386/cond_op_anylogic_q-2.c | 5 ++
5 files changed, 149 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 51733a3849d..a46a2373547 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -14063,6 +14063,24 @@ (define_expand "<code><mode>3"
DONE;
})
+(define_expand "cond_<code><mode>"
+ [(set (match_operand:VI48_AVX512VL 0 "register_operand")
+ (vec_merge:VI48_AVX512VL
+ (any_logic:VI48_AVX512VL
+ (match_operand:VI48_AVX512VL 2 "vector_operand")
+ (match_operand:VI48_AVX512VL 3 "vector_operand"))
+ (match_operand:VI48_AVX512VL 4 "nonimm_or_0_operand")
+ (match_operand:<avx512fmaskmode> 1 "register_operand")))]
+ "TARGET_AVX512F"
+{
+ emit_insn (gen_<code><mode>3_mask (operands[0],
+ operands[2],
+ operands[3],
+ operands[4],
+ operands[1]));
+ DONE;
+})
+
(define_insn "<mask_codefor><code><mode>3<mask_name>"
[(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,x,v")
(any_logic:VI48_AVX_AVX512F
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c
new file mode 100644
index 00000000000..8951f4a3a27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump ".COND_AND" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_XOR" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_IOR" "optimized" } } */
+/* { dg-final { scan-assembler-times "vpxord" 1 } } */
+/* { dg-final { scan-assembler-times "vpord" 1 } } */
+/* { dg-final { scan-assembler-times "vpandd" 1 } } */
+
+typedef int int32;
+typedef unsigned int uint32;
+typedef long long int64;
+typedef unsigned long long uint64;
+
+#ifndef NUM
+#define NUM 800
+#endif
+#ifndef TYPE
+#define TYPE int
+#endif
+
+TYPE a[NUM], b[NUM], c[NUM], d[NUM], e[NUM], j[NUM];
+
+#define BIN(OPNAME, OP) \
+ void \
+ __attribute__ ((noipa,optimize ("O3"))) \
+ foo_##OPNAME () \
+ { \
+ for (int i = 0; i != NUM; i++) \
+ if (b[i] < c[i]) \
+ a[i] = d[i] OP e[i]; \
+ else \
+ a[i] = d[i] - e[i]; \
+ }
+
+BIN (and, &);
+BIN (ior, |);
+BIN (xor, ^);
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c
new file mode 100644
index 00000000000..23ca4120cf2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c
@@ -0,0 +1,78 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256" } */
+/* { dg-require-effective-target avx512vl } */
+
+#define AVX512VL
+#ifndef CHECK
+#define CHECK "avx512f-helper.h"
+#endif
+
+#include CHECK
+
+#include "cond_op_anylogic_d-1.c"
+#define BINO2(OPNAME, OP) \
+ void \
+ __attribute__ ((noipa,optimize ("O2"))) \
+ foo_o2_##OPNAME () \
+ { \
+ for (int i = 0; i != NUM; i++) \
+ if (b[i] < c[i]) \
+ j[i] = d[i] OP e[i]; \
+ else \
+ j[i] = d[i] - e[i]; \
+ }
+
+BINO2 (and, &);
+BINO2 (ior, |);
+BINO2 (xor, ^);
+
+static void
+test_256 (void)
+{
+ int sign = -1;
+ for (int i = 0; i != NUM; i++)
+ {
+ a[i] = 0;
+ d[i] = i * 2;
+ e[i] = i * i * 3 - i * 9 + 153;
+ b[i] = i * 83;
+ c[i] = b[i] + sign;
+ sign *= -1;
+ j[i] = 1;
+ }
+ foo_and ();
+ foo_o2_and ();
+ for (int i = 0; i != NUM; i++)
+ {
+ if (a[i] != j[i])
+ abort ();
+ a[i] = 0;
+ b[i] = 1;
+ }
+
+ foo_xor ();
+ foo_o2_xor ();
+ for (int i = 0; i != NUM; i++)
+ {
+ if (a[i] != j[i])
+ abort ();
+ a[i] = 0;
+ j[i] = 1;
+ }
+
+ foo_ior ();
+ foo_o2_ior ();
+ for (int i = 0; i != NUM; i++)
+ {
+ if (a[i] != j[i])
+ abort ();
+ a[i] = 0;
+ j[i] = 1;
+ }
+}
+
+static void
+test_128 ()
+{
+
+}
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c
new file mode 100644
index 00000000000..cb4770113ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake-avx512 -DTYPE=int64 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump ".COND_AND" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_XOR" "optimized" } } */
+/* { dg-final { scan-tree-dump ".COND_IOR" "optimized" } } */
+/* { dg-final { scan-assembler-times "vpxorq" 1 } } */
+/* { dg-final { scan-assembler-times "vporq" 1 } } */
+/* { dg-final { scan-assembler-times "vpandq" 1 } } */
+
+#include "cond_op_anylogic_d-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c
new file mode 100644
index 00000000000..709babf271e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256 -DTYPE=int64" } */
+/* { dg-require-effective-target avx512vl } */
+
+#include "cond_op_anylogic_d-2.c"
--
2.18.1
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 0/3] [i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512
2021-08-04 12:39 [PATCH 0/3] [i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512 liuhongt
` (2 preceding siblings ...)
2021-08-04 12:39 ` [PATCH 3/3] [i386] Support cond_{xor, ior, and} for vector integer mode " liuhongt
@ 2021-08-04 12:48 ` Hongtao Liu
3 siblings, 0 replies; 5+ messages in thread
From: Hongtao Liu @ 2021-08-04 12:48 UTC (permalink / raw)
To: liuhongt; +Cc: GCC Patches
On Wed, Aug 4, 2021 at 8:39 PM liuhongt <hongtao.liu@intel.com> wrote:
>
> Hi:
> Together with the previous 3 patches, all cond_op expanders of vector
> modes are supported (if they have a corresponding avx512 mask instruction).
Oh, after double check, I realize there're still shift instructions
left, will support in another patch,
OPTAB_D (cond_ashl_optab, "cond_ashl$a")
OPTAB_D (cond_ashr_optab, "cond_ashr$a")
OPTAB_D (cond_lshr_optab, "cond_lshr$a")
>
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
>
> liuhongt (3):
> [i386] Support cond_{smax,smin,umax,umin} for vector integer modes
> under AVX512.
> [i386] Support cond_{smax,smin} for vector float/double modes under
> AVX512.
> [i386] Support cond_{xor,ior,and} for vector integer mode under
> AVX512.
>
> gcc/config/i386/sse.md | 54 +++++++++++++
> .../gcc.target/i386/cond_op_anylogic_d-1.c | 38 +++++++++
> .../gcc.target/i386/cond_op_anylogic_d-2.c | 78 +++++++++++++++++++
> .../gcc.target/i386/cond_op_anylogic_q-1.c | 10 +++
> .../gcc.target/i386/cond_op_anylogic_q-2.c | 5 ++
> .../gcc.target/i386/cond_op_maxmin_b-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_b-2.c | 6 ++
> .../gcc.target/i386/cond_op_maxmin_d-1.c | 41 ++++++++++
> .../gcc.target/i386/cond_op_maxmin_d-2.c | 67 ++++++++++++++++
> .../gcc.target/i386/cond_op_maxmin_double-1.c | 39 ++++++++++
> .../gcc.target/i386/cond_op_maxmin_double-2.c | 67 ++++++++++++++++
> .../gcc.target/i386/cond_op_maxmin_float-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_float-2.c | 5 ++
> .../gcc.target/i386/cond_op_maxmin_q-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_q-2.c | 5 ++
> .../gcc.target/i386/cond_op_maxmin_ub-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_ub-2.c | 6 ++
> .../gcc.target/i386/cond_op_maxmin_ud-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_ud-2.c | 5 ++
> .../gcc.target/i386/cond_op_maxmin_uq-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_uq-2.c | 5 ++
> .../gcc.target/i386/cond_op_maxmin_uw-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_uw-2.c | 6 ++
> .../gcc.target/i386/cond_op_maxmin_w-1.c | 8 ++
> .../gcc.target/i386/cond_op_maxmin_w-2.c | 6 ++
> 25 files changed, 507 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-2.c
>
> --
> 2.18.1
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 5+ messages in thread