From: Hongtao Liu <crazylht@gmail.com>
To: Uros Bizjak <ubizjak@gmail.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
Richard Biener <richard.guenther@gmail.com>
Subject: Re: [PATCH] [PR target/97194] [AVX2] Support variable index vec_set.
Date: Thu, 12 Nov 2020 17:25:24 +0800 [thread overview]
Message-ID: <CAMZc-bwi5pKPhXou-xt56ug54ZT+XNaXiVarWnvTOFbRVsBv2Q@mail.gmail.com> (raw)
In-Reply-To: <CAMZc-byFfm4HqPOTA5qgS32MLy6S4T4r7Gq+MxXezJsRxXpO1A@mail.gmail.com>
On Thu, Nov 12, 2020 at 5:15 PM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Thu, Nov 12, 2020 at 5:12 PM Hongtao Liu <crazylht@gmail.com> wrote:
> >
> > On Thu, Nov 12, 2020 at 4:21 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > >
> > > On Thu, Nov 12, 2020 at 3:04 AM Hongtao Liu <crazylht@gmail.com> wrote:
> > >
> > > > > > gcc/ChangeLog:
> > > > > >
> > > > > > PR target/97194
> > > > > > * config/i386/i386-expand.c (ix86_expand_vector_set_var): New function.
> > > > > > * config/i386/i386-protos.h (ix86_expand_vector_set_var): New Decl.
> > > > > > * config/i386/predicates.md (vec_setm_operand): New predicate,
> > > > > > true for const_int_operand or register_operand under TARGET_AVX2.
> > > > > > * config/i386/sse.md (vec_set<mode>): Support both constant
> > > > > > and variable index vec_set.
> > > > > >
> > > > > > gcc/testsuite/ChangeLog:
> > > > > >
> > > > > > * gcc.target/i386/avx2-vec-set-1.c: New test.
> > > > > > * gcc.target/i386/avx2-vec-set-2.c: New test.
> > > > > > * gcc.target/i386/avx512bw-vec-set-1.c: New test.
> > > > > > * gcc.target/i386/avx512bw-vec-set-2.c: New test.
> > > > > > * gcc.target/i386/avx512f-vec-set-2.c: New test.
> > > > > > * gcc.target/i386/avx512vl-vec-set-2.c: New test.
> > > > >
> > > > > +;; True for registers, or const_int_operand, used to vec_setm expander.
> > > > > +(define_predicate "vec_setm_operand"
> > > > > + (ior (and (match_operand 0 "register_operand")
> > > > > + (match_test "TARGET_AVX2"))
> > > > > + (match_code "const_int")))
> > > > > +
> > > > > ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
> > > > > (define_predicate "reg_or_pm1_operand"
> > > > > (ior (match_operand 0 "register_operand")
> > > > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> > > > > index b153a87fb98..1798e5dea75 100644
> > > > > --- a/gcc/config/i386/sse.md
> > > > > +++ b/gcc/config/i386/sse.md
> > > > > @@ -8098,11 +8098,14 @@ (define_insn "vec_setv2df_0"
> > > > > (define_expand "vec_set<mode>"
> > > > > [(match_operand:V 0 "register_operand")
> > > > > (match_operand:<ssescalarmode> 1 "register_operand")
> > > > > - (match_operand 2 "const_int_operand")]
> > > > > + (match_operand 2 "vec_setm_operand")]
> > > > >
> > > > > You need to specify a mode, otherwise a register of any mode can pass here.
> > > > >
> > > > Yes, theoretically, we only accept integer types. But in can_vec_set_var_idx_p
> > > > cut
> > > > ---
> > > > bool
> > > > can_vec_set_var_idx_p (machine_mode vec_mode)
> > > > {
> > > > if (!VECTOR_MODE_P (vec_mode))
> > > > return false;
> > > >
> > > > machine_mode inner_mode = GET_MODE_INNER (vec_mode);
> > > > rtx reg1 = alloca_raw_REG (vec_mode, LAST_VIRTUAL_REGISTER + 1);
> > > > rtx reg2 = alloca_raw_REG (inner_mode, LAST_VIRTUAL_REGISTER + 2);
> > > > rtx reg3 = alloca_raw_REG (VOIDmode, LAST_VIRTUAL_REGISTER + 3);
> > > >
> > > > enum insn_code icode = optab_handler (vec_set_optab, vec_mode);
> > > >
> > > > return icode != CODE_FOR_nothing && insn_operand_matches (icode, 0, reg1)
> > > > && insn_operand_matches (icode, 1, reg2)
> > > > && insn_operand_matches (icode, 2, reg3);
> > > > }
> > > > ---
> > > >
> > > > reg3 is assumed to be VOIDmode, set anymode in match_operand 2 will
> > > > fail insn_operand_matches (icode, 2, reg3)
> > > > ---
> > > > (gdb) p insn_operand_matches(icode,2,reg3)
> > > > $5 = false
> > > > (gdb)
> > > > ---
> > > >
> > > > Maybe we need to change
> > > >
> > > > rtx reg3 = alloca_raw_REG (VOIDmode, LAST_VIRTUAL_REGISTER + 3);
> > > >
> > > > to
> > > >
> > > > rtx reg3 = alloca_raw_REG (SImode, LAST_VIRTUAL_REGISTER + 3);
> > > >
> > > > cc Richard Biener, any thoughts?
> > >
> > > There are two targets (gcn in gcn-valu.md and s390 in vector.md) that
> > > specify SImode for operand 2 in vec_setM pattern and allow register
> > > operands. I wonder if and how they manage to generate the pattern.
> > >
> > > Uros.
> >
> > Variable index vec_set is enabled by r11-3486, about two months ago in
> > [1]. But for the upper two targets, the codes are already there since
> > GCC10(maybe earlier, i just looked at gcc10 branch), I don't think
> > those codes are for [1].
> >
> > [1] https://gcc.gnu.org/pipermail/gcc-patches/2020-October/555905.html
> >
> >
> > --
> > BR,
> > Hongtao
>
> Correct [1] https://gcc.gnu.org/pipermail/gcc-patches/2020-September/554240.html
>
> --
> BR,
> Hongtao
in https://gcc.gnu.org/pipermail/gcc-patches/2020-September/554592.html
It says
> >> +can_vec_set_var_idx_p (enum tree_code code, machine_mode vec_mode,
> >> + machine_mode value_mode, machine_mode idx_mode)
> >
> > toplevel comment missing
> >
> >> +{
> >> + gcc_assert (code == VECTOR_TYPE);
> >
> > what's the point of pasing 'code' here then? Since the optab only has a single
> > mode, the vector mode, the value_mode is redundant as well. And I guess
> > we might want to handle "arbitrary" index modes? That is, the .md expanders
> > should not restrict its mode - I guess it simply uses VOIDmode at the moment
> > (for integer constants). Not sure how to best do this without an explicit mode
> > in the optab ...
>
> Yes, removed 'code' and value_mode by checking VECTOR_MODE_P and use GET_MODE_INNER
> for value_mode. ".md expanders" shall support for integer constants index mode, but
> I guess they shouldn't be expanded by IFN as this function is for variable index
> insert only? Anyway, the v3 patch used VOIDmode check...
--
BR,
Hongtao
next prev parent reply other threads:[~2020-11-12 9:23 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-11 8:45 Uros Bizjak
2020-11-12 2:06 ` Hongtao Liu
2020-11-12 8:20 ` Uros Bizjak
2020-11-12 9:12 ` Hongtao Liu
2020-11-12 9:15 ` Hongtao Liu
2020-11-12 9:25 ` Hongtao Liu [this message]
2020-11-12 13:59 ` Richard Biener
2020-11-12 17:51 ` Uros Bizjak
2020-11-12 18:26 ` Uros Bizjak
2020-11-12 18:34 ` Uros Bizjak
2020-11-16 11:57 ` Uros Bizjak
2020-11-19 10:54 ` Richard Sandiford
2020-11-16 10:16 ` Uros Bizjak
-- strict thread matches above, loose matches on Subject: below --
2020-10-19 8:23 Hongtao Liu
2020-10-19 9:07 ` Richard Biener
2020-10-19 9:39 ` Hongtao Liu
2020-10-19 9:55 ` Richard Biener
2020-10-20 2:37 ` Hongtao Liu
2020-10-20 7:36 ` Richard Biener
2020-10-27 7:51 ` Hongtao Liu
2020-11-11 8:03 ` Hongtao Liu
2020-11-25 19:15 ` Jeff Law
2020-11-26 1:45 ` Hongtao Liu
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