From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112d.google.com (mail-yw1-x112d.google.com [IPv6:2607:f8b0:4864:20::112d]) by sourceware.org (Postfix) with ESMTPS id 477673954C63 for ; Wed, 16 Nov 2022 06:40:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 477673954C63 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x112d.google.com with SMTP id 00721157ae682-367cd2807f2so159117527b3.1 for ; Tue, 15 Nov 2022 22:40:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Nd/u6tuiYKDoHPibNKPOfV1Svra1ceHVaAtD3tgzOjg=; b=qPm1w9AKskbFQoP/k157i2Gxei/q5YglBo3x/HYerCzaLAHNwLNRvEBm84Q3//lvbT tGBuLeQkx/mZxo9vd1pUpgnfW4h/JIQaUwl6no7eqBicKaUCpzujPvNHjK6OZJe2urpt VYWX+iTcuC/XpugvJGiHWYFenGb2FZTLazVjvPKrQr8LMBWvHBUfuhYKPF9+uHMRROQr YoVZtn22sKTNyyXCg8yfqvP+OVh8NZbWty2Rq+DKe8GyzRzrXa5oGmkspxvh6QTtVz26 Zt3WA9MXCpjL4JTwVoXl+q8cP/u8K92xhR8HZRJy1QPzCvK8S1up8q/jjg7KawnLihLz eWHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Nd/u6tuiYKDoHPibNKPOfV1Svra1ceHVaAtD3tgzOjg=; b=NH/elXc4lwg+wVqOvTrlt1F7BM5McviMn2OI2qSDRP5PWXqwwxRrbCTbeKI/CQHCNv nF/pS1Yn2yFHXX8oE0P+qUr8gaho1Vj76l9cZBkakFvsQlMsoQ9+Fl2KHQBvHWvex1q4 mJhpnNx57f700y2cGWDOOh8Vbpuo+DfVca3ySTHrwRc2N+h6gI5z+bQit4L62ScUWjp4 LhiU8GhgyEqxFXcsdAt7iOeYNIUJzHUMPvJGkWb7zwbfbasgH/8Zsl/FpjvPo6m3C1F8 BMN4m5vPXFaJ7YR3AO6STl/MoLD2sWAXiK+QaXMp+oBypTG23yMXJ57jL36m4MRDsd3Z j8/A== X-Gm-Message-State: ANoB5plAFtZV8dcyggSwjXs1d1LWseph816axc31uqoZepZHKc2ZRoEv I0n509SlJIrVqKkf5F7v/poV6cgaDFTyMvMtRBM= X-Google-Smtp-Source: AA0mqf4ZYqyLaa1vcF/MSqIhTfpFu8tiotIPCKja3czUodBS6zT7zsYAaAt35VpyN8LgiWv/7eFrUgiZAU2w8L6IIDQ= X-Received: by 2002:a0d:ccd6:0:b0:368:4707:a61a with SMTP id o205-20020a0dccd6000000b003684707a61amr21250890ywd.344.1668580838394; Tue, 15 Nov 2022 22:40:38 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Hongtao Liu Date: Wed, 16 Nov 2022 14:40:27 +0800 Message-ID: Subject: Re: [PATCH][i386]: Update ix86_can_change_mode_class target hook to accept QImode conversions To: Tamar Christina Cc: gcc-patches@gcc.gnu.org, nd@arm.com, hubicka@ucw.cz, ubizjak@gmail.com, kirill.yukhin@gmail.com, hongtao.liu@intel.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Nov 14, 2022 at 10:14 AM Hongtao Liu wrote: > > On Fri, Nov 11, 2022 at 10:47 PM Tamar Christina via Gcc-patches > wrote: > > > > Hi All, > > > > The current i386 implementation of the TARGET_CAN_CHANGE_MODE_CLASS is currently > > not useful before re-alloc. > > > > In particular before regalloc optimization passes query the hook using ALL_REGS, > > but because of the > > > > if (MAYBE_FLOAT_CLASS_P (regclass)) > > return false; > > > > The hook returns false for all modes, even integer ones because ALL_REGS > > overlaps with floating point regs. > > > > The vector permute fallback cases used to unconditionally convert vector integer > > permutes to vector QImode ones as a fallback plan. This is incorrect and can > > result in incorrect code if the target doesn't support this conversion. > > > > To fix this some more checks were added, however that ended up introducing ICEs > > in the i386 backend because e.g. the hook would reject conversions between modes > > like V2TImode and V32QImode. > > > > My understanding is that for x87 we don't want to allow floating point > > conversions, but integers are fine. So I have modified the check such that it > > also checks the modes, not just the register class groups. > > > > The second part of the code is needed because now that integer modes aren't > > uniformly rejected the i386 backend trigger further optimizations. However the > > backend lacks instructions to deal with canonical RTL representations of > > certain instructions. for instance the back-end seems to prefer vec_select 0 > > instead of subregs. > > > > So to prevent the canonicalization I reject integer modes when the sizes of to This should not be right, we still want something like (subreg:SI (reg:V4SI)) > > and from don't match and when we would have exited with false previously. > > > > This fixes all the ICEs and codegen regressions, but perhaps an x86 maintainer > > should take a deeper look at this hook implementation. > > > > Bootstrapped Regtested on x86_64-pc-linux-gnu and no issues. > > > > Ok for master? > > > > Thanks, > > Tamar > > > > gcc/ChangeLog: > > > > * config/i386/i386.cc (ix86_can_change_mode_class): Update the target > > hook. > > > > --- inline copy of patch -- > > diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc > > index c4d0e36e9c0a2256f5dde1f4dc021c0328aa0cba..477dd007ea80272680751b61e35cc3eec79b66c3 100644 > > --- a/gcc/config/i386/i386.cc > > +++ b/gcc/config/i386/i386.cc > > @@ -19682,7 +19682,15 @@ ix86_can_change_mode_class (machine_mode from, machine_mode to, > > > > /* x87 registers can't do subreg at all, as all values are reformatted > > to extended precision. */ > > - if (MAYBE_FLOAT_CLASS_P (regclass)) > > + if (MAYBE_FLOAT_CLASS_P (regclass) > > + && VALID_FP_MODE_P (from) > > + && VALID_FP_MODE_P (to)) > > + return false; > This change looks reasonable since only VALID_FP_MODE_P will be > allocated to FLOAT_CLASS. > > + > > + /* Reject integer modes if the sizes aren't the same. It would have > > + normally exited above. */ > > + if (MAYBE_FLOAT_CLASS_P (regclass) > > + && GET_MODE_SIZE (from) != GET_MODE_SIZE (to)) > > return false; > Do you have a case(or a patch so I can reproduce the regression > myself) to indicate the regression, so I can have a deep look. This is not right, we still want something like (subreg:SI (reg:V4SI)). I'm trying to adjust all those vec_select to subregs, and it may take some time. We also need to adjust modes_tieable_p to prevent high rtx_cost for subreg which will prevent insns being combined. x86 is conservative on both can_change_mode_class and modes_tieable_p. I'm a bit worried that these changes are a bit big for stage3, let me try it first. > > > > if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass)) > > > > > > > > > > -- > > > > -- > BR, > Hongtao -- BR, Hongtao