* [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F and TARGET_SSE_MATH.
@ 2021-08-10 12:13 liuhongt
2021-08-11 6:36 ` Uros Bizjak
0 siblings, 1 reply; 7+ messages in thread
From: liuhongt @ 2021-08-10 12:13 UTC (permalink / raw)
To: gcc-patches
Hi:
AVX512F supported vscalefs{s,d} which is the same as ldexp except the second operand should be floating point.
Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
gcc/ChangeLog:
PR target/98309
* config/i386/i386.md (ldexp<mode>3): Extend to vscalefs[sd]
when TARGET_AVX512F and TARGET_SSE_MATH.
gcc/testsuite/ChangeLog:
PR target/98309
* gcc.target/i386/pr98309-1.c: New test.
* gcc.target/i386/pr98309-2.c: New test.
---
gcc/config/i386/i386.md | 34 +++++++++++++++-----
gcc/testsuite/gcc.target/i386/pr98309-1.c | 18 +++++++++++
gcc/testsuite/gcc.target/i386/pr98309-2.c | 39 +++++++++++++++++++++++
3 files changed, 83 insertions(+), 8 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr98309-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr98309-2.c
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index bc1c30b77f4..56b09c566ed 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -17914,17 +17914,35 @@ (define_expand "ldexp<mode>3"
[(use (match_operand:MODEF 0 "register_operand"))
(use (match_operand:MODEF 1 "general_operand"))
(use (match_operand:SI 2 "register_operand"))]
- "TARGET_USE_FANCY_MATH_387
- && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || TARGET_MIX_SSE_I387)
+ "((TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387))
+ || (TARGET_AVX512F && TARGET_SSE_MATH))
&& flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ /* Prefer avx512f version. */
+ if (TARGET_AVX512F && TARGET_SSE_MATH)
+ {
+ rtx op2 = gen_reg_rtx (<MODE>mode);
+ emit_insn (gen_floatsi<mode>2 (op2, operands[2]));
+ operands[0] = lowpart_subreg (<ssevecmodef>mode, operands[0], <MODE>mode);
+ if (MEM_P (operands[1]))
+ operands[1] = force_reg (<MODE>mode, operands[1]);
+ operands[1] = lowpart_subreg (<ssevecmodef>mode, operands[1], <MODE>mode);
+ op2 = lowpart_subreg (<ssevecmodef>mode, op2, <MODE>mode);
+ emit_insn (gen_avx512f_vmscalef<ssevecmodelower> (operands[0],
+ operands[1],
+ op2));
+ }
+ else
+ {
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
- emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
- emit_insn (gen_ldexpxf3 (op0, op1, operands[2]));
- emit_insn (gen_truncxf<mode>2 (operands[0], op0));
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_ldexpxf3 (op0, op1, operands[2]));
+ emit_insn (gen_truncxf<mode>2 (operands[0], op0));
+ }
DONE;
})
diff --git a/gcc/testsuite/gcc.target/i386/pr98309-1.c b/gcc/testsuite/gcc.target/i386/pr98309-1.c
new file mode 100644
index 00000000000..3a7afb58971
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr98309-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2 -mfpmath=sse -ffast-math" } */
+/* { dg-final { scan-assembler-times "vcvtsi2s\[sd\]" "2" } } */
+/* { dg-final { scan-assembler-times "vscalefs\[sd\]" "2" } } */
+
+double
+__attribute__((noipa))
+foo (double a, int b)
+{
+ return __builtin_ldexp (a, b);
+}
+
+float
+__attribute__((noipa))
+foo2 (float a, int b)
+{
+ return __builtin_ldexpf (a, b);
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr98309-2.c b/gcc/testsuite/gcc.target/i386/pr98309-2.c
new file mode 100644
index 00000000000..ecfb9168b7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr98309-2.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2 -mfpmath=sse -ffast-math" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+#ifndef CHECK
+#define CHECK "avx512f-helper.h"
+#endif
+
+#include CHECK
+
+#include "pr98309-1.c"
+
+double
+__attribute__((noipa, target("fpmath=387")))
+foo_i387 (double a, int b)
+{
+ return __builtin_ldexp (a, b);
+}
+
+float
+__attribute__((noipa, target("fpmath=387")))
+foo2_i387 (float a, int b)
+{
+ return __builtin_ldexpf (a, b);
+}
+
+static void
+test_512 (void)
+{
+ float fa = 14.5;
+ double da = 44.5;
+ int fb = 12;
+ int db = 8;
+ if (foo_i387 (da, db) != foo (da, db))
+ abort ();
+ if (foo2_i387 (fa, fb) != foo2 (fa, fb))
+ abort ();
+}
--
2.27.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F and TARGET_SSE_MATH.
2021-08-10 12:13 [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F and TARGET_SSE_MATH liuhongt
@ 2021-08-11 6:36 ` Uros Bizjak
2021-08-11 11:16 ` Uros Bizjak
0 siblings, 1 reply; 7+ messages in thread
From: Uros Bizjak @ 2021-08-11 6:36 UTC (permalink / raw)
To: liuhongt; +Cc: gcc-patches, Hongtao Liu
On Tue, Aug 10, 2021 at 2:13 PM liuhongt <hongtao.liu@intel.com> wrote:
>
> Hi:
> AVX512F supported vscalefs{s,d} which is the same as ldexp except the second operand should be floating point.
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
>
> gcc/ChangeLog:
>
> PR target/98309
> * config/i386/i386.md (ldexp<mode>3): Extend to vscalefs[sd]
> when TARGET_AVX512F and TARGET_SSE_MATH.
>
> gcc/testsuite/ChangeLog:
>
> PR target/98309
> * gcc.target/i386/pr98309-1.c: New test.
> * gcc.target/i386/pr98309-2.c: New test.
OK.
Thanks,
Uros.
> ---
> gcc/config/i386/i386.md | 34 +++++++++++++++-----
> gcc/testsuite/gcc.target/i386/pr98309-1.c | 18 +++++++++++
> gcc/testsuite/gcc.target/i386/pr98309-2.c | 39 +++++++++++++++++++++++
> 3 files changed, 83 insertions(+), 8 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr98309-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/pr98309-2.c
>
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index bc1c30b77f4..56b09c566ed 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -17914,17 +17914,35 @@ (define_expand "ldexp<mode>3"
> [(use (match_operand:MODEF 0 "register_operand"))
> (use (match_operand:MODEF 1 "general_operand"))
> (use (match_operand:SI 2 "register_operand"))]
> - "TARGET_USE_FANCY_MATH_387
> - && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
> - || TARGET_MIX_SSE_I387)
> + "((TARGET_USE_FANCY_MATH_387
> + && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
> + || TARGET_MIX_SSE_I387))
> + || (TARGET_AVX512F && TARGET_SSE_MATH))
> && flag_unsafe_math_optimizations"
> {
> - rtx op0 = gen_reg_rtx (XFmode);
> - rtx op1 = gen_reg_rtx (XFmode);
> + /* Prefer avx512f version. */
> + if (TARGET_AVX512F && TARGET_SSE_MATH)
> + {
> + rtx op2 = gen_reg_rtx (<MODE>mode);
> + emit_insn (gen_floatsi<mode>2 (op2, operands[2]));
> + operands[0] = lowpart_subreg (<ssevecmodef>mode, operands[0], <MODE>mode);
> + if (MEM_P (operands[1]))
> + operands[1] = force_reg (<MODE>mode, operands[1]);
> + operands[1] = lowpart_subreg (<ssevecmodef>mode, operands[1], <MODE>mode);
> + op2 = lowpart_subreg (<ssevecmodef>mode, op2, <MODE>mode);
> + emit_insn (gen_avx512f_vmscalef<ssevecmodelower> (operands[0],
> + operands[1],
> + op2));
> + }
> + else
> + {
> + rtx op0 = gen_reg_rtx (XFmode);
> + rtx op1 = gen_reg_rtx (XFmode);
>
> - emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
> - emit_insn (gen_ldexpxf3 (op0, op1, operands[2]));
> - emit_insn (gen_truncxf<mode>2 (operands[0], op0));
> + emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
> + emit_insn (gen_ldexpxf3 (op0, op1, operands[2]));
> + emit_insn (gen_truncxf<mode>2 (operands[0], op0));
> + }
> DONE;
> })
>
> diff --git a/gcc/testsuite/gcc.target/i386/pr98309-1.c b/gcc/testsuite/gcc.target/i386/pr98309-1.c
> new file mode 100644
> index 00000000000..3a7afb58971
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr98309-1.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2 -mfpmath=sse -ffast-math" } */
> +/* { dg-final { scan-assembler-times "vcvtsi2s\[sd\]" "2" } } */
> +/* { dg-final { scan-assembler-times "vscalefs\[sd\]" "2" } } */
> +
> +double
> +__attribute__((noipa))
> +foo (double a, int b)
> +{
> + return __builtin_ldexp (a, b);
> +}
> +
> +float
> +__attribute__((noipa))
> +foo2 (float a, int b)
> +{
> + return __builtin_ldexpf (a, b);
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/pr98309-2.c b/gcc/testsuite/gcc.target/i386/pr98309-2.c
> new file mode 100644
> index 00000000000..ecfb9168b7d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr98309-2.c
> @@ -0,0 +1,39 @@
> +/* { dg-do run } */
> +/* { dg-options "-mavx512f -O2 -mfpmath=sse -ffast-math" } */
> +/* { dg-require-effective-target avx512f } */
> +
> +#define AVX512F
> +#ifndef CHECK
> +#define CHECK "avx512f-helper.h"
> +#endif
> +
> +#include CHECK
> +
> +#include "pr98309-1.c"
> +
> +double
> +__attribute__((noipa, target("fpmath=387")))
> +foo_i387 (double a, int b)
> +{
> + return __builtin_ldexp (a, b);
> +}
> +
> +float
> +__attribute__((noipa, target("fpmath=387")))
> +foo2_i387 (float a, int b)
> +{
> + return __builtin_ldexpf (a, b);
> +}
> +
> +static void
> +test_512 (void)
> +{
> + float fa = 14.5;
> + double da = 44.5;
> + int fb = 12;
> + int db = 8;
> + if (foo_i387 (da, db) != foo (da, db))
> + abort ();
> + if (foo2_i387 (fa, fb) != foo2 (fa, fb))
> + abort ();
> +}
> --
> 2.27.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F and TARGET_SSE_MATH.
2021-08-11 6:36 ` Uros Bizjak
@ 2021-08-11 11:16 ` Uros Bizjak
2021-08-12 4:05 ` [PATCH] [i386] Introduce a scalar version of avx512f_vmscalef and adjust ldexp<mode>3 for it liuhongt
2021-08-12 4:46 ` [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F and TARGET_SSE_MATH Hongtao Liu
0 siblings, 2 replies; 7+ messages in thread
From: Uros Bizjak @ 2021-08-11 11:16 UTC (permalink / raw)
To: liuhongt; +Cc: gcc-patches, Hongtao Liu
[-- Attachment #1: Type: text/plain, Size: 934 bytes --]
On Wed, Aug 11, 2021 at 8:36 AM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> On Tue, Aug 10, 2021 at 2:13 PM liuhongt <hongtao.liu@intel.com> wrote:
> >
> > Hi:
> > AVX512F supported vscalefs{s,d} which is the same as ldexp except the second operand should be floating point.
> > Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
> >
> > gcc/ChangeLog:
> >
> > PR target/98309
> > * config/i386/i386.md (ldexp<mode>3): Extend to vscalefs[sd]
> > when TARGET_AVX512F and TARGET_SSE_MATH.
> >
> > gcc/testsuite/ChangeLog:
> >
> > PR target/98309
> > * gcc.target/i386/pr98309-1.c: New test.
> > * gcc.target/i386/pr98309-2.c: New test.
>
> OK.
Actually, we should introduce a scalar version of avx512f_vmscalef, so
we can avoid all subreg conversions with the vector-merge (VM)
version, and will also allow memory in operand 2.
Please test the attached incremental patch.
Uros.
[-- Attachment #2: p.diff.txt --]
[-- Type: text/plain, Size: 1986 bytes --]
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 56b09c566ed..4a8e8fea290 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -125,6 +125,9 @@
UNSPEC_RSQRT
UNSPEC_PSADBW
+ ;; For AVX512F support
+ UNSPEC_SCALEF
+
;; Generic math support
UNSPEC_COPYSIGN
UNSPEC_XORSIGN
@@ -17894,6 +17897,17 @@
DONE;
})
+(define_insn "avx512f_scalef<mode>2"
+ [(set (match_operand:MODEF 0 "register_operand" "=v")
+ (unspec:MODEF
+ [(match_operand:MODEF 1 "register_operand" "v")
+ (match_operand:MODEF 2 "nonimmediate_operand" "vm")]
+ UNSPEC_SCALEF))]
+ "TARGET_AVX512F"
+ "vscalef<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<MODE>")])
+
(define_expand "ldexpxf3"
[(match_operand:XF 0 "register_operand")
(match_operand:XF 1 "register_operand")
@@ -17924,15 +17938,12 @@
if (TARGET_AVX512F && TARGET_SSE_MATH)
{
rtx op2 = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_floatsi<mode>2 (op2, operands[2]));
- operands[0] = lowpart_subreg (<ssevecmodef>mode, operands[0], <MODE>mode);
- if (MEM_P (operands[1]))
+
+ if (!nonimmediate_operand (operands[1], <MODE>mode))
operands[1] = force_reg (<MODE>mode, operands[1]);
- operands[1] = lowpart_subreg (<ssevecmodef>mode, operands[1], <MODE>mode);
- op2 = lowpart_subreg (<ssevecmodef>mode, op2, <MODE>mode);
- emit_insn (gen_avx512f_vmscalef<ssevecmodelower> (operands[0],
- operands[1],
- op2));
+
+ emit_insn (gen_floatsi<mode>2 (op2, operands[2]));
+ emit_insn (gen_avx512f_scalef<mode>2 (operands[0], operands[1], op2));
}
else
{
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 3957c86c3df..9233dfc6150 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -92,7 +92,6 @@
UNSPEC_RCP14
UNSPEC_RSQRT14
UNSPEC_FIXUPIMM
- UNSPEC_SCALEF
UNSPEC_VTERNLOG
UNSPEC_GETEXP
UNSPEC_GETMANT
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] [i386] Introduce a scalar version of avx512f_vmscalef and adjust ldexp<mode>3 for it.
2021-08-11 11:16 ` Uros Bizjak
@ 2021-08-12 4:05 ` liuhongt
2021-08-12 4:47 ` Hongtao Liu
2021-08-12 4:46 ` [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F and TARGET_SSE_MATH Hongtao Liu
1 sibling, 1 reply; 7+ messages in thread
From: liuhongt @ 2021-08-12 4:05 UTC (permalink / raw)
To: gcc-patches
Hi:
This is the patch i'm going to checkin.
Bootstrapped and regtested on x86_64-linux-gnu{-m32,};
2021-08-12 Uros Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/98309
* config/i386/i386.md (avx512f_scalef<mode>2): New
define_insn.
(ldexp<mode>3): Adjust for new define_insn.
(UNSPEC_SCALEF): Move from sse.md.
* config/i386/sse.md (UNSPEC_SCALEF): Move to i386.md.
---
gcc/config/i386/i386.md | 27 +++++++++++++++++++--------
gcc/config/i386/sse.md | 1 -
2 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 56b09c566ed..4a8e8fea290 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -125,6 +125,9 @@ (define_c_enum "unspec" [
UNSPEC_RSQRT
UNSPEC_PSADBW
+ ;; For AVX512F support
+ UNSPEC_SCALEF
+
;; Generic math support
UNSPEC_COPYSIGN
UNSPEC_XORSIGN
@@ -17894,6 +17897,17 @@ (define_expand "expm1<mode>2"
DONE;
})
+(define_insn "avx512f_scalef<mode>2"
+ [(set (match_operand:MODEF 0 "register_operand" "=v")
+ (unspec:MODEF
+ [(match_operand:MODEF 1 "register_operand" "v")
+ (match_operand:MODEF 2 "nonimmediate_operand" "vm")]
+ UNSPEC_SCALEF))]
+ "TARGET_AVX512F"
+ "vscalef<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<MODE>")])
+
(define_expand "ldexpxf3"
[(match_operand:XF 0 "register_operand")
(match_operand:XF 1 "register_operand")
@@ -17924,15 +17938,12 @@ (define_expand "ldexp<mode>3"
if (TARGET_AVX512F && TARGET_SSE_MATH)
{
rtx op2 = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_floatsi<mode>2 (op2, operands[2]));
- operands[0] = lowpart_subreg (<ssevecmodef>mode, operands[0], <MODE>mode);
- if (MEM_P (operands[1]))
+
+ if (!nonimmediate_operand (operands[1], <MODE>mode))
operands[1] = force_reg (<MODE>mode, operands[1]);
- operands[1] = lowpart_subreg (<ssevecmodef>mode, operands[1], <MODE>mode);
- op2 = lowpart_subreg (<ssevecmodef>mode, op2, <MODE>mode);
- emit_insn (gen_avx512f_vmscalef<ssevecmodelower> (operands[0],
- operands[1],
- op2));
+
+ emit_insn (gen_floatsi<mode>2 (op2, operands[2]));
+ emit_insn (gen_avx512f_scalef<mode>2 (operands[0], operands[1], op2));
}
else
{
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 3957c86c3df..9233dfc6150 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -92,7 +92,6 @@ (define_c_enum "unspec" [
UNSPEC_RCP14
UNSPEC_RSQRT14
UNSPEC_FIXUPIMM
- UNSPEC_SCALEF
UNSPEC_VTERNLOG
UNSPEC_GETEXP
UNSPEC_GETMANT
--
2.18.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F and TARGET_SSE_MATH.
2021-08-11 11:16 ` Uros Bizjak
2021-08-12 4:05 ` [PATCH] [i386] Introduce a scalar version of avx512f_vmscalef and adjust ldexp<mode>3 for it liuhongt
@ 2021-08-12 4:46 ` Hongtao Liu
2021-08-12 19:21 ` Uros Bizjak
1 sibling, 1 reply; 7+ messages in thread
From: Hongtao Liu @ 2021-08-12 4:46 UTC (permalink / raw)
To: Uros Bizjak; +Cc: liuhongt, gcc-patches
On Wed, Aug 11, 2021 at 7:16 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> On Wed, Aug 11, 2021 at 8:36 AM Uros Bizjak <ubizjak@gmail.com> wrote:
> >
> > On Tue, Aug 10, 2021 at 2:13 PM liuhongt <hongtao.liu@intel.com> wrote:
> > >
> > > Hi:
> > > AVX512F supported vscalefs{s,d} which is the same as ldexp except the second operand should be floating point.
> > > Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
> > >
> > > gcc/ChangeLog:
> > >
> > > PR target/98309
> > > * config/i386/i386.md (ldexp<mode>3): Extend to vscalefs[sd]
> > > when TARGET_AVX512F and TARGET_SSE_MATH.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > PR target/98309
> > > * gcc.target/i386/pr98309-1.c: New test.
> > > * gcc.target/i386/pr98309-2.c: New test.
> >
> > OK.
>
> Actually, we should introduce a scalar version of avx512f_vmscalef, so
> we can avoid all subreg conversions with the vector-merge (VM)
> version, and will also allow memory in operand 2.
>
> Please test the attached incremental patch.
>
Bootstrapped and regtested on x86_64-linux-gnu{-m32,} on CLX.
tests is fine.
> Uros.
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] [i386] Introduce a scalar version of avx512f_vmscalef and adjust ldexp<mode>3 for it.
2021-08-12 4:05 ` [PATCH] [i386] Introduce a scalar version of avx512f_vmscalef and adjust ldexp<mode>3 for it liuhongt
@ 2021-08-12 4:47 ` Hongtao Liu
0 siblings, 0 replies; 7+ messages in thread
From: Hongtao Liu @ 2021-08-12 4:47 UTC (permalink / raw)
To: liuhongt; +Cc: GCC Patches, Uros Bizjak
On Thu, Aug 12, 2021 at 12:05 PM liuhongt <hongtao.liu@intel.com> wrote:
>
> Hi:
> This is the patch i'm going to checkin.
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,};
>
>
> 2021-08-12 Uros Bizjak <ubizjak@gmail.com>
>
> gcc/ChangeLog:
>
> PR target/98309
> * config/i386/i386.md (avx512f_scalef<mode>2): New
> define_insn.
> (ldexp<mode>3): Adjust for new define_insn.
> (UNSPEC_SCALEF): Move from sse.md.
> * config/i386/sse.md (UNSPEC_SCALEF): Move to i386.md.
> ---
> gcc/config/i386/i386.md | 27 +++++++++++++++++++--------
> gcc/config/i386/sse.md | 1 -
> 2 files changed, 19 insertions(+), 9 deletions(-)
>
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index 56b09c566ed..4a8e8fea290 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -125,6 +125,9 @@ (define_c_enum "unspec" [
> UNSPEC_RSQRT
> UNSPEC_PSADBW
>
> + ;; For AVX512F support
> + UNSPEC_SCALEF
> +
> ;; Generic math support
> UNSPEC_COPYSIGN
> UNSPEC_XORSIGN
> @@ -17894,6 +17897,17 @@ (define_expand "expm1<mode>2"
> DONE;
> })
>
> +(define_insn "avx512f_scalef<mode>2"
> + [(set (match_operand:MODEF 0 "register_operand" "=v")
> + (unspec:MODEF
> + [(match_operand:MODEF 1 "register_operand" "v")
> + (match_operand:MODEF 2 "nonimmediate_operand" "vm")]
> + UNSPEC_SCALEF))]
> + "TARGET_AVX512F"
> + "vscalef<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> + [(set_attr "prefix" "evex")
> + (set_attr "mode" "<MODE>")])
> +
> (define_expand "ldexpxf3"
> [(match_operand:XF 0 "register_operand")
> (match_operand:XF 1 "register_operand")
> @@ -17924,15 +17938,12 @@ (define_expand "ldexp<mode>3"
> if (TARGET_AVX512F && TARGET_SSE_MATH)
> {
> rtx op2 = gen_reg_rtx (<MODE>mode);
> - emit_insn (gen_floatsi<mode>2 (op2, operands[2]));
> - operands[0] = lowpart_subreg (<ssevecmodef>mode, operands[0], <MODE>mode);
> - if (MEM_P (operands[1]))
> +
> + if (!nonimmediate_operand (operands[1], <MODE>mode))
> operands[1] = force_reg (<MODE>mode, operands[1]);
> - operands[1] = lowpart_subreg (<ssevecmodef>mode, operands[1], <MODE>mode);
> - op2 = lowpart_subreg (<ssevecmodef>mode, op2, <MODE>mode);
> - emit_insn (gen_avx512f_vmscalef<ssevecmodelower> (operands[0],
> - operands[1],
> - op2));
> +
> + emit_insn (gen_floatsi<mode>2 (op2, operands[2]));
> + emit_insn (gen_avx512f_scalef<mode>2 (operands[0], operands[1], op2));
> }
> else
> {
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 3957c86c3df..9233dfc6150 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -92,7 +92,6 @@ (define_c_enum "unspec" [
> UNSPEC_RCP14
> UNSPEC_RSQRT14
> UNSPEC_FIXUPIMM
> - UNSPEC_SCALEF
> UNSPEC_VTERNLOG
> UNSPEC_GETEXP
> UNSPEC_GETMANT
> --
> 2.18.1
>
Please ignore this, have replied in another thread.
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F and TARGET_SSE_MATH.
2021-08-12 4:46 ` [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F and TARGET_SSE_MATH Hongtao Liu
@ 2021-08-12 19:21 ` Uros Bizjak
0 siblings, 0 replies; 7+ messages in thread
From: Uros Bizjak @ 2021-08-12 19:21 UTC (permalink / raw)
To: Hongtao Liu; +Cc: liuhongt, gcc-patches
On Thu, Aug 12, 2021 at 6:40 AM Hongtao Liu <crazylht@gmail.com> wrote:
> > > > Hi:
> > > > AVX512F supported vscalefs{s,d} which is the same as ldexp except the second operand should be floating point.
> > > > Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
> > > >
> > > > gcc/ChangeLog:
> > > >
> > > > PR target/98309
> > > > * config/i386/i386.md (ldexp<mode>3): Extend to vscalefs[sd]
> > > > when TARGET_AVX512F and TARGET_SSE_MATH.
> > > >
> > > > gcc/testsuite/ChangeLog:
> > > >
> > > > PR target/98309
> > > > * gcc.target/i386/pr98309-1.c: New test.
> > > > * gcc.target/i386/pr98309-2.c: New test.
> > >
> > > OK.
> >
> > Actually, we should introduce a scalar version of avx512f_vmscalef, so
> > we can avoid all subreg conversions with the vector-merge (VM)
> > version, and will also allow memory in operand 2.
> >
> > Please test the attached incremental patch.
> >
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,} on CLX.
> tests is fine.
Thanks, committed with the following ChangeLog:
[i386] Introduce scalar version of avx512f_vmscalef.
2021-08-12 Uroš Bizjak <ubizjak@gmail.com>
gcc/
PR target/98309
* config/i386/i386.md (avx512f_scalef<mode>2): New insn pattern.
(ldexp<mode>3): Use avx512f_scalef<mode>2.
(UNSPEC_SCALEF): Move from ...
* config/i386/sse.md (UNSPEC_SCALEF): ... here.
Uros.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-08-12 19:21 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-10 12:13 [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F and TARGET_SSE_MATH liuhongt
2021-08-11 6:36 ` Uros Bizjak
2021-08-11 11:16 ` Uros Bizjak
2021-08-12 4:05 ` [PATCH] [i386] Introduce a scalar version of avx512f_vmscalef and adjust ldexp<mode>3 for it liuhongt
2021-08-12 4:47 ` Hongtao Liu
2021-08-12 4:46 ` [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F and TARGET_SSE_MATH Hongtao Liu
2021-08-12 19:21 ` Uros Bizjak
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).