From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb2c.google.com (mail-yb1-xb2c.google.com [IPv6:2607:f8b0:4864:20::b2c]) by sourceware.org (Postfix) with ESMTPS id 5874C3858D20 for ; Mon, 14 Nov 2022 09:04:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5874C3858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yb1-xb2c.google.com with SMTP id j2so12659942ybb.6 for ; Mon, 14 Nov 2022 01:04:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Wlsx0NoxnUbtrG+BFzx3zzj/dK7ccdacydF09PEuw8I=; b=f3pY3OAWYhQykAYRNNN1RlErMAf+RydVZkdeZBuIXfL2hiWKkPcmOxSEf3geH1ymLO xgFN4OasvAqa6BweaZ3FgoMdah07RX6up5vQfBC05UCwoj8e0s+htXZyW3JiNGQaCS0i xWmJH4YhplB/OZztuBZ65qDd+Xl4Bfjd/tMBgEaJp3SFQ2ejPeuCc1NQI4a+57Bz+7u1 W0fqWgzf9l8vBcbM8bK1MiRBvVf9gp0DjPBvfQI44VrQ9TZ6zv8B75fUCmhktZekEIXs PIVbNEXw81veW+u+karBEYJsld139OuuFGIYIs8v3ljrpLPSBEKSSx6jRmHol7Vr+kjV fHqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Wlsx0NoxnUbtrG+BFzx3zzj/dK7ccdacydF09PEuw8I=; b=i4Xgv7GqzsADWQTeA1615fEN5+T+3VVRXg8nCUruxZsSMsh2RLJZRFQPrMy5bMMu0x ksEt1jPVuCj+ntUjOnbVfzrvXQo6JfPMkRIKEKNzgNhMYB59EBPPnPEH0kkzyvm3DIXq O2z4CtHLPOwgO8MKv+IKz8F7p1N9KxlunzVWy/AupC37VrEV1apNuGNUDEK5pxF07ciO xSiFPDwT/dOWI1x7KBFeXkyGfzN2B8gNg4TpXQFX0K9Mxy/lyYWyF4zGkgaivjKf4CNA RChBHWbhndabjpYCIUc4r+GgaW0TkkywM8TkBbvu6jAB0gQTHQkAQLreF0XSDi3TU22k P0mA== X-Gm-Message-State: ANoB5pm8JGLqb//mWKyhkRQ7FpZNmUlo6zjJ1bMrNLgcMMXEc0vUYyCt mSx7kPoLm9KCLOBvzDK1C3RucksWJj5v6ud9/xY= X-Google-Smtp-Source: AA0mqf5DVz0SLdIetXcJwMXwdAIBGqUbIB89/dcZxDU7vP26U0orN46IZWBEG3eifsXTfZJT0ojaH9ZPUtp7xCg8OfU= X-Received: by 2002:a25:d02:0:b0:6d8:206:b63e with SMTP id 2-20020a250d02000000b006d80206b63emr11264763ybn.624.1668416675746; Mon, 14 Nov 2022 01:04:35 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Hongtao Liu Date: Mon, 14 Nov 2022 17:04:24 +0800 Message-ID: Subject: Re: [PATCH] i386: Emit 16b atomics inline with -m64 -mcx16 -mavx [PR104688] To: Uros Bizjak Cc: Jakub Jelinek , gcc-patches@gcc.gnu.org, Florian Weimer , "H.J. Lu" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Nov 14, 2022 at 3:57 PM Uros Bizjak via Gcc-patches wrote: > > On Mon, Nov 14, 2022 at 8:52 AM Jakub Jelinek wrote: > > > > Hi! > > > > Working virtually out of Baker Island. > > > > Given > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688#c10 > > the following patch implements atomic load/store (and therefore also > > enabling compare and exchange) for -m64 -mcx16 -mavx. > > > > Ok for trunk if it passes bootstrap/regtest? > > We only have guarantee from Intel and AMD, there can be other vendors. Can we make it a as a micro-architecture tuning? > > Uros. > > > > > 2022-11-13 Jakub Jelinek > > > > PR target/104688 > > * config/i386/sync.md (atomic_loadti, atomic_storeti): New > > define_expand patterns. > > (atomic_loadti_1, atomic_storeti_1): New define_insn patterns. > > > > * gcc.target/i386/pr104688-1.c: New test. > > * gcc.target/i386/pr104688-2.c: New test. > > * gcc.target/i386/pr104688-3.c: New test. > > > > --- gcc/config/i386/sync.md.jj 2022-11-07 20:54:37.259400942 -1200 > > +++ gcc/config/i386/sync.md 2022-11-13 19:27:22.977987355 -1200 > > @@ -225,6 +225,31 @@ (define_insn_and_split "atomic_loaddi_fp > > DONE; > > }) > > > > +;; Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned address > > +;; is atomic. AMD will give a similar guarantee. > > +(define_expand "atomic_loadti" > > + [(set (match_operand:TI 0 "register_operand" "=x,Yv") > > + (unspec:TI [(match_operand:TI 1 "memory_operand" "m,m") > > + (match_operand:SI 2 "const_int_operand")] > > + UNSPEC_LDA))] > > + "TARGET_64BIT && TARGET_CMPXCHG16B && TARGET_AVX" > > +{ > > + emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); > > + DONE; > > +}) > > + > > +(define_insn "atomic_loadti_1" > > + [(set (match_operand:TI 0 "register_operand" "=x,Yv") > > + (unspec:TI [(match_operand:TI 1 "memory_operand" "m,m")] > > + UNSPEC_LDA))] > > + "TARGET_64BIT && TARGET_CMPXCHG16B && TARGET_AVX" > > + "@ > > + vmovdqa\t{%1, %0|%0, %1} > > + vmovdqa64\t{%1, %0|%0, %1}" > > + [(set_attr "type" "ssemov") > > + (set_attr "prefix" "vex,evex") > > + (set_attr "mode" "TI")]) > > + > > (define_expand "atomic_store" > > [(set (match_operand:ATOMIC 0 "memory_operand") > > (unspec:ATOMIC [(match_operand:ATOMIC 1 "nonimmediate_operand") > > @@ -276,6 +301,36 @@ (define_insn "atomic_store_1" > > "" > > "%K2mov{}\t{%1, %0|%0, %1}") > > > > +(define_expand "atomic_storeti" > > + [(set (match_operand:TI 0 "memory_operand") > > + (unspec:TI [(match_operand:TI 1 "register_operand") > > + (match_operand:SI 2 "const_int_operand")] > > + UNSPEC_STA))] > > + "TARGET_64BIT && TARGET_CMPXCHG16B && TARGET_AVX" > > +{ > > + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); > > + > > + emit_insn (gen_atomic_storeti_1 (operands[0], operands[1], operands[2])); > > + > > + /* ... followed by an MFENCE, if required. */ > > + if (is_mm_seq_cst (model)) > > + emit_insn (gen_mem_thread_fence (operands[2])); > > + DONE; > > +}) > > + > > +(define_insn "atomic_storeti_1" > > + [(set (match_operand:TI 0 "memory_operand" "=m,m") > > + (unspec:TI [(match_operand:TI 1 "register_operand" "x,Yv") > > + (match_operand:SI 2 "const_int_operand")] > > + UNSPEC_STA))] > > + "" > > + "@ > > + %K2vmovdqa\t{%1, %0|%0, %1} > > + %K2vmovdqa64\t{%1, %0|%0, %1}" > > + [(set_attr "type" "ssemov") > > + (set_attr "prefix" "vex,evex") > > + (set_attr "mode" "TI")]) > > + > > (define_insn_and_split "atomic_storedi_fpu" > > [(set (match_operand:DI 0 "memory_operand" "=m,m,m") > > (unspec:DI [(match_operand:DI 1 "nonimmediate_operand" "x,m,?r")] > > --- gcc/testsuite/gcc.target/i386/pr104688-1.c.jj 2022-11-13 19:36:43.251332612 -1200 > > +++ gcc/testsuite/gcc.target/i386/pr104688-1.c 2022-11-13 19:40:22.649334650 -1200 > > @@ -0,0 +1,34 @@ > > +/* PR target/104688 */ > > +/* { dg-do compile { target int128 } } */ > > +/* { dg-options "-O2 -mno-cx16" } */ > > +/* { dg-final { scan-assembler "\t__sync_val_compare_and_swap_16" } } */ > > +/* { dg-final { scan-assembler "\t__atomic_load_16" } } */ > > +/* { dg-final { scan-assembler "\t__atomic_store_16" } } */ > > +/* { dg-final { scan-assembler "\t__atomic_compare_exchange_16" } } */ > > + > > +__int128 v; > > + > > +__int128 > > +f1 (void) > > +{ > > + return __sync_val_compare_and_swap (&v, 42, 0); > > +} > > + > > +__int128 > > +f2 (void) > > +{ > > + return __atomic_load_n (&v, __ATOMIC_SEQ_CST); > > +} > > + > > +void > > +f3 (__int128 x) > > +{ > > + __atomic_store_n (&v, 42, __ATOMIC_SEQ_CST); > > +} > > + > > +__int128 > > +f4 (void) > > +{ > > + __int128 y = 42; > > + __atomic_compare_exchange_n (&v, &y, 0, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); > > +} > > --- gcc/testsuite/gcc.target/i386/pr104688-2.c.jj 2022-11-13 19:36:46.513288025 -1200 > > +++ gcc/testsuite/gcc.target/i386/pr104688-2.c 2022-11-13 19:40:34.676170305 -1200 > > @@ -0,0 +1,34 @@ > > +/* PR target/104688 */ > > +/* { dg-do compile { target int128 } } */ > > +/* { dg-options "-O2 -mno-avx" } */ > > +/* { dg-final { scan-assembler "\t__sync_val_compare_and_swap_16" } } */ > > +/* { dg-final { scan-assembler "\t__atomic_load_16" } } */ > > +/* { dg-final { scan-assembler "\t__atomic_store_16" } } */ > > +/* { dg-final { scan-assembler "\t__atomic_compare_exchange_16" } } */ > > + > > +__int128 v; > > + > > +__int128 > > +f1 (void) > > +{ > > + return __sync_val_compare_and_swap (&v, 42, 0); > > +} > > + > > +__int128 > > +f2 (void) > > +{ > > + return __atomic_load_n (&v, __ATOMIC_SEQ_CST); > > +} > > + > > +void > > +f3 (__int128 x) > > +{ > > + __atomic_store_n (&v, 42, __ATOMIC_SEQ_CST); > > +} > > + > > +__int128 > > +f4 (void) > > +{ > > + __int128 y = 42; > > + __atomic_compare_exchange_n (&v, &y, 0, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); > > +} > > --- gcc/testsuite/gcc.target/i386/pr104688-3.c.jj 2022-11-13 19:37:00.899091450 -1200 > > +++ gcc/testsuite/gcc.target/i386/pr104688-3.c 2022-11-13 19:40:41.984070460 -1200 > > @@ -0,0 +1,34 @@ > > +/* PR target/104688 */ > > +/* { dg-do compile { target int128 } } */ > > +/* { dg-options "-O2 -mcx16 -mavx" } */ > > +/* { dg-final { scan-assembler-not "\t__sync_val_compare_and_swap_16" } } */ > > +/* { dg-final { scan-assembler-not "\t__atomic_load_16" } } */ > > +/* { dg-final { scan-assembler-not "\t__atomic_store_16" } } */ > > +/* { dg-final { scan-assembler-not "\t__atomic_compare_exchange_16" } } */ > > + > > +__int128 v; > > + > > +__int128 > > +f1 (void) > > +{ > > + return __sync_val_compare_and_swap (&v, 42, 0); > > +} > > + > > +__int128 > > +f2 (void) > > +{ > > + return __atomic_load_n (&v, __ATOMIC_SEQ_CST); > > +} > > + > > +void > > +f3 (__int128 x) > > +{ > > + __atomic_store_n (&v, 42, __ATOMIC_SEQ_CST); > > +} > > + > > +__int128 > > +f4 (void) > > +{ > > + __int128 y = 42; > > + __atomic_compare_exchange_n (&v, &y, 0, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); > > +} > > > > > > Jakub > > -- BR, Hongtao