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Sun, 16 Jul 2023 18:39:49 -0700 (PDT) MIME-Version: 1.0 References: <20230713060335.203711-1-haochen.jiang@intel.com> <20230713060335.203711-3-haochen.jiang@intel.com> In-Reply-To: <20230713060335.203711-3-haochen.jiang@intel.com> From: Hongtao Liu Date: Mon, 17 Jul 2023 09:39:38 +0800 Message-ID: Subject: Re: [PATCH 2/4] Support Intel SM3 To: Haochen Jiang Cc: gcc-patches@gcc.gnu.org, hongtao.liu@intel.com, ubizjak@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Jul 13, 2023 at 2:04=E2=80=AFPM Haochen Jiang via Gcc-patches wrote: > > gcc/ChangeLog: > > * common/config/i386/cpuinfo.h (get_available_features): > Detect SM3. > * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM3_SET, > OPTION_MASK_ISA2_SM3_UNSET): New. > (OPTION_MASK_ISA2_AVX_UNSET): Add SM3. > (ix86_handle_option): Handle -msm3. > * common/config/i386/i386-cpuinfo.h (enum processor_features): > Add FEATURE_SM3. > * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for > SM3. > * config.gcc: Add sm3intrin.h > * config/i386/cpuid.h (bit_SM3): New. > * config/i386/i386-builtin-types.def: > Add DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT). > * config/i386/i386-builtin.def (BDESC): Add new builtins. > * config/i386/i386-c.cc (ix86_target_macros_internal): Define > __SM3__. > * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle > V4SI_FTYPE_V4SI_V4SI_V4SI_INT. > * config/i386/i386-isa.def (SM3): Add DEF_PTA(SM3). > * config/i386/i386-options.cc (isa2_opts): Add -msm3. > (ix86_valid_target_attribute_inner_p): Handle sm3. > * config/i386/i386.opt: Add option -msm3. > * config/i386/immintrin.h: Include sm3intrin.h. > * config/i386/sse.md (vsm3msg1): New define insn. > (vsm3msg2): Ditto. > (vsm3rnds2): Ditto. > * doc/extend.texi: Document sm3. > * doc/invoke.texi: Document -msm3. > * doc/sourcebuild.texi: Document target sm3. > * config/i386/sm3intrin.h: New file. > > gcc/testsuite/ChangeLog: > > * g++.dg/other/i386-2.C: Add -msm3. > * g++.dg/other/i386-3.C: Ditto. > * gcc.target/i386/avx-1.c: Add new define for immediate. > * gcc.target/i386/funcspec-56.inc: Add new target attribute. > * gcc.target/i386/sse-12.c: Add -msm3. > * gcc.target/i386/sse-13.c: Ditto. > * gcc.target/i386/sse-14.c: Ditto. > * gcc.target/i386/sse-22.c: Add sm3. > * gcc.target/i386/sse-23.c: Ditto. > * lib/target-supports.exp (check_effective_target_sm3): New. > * gcc.target/i386/sm3-1.c: New test. > * gcc.target/i386/sm3-check.h: Ditto. > * gcc.target/i386/sm3msg1-2.c: Ditto. > * gcc.target/i386/sm3msg2-2.c: Ditto. > * gcc.target/i386/sm3rnds2-2.c: Ditto. Ok. > --- > gcc/common/config/i386/cpuinfo.h | 2 + > gcc/common/config/i386/i386-common.cc | 20 +++- > gcc/common/config/i386/i386-cpuinfo.h | 1 + > gcc/common/config/i386/i386-isas.h | 1 + > gcc/config.gcc | 3 +- > gcc/config/i386/cpuid.h | 1 + > gcc/config/i386/i386-builtin-types.def | 3 + > gcc/config/i386/i386-builtin.def | 5 + > gcc/config/i386/i386-c.cc | 2 + > gcc/config/i386/i386-expand.cc | 1 + > gcc/config/i386/i386-isa.def | 1 + > gcc/config/i386/i386-options.cc | 2 + > gcc/config/i386/i386.opt | 5 + > gcc/config/i386/immintrin.h | 2 + > gcc/config/i386/sm3intrin.h | 72 ++++++++++++ > gcc/config/i386/sse.md | 43 ++++++++ > gcc/doc/extend.texi | 5 + > gcc/doc/invoke.texi | 7 +- > gcc/doc/sourcebuild.texi | 3 + > gcc/testsuite/g++.dg/other/i386-2.C | 2 +- > gcc/testsuite/g++.dg/other/i386-3.C | 2 +- > gcc/testsuite/gcc.target/i386/avx-1.c | 3 + > gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + > gcc/testsuite/gcc.target/i386/sm3-1.c | 17 +++ > gcc/testsuite/gcc.target/i386/sm3-check.h | 37 +++++++ > gcc/testsuite/gcc.target/i386/sm3msg1-2.c | 54 +++++++++ > gcc/testsuite/gcc.target/i386/sm3msg2-2.c | 57 ++++++++++ > gcc/testsuite/gcc.target/i386/sm3rnds2-2.c | 104 ++++++++++++++++++ > gcc/testsuite/gcc.target/i386/sse-12.c | 2 +- > gcc/testsuite/gcc.target/i386/sse-13.c | 5 +- > gcc/testsuite/gcc.target/i386/sse-14.c | 5 +- > gcc/testsuite/gcc.target/i386/sse-22.c | 7 +- > gcc/testsuite/gcc.target/i386/sse-23.c | 5 +- > gcc/testsuite/lib/target-supports.exp | 15 +++ > 34 files changed, 484 insertions(+), 12 deletions(-) > create mode 100644 gcc/config/i386/sm3intrin.h > create mode 100644 gcc/testsuite/gcc.target/i386/sm3-1.c > create mode 100644 gcc/testsuite/gcc.target/i386/sm3-check.h > create mode 100644 gcc/testsuite/gcc.target/i386/sm3msg1-2.c > create mode 100644 gcc/testsuite/gcc.target/i386/sm3msg2-2.c > create mode 100644 gcc/testsuite/gcc.target/i386/sm3rnds2-2.c > > diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cp= uinfo.h > index 3599f9def2c..e5cdffe017a 100644 > --- a/gcc/common/config/i386/cpuinfo.h > +++ b/gcc/common/config/i386/cpuinfo.h > @@ -877,6 +877,8 @@ get_available_features (struct __processor_model *cpu= _model, > set_feature (FEATURE_AVXNECONVERT); > if (edx & bit_AVXVNNIINT16) > set_feature (FEATURE_AVXVNNIINT16); > + if (eax & bit_SM3) > + set_feature (FEATURE_SM3); > } > if (avx512_usable) > { > diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i3= 86/i386-common.cc > index 32c6d00580d..57b008ca3af 100644 > --- a/gcc/common/config/i386/i386-common.cc > +++ b/gcc/common/config/i386/i386-common.cc > @@ -120,6 +120,7 @@ along with GCC; see the file COPYING3. If not see > #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \ > (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_COMPLEX) > #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16 > +#define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3 > > /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same > as -msse4.2. */ > @@ -303,6 +304,7 @@ along with GCC; see the file COPYING3. If not see > #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT > #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX > #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT1= 6 > +#define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3 > > /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same > as -mno-sse4.1. */ > @@ -351,7 +353,8 @@ along with GCC; see the file COPYING3. If not see > #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ > OPTION_MASK_ISA2_SSE_UNSET > #define OPTION_MASK_ISA2_AVX_UNSET \ > - (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET) > + (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \ > + | OPTION_MASK_ISA2_SM3_UNSET) > #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET > #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET > #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET > @@ -1288,6 +1291,21 @@ ix86_handle_option (struct gcc_options *opts, > } > return true; > > + case OPT_msm3: > + if (value) > + { > + opts->x_ix86_isa_flags2 |=3D OPTION_MASK_ISA2_SM3_SET; > + opts->x_ix86_isa_flags2_explicit |=3D OPTION_MASK_ISA2_SM3_SET; > + opts->x_ix86_isa_flags |=3D OPTION_MASK_ISA_AVX_SET; > + opts->x_ix86_isa_flags_explicit |=3D OPTION_MASK_ISA_AVX_SET; > + } > + else > + { > + opts->x_ix86_isa_flags2 &=3D ~OPTION_MASK_ISA2_SM3_UNSET; > + opts->x_ix86_isa_flags2_explicit |=3D OPTION_MASK_ISA2_SM3_UNSE= T; > + } > + return true; > + > case OPT_mfma: > if (value) > { > diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i3= 86/i386-cpuinfo.h > index ae4e6a02f7f..c3403090c3b 100644 > --- a/gcc/common/config/i386/i386-cpuinfo.h > +++ b/gcc/common/config/i386/i386-cpuinfo.h > @@ -256,6 +256,7 @@ enum processor_features > FEATURE_RAOINT, > FEATURE_AMX_COMPLEX, > FEATURE_AVXVNNIINT16, > + FEATURE_SM3, > CPU_FEATURE_MAX > }; > > diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/= i386-isas.h > index fc6abdedf24..961a7f0ccd4 100644 > --- a/gcc/common/config/i386/i386-isas.h > +++ b/gcc/common/config/i386/i386-isas.h > @@ -188,4 +188,5 @@ ISA_NAMES_TABLE_START > P_NONE, "-mamx-complex") > ISA_NAMES_TABLE_ENTRY("avxvnniint16", FEATURE_AVXVNNIINT16, > P_NONE, "-mavxvnniint16") > + ISA_NAMES_TABLE_ENTRY("sm3", FEATURE_SM3, P_NONE, "-msm3") > ISA_NAMES_TABLE_END > diff --git a/gcc/config.gcc b/gcc/config.gcc > index fc74d776048..fbd7360e355 100644 > --- a/gcc/config.gcc > +++ b/gcc/config.gcc > @@ -435,7 +435,8 @@ i[34567]86-*-* | x86_64-*-*) > mwaitintrin.h avx512fp16intrin.h avx512fp16vlintri= n.h > avxifmaintrin.h avxvnniint8intrin.h avxneconvertin= trin.h > cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h > - raointintrin.h amxcomplexintrin.h avxvnniint16intr= in.h" > + raointintrin.h amxcomplexintrin.h avxvnniint16intr= in.h > + sm3intrin.h" > ;; > ia64-*-*) > extra_headers=3Dia64intrin.h > diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h > index 98d0f193d22..28a36ad0628 100644 > --- a/gcc/config/i386/cpuid.h > +++ b/gcc/config/i386/cpuid.h > @@ -132,6 +132,7 @@ > > /* Extended Features Sub-leaf (%eax =3D=3D 7, %ecx =3D=3D 1) */ > /* %eax */ > +#define bit_SM3 (1 << 1) > #define bit_RAOINT (1 << 3) > #define bit_AVXVNNI (1 << 4) > #define bit_AVX512BF16 (1 << 5) > diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i38= 6-builtin-types.def > index cb2d0cd56ed..899eac1e014 100644 > --- a/gcc/config/i386/i386-builtin-types.def > +++ b/gcc/config/i386/i386-builtin-types.def > @@ -1416,3 +1416,6 @@ DEF_FUNCTION_TYPE (LONGLONG, PLONGLONG, LONGLONG, L= ONGLONG, INT) > # PREFETCHI builtins > DEF_FUNCTION_TYPE (VOID, PCVOID, INT) > DEF_FUNCTION_TYPE (VOID, PCVOID, INT, INT, INT) > + > +# SM3 builtins > +DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT) > diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-buil= tin.def > index ff5b3dcbcd3..17db19c2495 100644 > --- a/gcc/config/i386/i386-builtin.def > +++ b/gcc/config/i386/i386-builtin.def > @@ -1655,6 +1655,11 @@ BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sha256msg= 1, 0, IX86_BUILTIN_SHA256MSG1, > BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA= 256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI) > BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SH= A256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) > > +/* SM3 */ > +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg1, "__= builtin_ia32_vsm3msg1", IX86_BUILTIN_VSM3MSG1, UNKNOWN, (int) V4SI_FTYPE_V4= SI_V4SI_V4SI) > +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg2, "__= builtin_ia32_vsm3msg2", IX86_BUILTIN_VSM3MSG2, UNKNOWN, (int) V4SI_FTYPE_V4= SI_V4SI_V4SI) > +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3rnds2, "_= _builtin_ia32_vsm3rnds2", IX86_BUILTIN_VSM3RNDS2, UNKNOWN, (int) V4SI_FTYPE= _V4SI_V4SI_V4SI_INT) > + > /* AVX512VL. */ > BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_= avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALI= GNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_USI_CONVERT) > BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_= ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PAL= IGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_UHI_CONVERT) > diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc > index d3514dd46ac..0cb5a6dcce5 100644 > --- a/gcc/config/i386/i386-c.cc > +++ b/gcc/config/i386/i386-c.cc > @@ -679,6 +679,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, > def_or_undef (parse_in, "__AMX_COMPLEX__"); > if (isa_flag2 & OPTION_MASK_ISA2_AVXVNNIINT16) > def_or_undef (parse_in, "__AVXVNNIINT16__"); > + if (isa_flag2 & OPTION_MASK_ISA2_SM3) > + def_or_undef (parse_in, "__SM3__"); > if (TARGET_IAMCU) > { > def_or_undef (parse_in, "__iamcu"); > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand= .cc > index 648d6098eff..f6ad54c0cfe 100644 > --- a/gcc/config/i386/i386-expand.cc > +++ b/gcc/config/i386/i386-expand.cc > @@ -11202,6 +11202,7 @@ ix86_expand_args_builtin (const struct builtin_de= scription *d, > case V4SF_FTYPE_V4SF_V4SF_V4SI_INT: > case V8SF_FTYPE_V8SF_V8SF_V8SI_INT: > case V16SF_FTYPE_V16SF_V16SF_V16SI_INT: > + case V4SI_FTYPE_V4SI_V4SI_V4SI_INT: > nargs =3D 4; > nargs_constant =3D 1; > break; > diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def > index fbf22f7270a..432c36e7f79 100644 > --- a/gcc/config/i386/i386-isa.def > +++ b/gcc/config/i386/i386-isa.def > @@ -118,3 +118,4 @@ DEF_PTA(PREFETCHI) > DEF_PTA(RAOINT) > DEF_PTA(AMX_COMPLEX) > DEF_PTA(AVXVNNIINT16) > +DEF_PTA(SM3) > diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-optio= ns.cc > index d981666dd87..db2ff0c7ae1 100644 > --- a/gcc/config/i386/i386-options.cc > +++ b/gcc/config/i386/i386-options.cc > @@ -241,6 +241,7 @@ static struct ix86_target_opts isa2_opts[] =3D > { "-mraoint", OPTION_MASK_ISA2_RAOINT }, > { "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX }, > { "-mavxvnniint16", OPTION_MASK_ISA2_AVXVNNIINT16 }, > + { "-msm3", OPTION_MASK_ISA2_SM3 } > }; > static struct ix86_target_opts isa_opts[] =3D > { > @@ -1093,6 +1094,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, t= ree args, char *p_strings[], > IX86_ATTR_ISA ("raoint", OPT_mraoint), > IX86_ATTR_ISA ("amx-complex", OPT_mamx_complex), > IX86_ATTR_ISA ("avxvnniint16", OPT_mavxvnniint16), > + IX86_ATTR_ISA ("sm3", OPT_msm3), > > /* enum options */ > IX86_ATTR_ENUM ("fpmath=3D", OPT_mfpmath_), > diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt > index 618d713530f..80a8611993c 100644 > --- a/gcc/config/i386/i386.opt > +++ b/gcc/config/i386/i386.opt > @@ -1283,3 +1283,8 @@ mavxvnniint16 > Target Mask(ISA2_AVXVNNIINT16) Var(ix86_isa_flags2) Save > Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and > AVXVNNIINT16 built-in functions and code generation. > + > +msm3 > +Target Mask(ISA2_SM3) Var(ix86_isa_flags2) Save > +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and > +SM3 built-in functions and code generation. > diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h > index 52dc35d8398..7731990131c 100644 > --- a/gcc/config/i386/immintrin.h > +++ b/gcc/config/i386/immintrin.h > @@ -108,6 +108,8 @@ > > #include > > +#include > + > #include > > #include > diff --git a/gcc/config/i386/sm3intrin.h b/gcc/config/i386/sm3intrin.h > new file mode 100644 > index 00000000000..378c3dd41d9 > --- /dev/null > +++ b/gcc/config/i386/sm3intrin.h > @@ -0,0 +1,72 @@ > +/* Copyright (C) 2023 Free Software Foundation, Inc. > + > + This file is part of GCC. > + > + GCC is free software; you can redistribute it and/or modify > + it under the terms of the GNU General Public License as published by > + the Free Software Foundation; either version 3, or (at your option) > + any later version. > + > + GCC is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + GNU General Public License for more details. > + > + Under Section 7 of GPL version 3, you are granted additional > + permissions described in the GCC Runtime Library Exception, version > + 3.1, as published by the Free Software Foundation. > + > + You should have received a copy of the GNU General Public License and > + a copy of the GCC Runtime Library Exception along with this program; > + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > + . */ > + > +#ifndef _IMMINTRIN_H_INCLUDED > +#error "Never use directly; include instead.= " > +#endif > + > +#ifndef _SM3INTRIN_H_INCLUDED > +#define _SM3INTRIN_H_INCLUDED > + > +#ifndef __SM3__ > +#pragma GCC push_options > +#pragma GCC target("sm3") > +#define __DISABLE_SM3__ > +#endif /* __SM3__ */ > + > +extern __inline __m128i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C) > +{ > + return (__m128i) __builtin_ia32_vsm3msg1 ((__v4si) __A, (__v4si) __B, > + (__v4si) __C); > +} > + > +extern __inline __m128i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm_sm3msg2_epi32 (__m128i __A, __m128i __B, __m128i __C) > +{ > + return (__m128i) __builtin_ia32_vsm3msg2 ((__v4si) __A, (__v4si) __B, > + (__v4si) __C); > +} > + > +#ifdef __OPTIMIZE__ > +extern __inline __m128i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm_sm3rnds2_epi32 (__m128i __A, __m128i __B, __m128i __C, const int __D= ) > +{ > + return (__m128i) __builtin_ia32_vsm3rnds2 ((__v4si) __A, (__v4si) __B, > + (__v4si) __C, __D); > +} > +#else > +#define _mm_sm3rnds2_epi32(A, B, C, D) \ > + ((__m128i) __builtin_ia32_vsm3rnds2 ((__v4si) (A), (__v4si) (B), \ > + (__v4si) (C), (int) (D))) > +#endif > + > +#ifdef __DISABLE_SM3__ > +#undef __DISABLE_SM3__ > +#pragma GCC pop_options > +#endif /* __DISABLE_SM3__ */ > + > +#endif /* _SM3INTRIN_H_INCLUDED */ > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 85a5f801e7a..25a1e5dd780 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -196,6 +196,11 @@ > UNSPEC_COMPLEX_FMUL > UNSPEC_COMPLEX_FCMUL > UNSPEC_COMPLEX_MASK > + > + ;; For SM3 support > + UNSPEC_SM3MSG1 > + UNSPEC_SM3MSG2 > + UNSPEC_SM3RNDS2 > > ;; For AVX-VNNI-INT8 support > UNSPEC_VPDPBSSD > @@ -28597,6 +28602,44 @@ > (set_attr "length_immediate" "1") > (set_attr "mode" "TI")]) > > +(define_insn "vsm3msg1" > + [(set (match_operand:V4SI 0 "register_operand" "=3Dx") > + (unspec:V4SI > + [(match_operand:V4SI 1 "register_operand" "0") > + (match_operand:V4SI 2 "register_operand" "x") > + (match_operand:V4SI 3 "vector_operand" "xBm")] > + UNSPEC_SM3MSG1))] > + "TARGET_SM3" > + "vsm3msg1\t{%3, %2, %0|%0, %2, %3}" > + [(set_attr "type" "other") > + (set_attr "mode" "TI")]) > + > +(define_insn "vsm3msg2" > + [(set (match_operand:V4SI 0 "register_operand" "=3Dx") > + (unspec:V4SI > + [(match_operand:V4SI 1 "register_operand" "0") > + (match_operand:V4SI 2 "register_operand" "x") > + (match_operand:V4SI 3 "vector_operand" "xBm")] > + UNSPEC_SM3MSG2))] > + "TARGET_SM3" > + "vsm3msg2\t{%3, %2, %0|%0, %2, %3}" > + [(set_attr "type" "other") > + (set_attr "mode" "TI")]) > + > +(define_insn "vsm3rnds2" > + [(set (match_operand:V4SI 0 "register_operand" "=3Dx") > + (unspec:V4SI > + [(match_operand:V4SI 1 "register_operand" "0") > + (match_operand:V4SI 2 "register_operand" "x") > + (match_operand:V4SI 3 "vector_operand" "xBm") > + (match_operand:SI 4 "const_0_to_255_operand" "n")] > + UNSPEC_SM3RNDS2))] > + "TARGET_SM3" > + "vsm3rnds2\t{%4, %3, %2, %0|%0, %2, %3, %4}" > + [(set_attr "type" "other") > + (set_attr "mode" "TI") > + (set_attr "length_immediate" "1")]) > + > (define_insn_and_split "avx512f__" > [(set (match_operand:AVX512MODE2P 0 "nonimmediate_operand" "=3Dx,m") > (vec_concat:AVX512MODE2P > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > index 565bf1352e2..e76cd399a83 100644 > --- a/gcc/doc/extend.texi > +++ b/gcc/doc/extend.texi > @@ -7168,6 +7168,11 @@ Enable/disable the generation of the AMX-COMPLEX i= nstructions. > @itemx no-avxvnniint16 > Enable/disable the generation of the AVXVNNIINT16 instructions. > > +@cindex @code{target("sm3")} function attribute, x86 > +@item sm3 > +@itemx no-sm3 > +Enable/disable the generation of the SM3 instructions. > + > @cindex @code{target("cld")} function attribute, x86 > @item cld > @itemx no-cld > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 359887db5fd..2671d70736f 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -1433,7 +1433,7 @@ See RS/6000 and PowerPC Options. > -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk > -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni > -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp= 16 > --mprefetchi -mraoint -mamx-complex -mavxvnniint16 > +-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 > -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops > -minline-stringops-dynamically -mstringop-strategy=3D@var{alg} > -mkl -mwidekl > @@ -33555,6 +33555,9 @@ preferred alignment to @option{-mpreferred-stack-= boundary=3D2}. > @need 200 > @opindex mavxvnniint16 > @itemx -mavxvnniint16 > +@need 200 > +@opindex msm3 > +@itemx -msm3 > These switches enable the use of instructions in the MMX, SSE, > AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI= , SHA, > AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCON= FIG, > @@ -33565,7 +33568,7 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MO= VDIRI, MOVDIR64B, AVX512BF16, > ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALI= ZE, > UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP= 16, > AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOI= NT, > -AMX-COMPLEX, AVXVNNIINT16 or CLDEMOTE extended instruction sets. Each ha= s a > +AMX-COMPLEX, AVXVNNIINT16, SM3 or CLDEMOTE extended instruction sets. Ea= ch has a > corresponding @option{-mno-} option to disable use of these instructions= . > > These extensions are also available as built-in functions: see > diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi > index 40919b30a62..dae51132c42 100644 > --- a/gcc/doc/sourcebuild.texi > +++ b/gcc/doc/sourcebuild.texi > @@ -2589,6 +2589,9 @@ Target supports the execution of @code{raoint} inst= ructions. > @item rdrand > Target supports x86 @code{rdrand} instruction. > > +@item sm3 > +Target supports the execution of @code{sm3} instructions. > + > @item sqrt_insn > Target has a square root instruction that the compiler can generate. > > diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/o= ther/i386-2.C > index 53622df2bb8..2ec93261cac 100644 > --- a/gcc/testsuite/g++.dg/other/i386-2.C > +++ b/gcc/testsuite/g++.dg/other/i386-2.C > @@ -1,5 +1,5 @@ > /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ > -/* { dg-options "-O -pedantic-errors -march=3Dk8 -msse4a -m3dnow -mavx -= mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm= -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr= -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 = -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512if= ma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcnt= dq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpco= nfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mts= xldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp1= 6 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi= -mraoint -mamx-complex -mavxvnniint16" } */ > +/* { dg-options "-O -pedantic-errors -march=3Dk8 -msse4a -m3dnow -mavx -= mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm= -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr= -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 = -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512if= ma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcnt= dq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpco= nfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mts= xldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp1= 6 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi= -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ > > /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, > xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, > diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/o= ther/i386-3.C > index 3b76cee3af8..fe03143e39b 100644 > --- a/gcc/testsuite/g++.dg/other/i386-3.C > +++ b/gcc/testsuite/g++.dg/other/i386-3.C > @@ -1,5 +1,5 @@ > /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ > -/* { dg-options "-O -fkeep-inline-functions -march=3Dk8 -msse4a -m3dnow = -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi= 2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx= -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefe= tchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mav= x512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512v= popcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg= -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserializ= e -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx= 512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mpre= fetchi -mraoint -mamx-complex -mavxvnniint16" } */ > +/* { dg-options "-O -fkeep-inline-functions -march=3Dk8 -msse4a -m3dnow = -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi= 2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx= -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefe= tchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mav= x512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512v= popcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg= -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserializ= e -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx= 512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mpre= fetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ > > /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, > xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, > diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.ta= rget/i386/avx-1.c > index 0b2b68b678d..a6589deca84 100644 > --- a/gcc/testsuite/gcc.target/i386/avx-1.c > +++ b/gcc/testsuite/gcc.target/i386/avx-1.c > @@ -839,6 +839,9 @@ > #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A,= B, C, 1) > #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd6= 4(A, B, C, 1) > > +/* sm3intrin.h */ > +#define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A= , B, C, 1) > + > #include > #include > #include > diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuit= e/gcc.target/i386/funcspec-56.inc > index bba0fa37efd..8dd8d9bf9d8 100644 > --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc > +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc > @@ -89,6 +89,7 @@ extern void test_prefetchi (void) __attri= bute__((__target__("prefe > extern void test_raoint (void) __attribute__((__target_= _("raoint"))); > extern void test_amx_complex (void) __attribute__((__target__= ("amx-complex"))); > extern void test_avxvnniint16 (void) __attribute__((__target__= ("avxvnniint16"))); > +extern void test_sm3 (void) __attribute__((__target__= ("sm3"))); > > extern void test_no_sgx (void) __attribute__((__target__= ("no-sgx"))); > extern void test_no_avx5124fmaps(void) __attribute__((__target__= ("no-avx5124fmaps"))); > @@ -179,6 +180,7 @@ extern void test_no_prefetchi (void) __att= ribute__((__target__("no-pr > extern void test_no_raoint (void) __attribute__((__target_= _("no-raoint"))); > extern void test_no_amx_complex (void) __attribute__((__target__= ("no-amx-complex"))); > extern void test_no_avxvnniint16 (void) __attribute__((__= target__("no-avxvnniint16"))); > +extern void test_no_sm3 (void) __attribute__((__target__= ("no-sm3"))); > > extern void test_arch_nocona (void) __attribute__((__target__= ("arch=3Dnocona"))); > extern void test_arch_core2 (void) __attribute__((__target__= ("arch=3Dcore2"))); > diff --git a/gcc/testsuite/gcc.target/i386/sm3-1.c b/gcc/testsuite/gcc.ta= rget/i386/sm3-1.c > new file mode 100644 > index 00000000000..0a8ea658130 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/sm3-1.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -msm3" } */ > +/* { dg-final { scan-assembler "vsm3msg1\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^= \n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]" } } */ > +/* { dg-final { scan-assembler "vsm3msg2\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^= \n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]" } } */ > +/* { dg-final { scan-assembler "vsm3rnds2\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[= ^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]" } } */ > + > +#include > + > +volatile __m128i x, y, z; > + > +void extern > +sm3_test (void) > +{ > + x =3D _mm_sm3msg1_epi32 (x, y, z); > + x =3D _mm_sm3msg2_epi32 (x, y, z); > + x =3D _mm_sm3rnds2_epi32 (x, y, z, 1); > +} > diff --git a/gcc/testsuite/gcc.target/i386/sm3-check.h b/gcc/testsuite/gc= c.target/i386/sm3-check.h > new file mode 100644 > index 00000000000..ad9847402fc > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/sm3-check.h > @@ -0,0 +1,37 @@ > +#include > +#include "m128-check.h" > + > +static void sm3_test (void); > + > +static unsigned > +rol32 (unsigned w, int n) > +{ > + int count =3D n % 32; > + return ((w << n) | (w >> (32 - n))); > +} > + > +static void > +__attribute__ ((noinline)) > +do_test (void) > +{ > + sm3_test (); > +} > + > +int > +main () > +{ > + /* Run SM3 test only if host has SM3 support. */ > + if (__builtin_cpu_supports ("sm3")) > + { > + do_test (); > +#ifdef DEBUG > + printf ("PASSED\n"); > +#endif > + return 0; > + } > + > +#ifdef DEBUG > + printf ("SKIPPED\n"); > +#endif > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/i386/sm3msg1-2.c b/gcc/testsuite/gc= c.target/i386/sm3msg1-2.c > new file mode 100644 > index 00000000000..e08abf5539d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/sm3msg1-2.c > @@ -0,0 +1,54 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2 -msm3" } */ > +/* { dg-require-effective-target sm3 } */ > + > +#include "sm3-check.h" > +#include > +#include > + > +static unsigned > +p1 (unsigned w) > +{ > + return rol32 (w, 15) ^ rol32 (w, 23) ^ w; > +} > + > +static void > +compute_sm3msg1 (int *src0, int *src1, int *src2, int *res) > +{ > + unsigned w0, w1, w2, w3, w7, w8, w9, w10, w13, w14, w15; > + > + w0 =3D src2[0]; > + w1 =3D src2[1]; > + w2 =3D src2[2]; > + w3 =3D src2[3]; > + w7 =3D src0[0]; > + w8 =3D src0[1]; > + w9 =3D src0[2]; > + w10 =3D src0[3]; > + w13 =3D src1[0]; > + w14 =3D src1[1]; > + w15 =3D src1[2]; > + > + res[0] =3D p1 (w7 ^ w0 ^ rol32 (w13, 15)); > + res[1] =3D p1 (w8 ^ w1 ^ rol32 (w14, 15)); > + res[2] =3D p1 (w9 ^ w2 ^ rol32 (w15, 15)); > + res[3] =3D p1 (w10 ^ w3); > +} > + > +static void > +sm3_test (void) > +{ > + union128i_d s1, s2, s3, res; > + int res_ref[4]; > + > + s1.x =3D _mm_set_epi32 (111, 222, 333, 444); > + s2.x =3D _mm_set_epi32 (555, 666, 777, 888); > + s3.x =3D _mm_set_epi32 (999, 123, 456, 789); > + > + res.x =3D _mm_sm3msg1_epi32 (s1.x, s2.x, s3.x); > + > + compute_sm3msg1 (s1.a, s2.a, s3.a, res_ref); > + > + if (check_union128i_d (res, res_ref)) > + abort (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/sm3msg2-2.c b/gcc/testsuite/gc= c.target/i386/sm3msg2-2.c > new file mode 100644 > index 00000000000..f5986313c7d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/sm3msg2-2.c > @@ -0,0 +1,57 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2 -msm3" } */ > +/* { dg-require-effective-target sm3 } */ > + > +#include "sm3-check.h" > +#include > +#include > + > +static void > +compute_sm3msg2 (int *src0, int *src1, int *src2, int *res) > +{ > + unsigned wtmp0, wtmp1, wtmp2, wtmp3, w3, w4, w5, w6, w10, w11, w12, w1= 3, > + w16, w17, w18, w19; > + > + wtmp0 =3D src0[0]; > + wtmp1 =3D src0[1]; > + wtmp2 =3D src0[2]; > + wtmp3 =3D src0[3]; > + w3 =3D src1[0]; > + w4 =3D src1[1]; > + w5 =3D src1[2]; > + w6 =3D src1[3]; > + w10 =3D src2[0]; > + w11 =3D src2[1]; > + w12 =3D src2[2]; > + w13 =3D src2[3]; > + > + w16 =3D rol32 (w3, 7) ^ w10 ^ wtmp0; > + w17 =3D rol32 (w4, 7) ^ w11 ^ wtmp1; > + w18 =3D rol32 (w5, 7) ^ w12 ^ wtmp2; > + w19 =3D rol32 (w6, 7) ^ w13 ^ wtmp3; > + > + w19 =3D w19 ^ rol32 (w16, 6) ^ rol32 (w16, 15) ^ rol32 (w16, 30) ; > + > + res[0] =3D w16; > + res[1] =3D w17; > + res[2] =3D w18; > + res[3] =3D w19; > +} > + > +static void > +sm3_test (void) > +{ > + union128i_d s1, s2, s3, res; > + int res_ref[4]; > + > + s1.x =3D _mm_set_epi32 (111, 222, 333, 444); > + s2.x =3D _mm_set_epi32 (555, 666, 777, 888); > + s3.x =3D _mm_set_epi32 (999, 123, 456, 789); > + > + res.x =3D _mm_sm3msg2_epi32 (s1.x, s2.x, s3.x); > + > + compute_sm3msg2 (s1.a, s2.a, s3.a, res_ref); > + > + if (check_union128i_d (res, res_ref)) > + abort (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/sm3rnds2-2.c b/gcc/testsuite/g= cc.target/i386/sm3rnds2-2.c > new file mode 100644 > index 00000000000..ffa3ed125f3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/sm3rnds2-2.c > @@ -0,0 +1,104 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2 -msm3" } */ > +/* { dg-require-effective-target sm3 } */ > + > +#include "sm3-check.h" > +#include > +#include > + > +static unsigned > +p0 (unsigned w) > +{ > + return (w ^ rol32 (w, 9) ^ rol32 (w, 17)); > +} > + > +static unsigned > +ff (unsigned x, unsigned y, unsigned z, int round) > +{ > + if (round < 16) > + return (x ^ y ^ z); > + else > + return ((x & y) | (x & z) | (y & z)); > +} > + > +static unsigned > +gg (unsigned x, unsigned y, unsigned z, int round) > +{ > + if (round < 16) > + return (x ^ y ^ z); > + else > + return ((x & y) | ((~x) & z)); > +} > + > +static void > +compute_sm3rnds2 (int *src0, int *src1, int *src2, int imm, int *res) > +{ > + unsigned s1, s2, t1, t2, co; > + unsigned w[6], a[3], b[3], c[3], d[3], e[3], f[3], g[3], h[3]; > + int round, i; > + > + a[0] =3D src1[3]; > + b[0] =3D src1[2]; > + c[0] =3D src0[3]; > + d[0] =3D src0[2]; > + e[0] =3D src1[1]; > + f[0] =3D src1[0]; > + g[0] =3D src0[1]; > + h[0] =3D src0[0]; > + w[0] =3D src2[0]; > + w[1] =3D src2[1]; > + w[4] =3D src2[2]; > + w[5] =3D src2[3]; > + > + c[0] =3D rol32 (c[0], 9); > + d[0] =3D rol32 (d[0], 9); > + g[0] =3D rol32 (g[0], 19); > + h[0] =3D rol32 (h[0], 19); > + > + round =3D imm & 0x3e; > + if (round < 16) > + co =3D 0x79cc4519; > + else > + co =3D 0x7a879d8a; > + co =3D rol32 (co, round); > + > + for (i =3D 0; i < 2; i++) > + { > + s1 =3D rol32 ((rol32 (a[i], 12) + e[i] + co), 7); > + s2 =3D s1 ^ rol32 (a[i], 12); > + t1 =3D ff (a[i], b[i], c[i], round) + d[i] + s2 + (w[i] ^ w[i + 4]); > + t2 =3D gg (e[i], f[i], g[i], round) + h[i] + s1 + w[i]; > + d[i + 1] =3D c[i]; > + c[i + 1] =3D rol32 (b[i], 9); > + b[i + 1] =3D a[i]; > + a[i + 1] =3D t1; > + h[i + 1] =3D g[i]; > + g[i + 1] =3D rol32 (f[i], 19); > + f[i + 1] =3D e[i]; > + e[i + 1] =3D p0 (t2); > + co =3D rol32 (co, 1); > + } > + > + res[3] =3D a[2]; > + res[2] =3D b[2]; > + res[1] =3D e[2]; > + res[0] =3D f[2]; > +} > + > +static void > +sm3_test (void) > +{ > + union128i_d s1, s2, s3, res; > + int res_ref[4]; > + > + s1.x =3D _mm_set_epi32 (111, 222, 333, 444); > + s2.x =3D _mm_set_epi32 (555, 666, 777, 888); > + s3.x =3D _mm_set_epi32 (999, 123, 456, 789); > + > + res.x =3D _mm_sm3rnds2_epi32 (s1.x, s2.x, s3.x, 22); > + > + compute_sm3rnds2 (s1.a, s2.a, s3.a, 22, res_ref); > + > + if (check_union128i_d (res, res_ref)) > + abort (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.t= arget/i386/sse-12.c > index 2b7d78c51d3..5058be6f6e9 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-12.c > +++ b/gcc/testsuite/gcc.target/i386/sse-12.c > @@ -3,7 +3,7 @@ > popcntintrin.h gfniintrin.h and mm_malloc.h are usable > with -O -std=3Dc89 -pedantic-errors. */ > /* { dg-do compile } */ > -/* { dg-options "-O -std=3Dc89 -pedantic-errors -march=3Dk8 -msse4a -m3d= now -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -= mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -= madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mp= refetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl = -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx= 512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bi= talg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mseri= alize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -= mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -ma= vxvnniint16" } */ > +/* { dg-options "-O -std=3Dc89 -pedantic-errors -march=3Dk8 -msse4a -m3d= now -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -= mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -= madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mp= refetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl = -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx= 512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bi= talg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mseri= alize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -= mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -ma= vxvnniint16 -msm3" } */ > > #include > > diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.t= arget/i386/sse-13.c > index 33693484d2a..d30b365564a 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-13.c > +++ b/gcc/testsuite/gcc.target/i386/sse-13.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=3Dk8 -= msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlz= cnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed= -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512p= f -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq = -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124= vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku= -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -men= qcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl = -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -= mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */ > +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=3Dk8 -= msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlz= cnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed= -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512p= f -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq = -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124= vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku= -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -men= qcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl = -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -= mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ > /* { dg-add-options bind_pic_locally } */ > > #include > @@ -846,4 +846,7 @@ > #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A,= B, C, 1) > #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd6= 4(A, B, C, 1) > > +/* sm3intrin.h */ > +#define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A= , B, C, 1) > + > #include > diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.t= arget/i386/sse-14.c > index 51c2946b25a..7842005a98b 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-14.c > +++ b/gcc/testsuite/gcc.target/i386/sse-14.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=3Dk8 -= msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlz= cnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed= -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512p= f -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw = -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124= vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni= -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect= -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mav= xvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoi= nt -mamx-complex -mavxvnniint16" } */ > +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=3Dk8 -= msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlz= cnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed= -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512p= f -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw = -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124= vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni= -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect= -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mav= xvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoi= nt -mamx-complex -mavxvnniint16 -msm3" } */ > /* { dg-add-options bind_pic_locally } */ > > #include > @@ -1054,3 +1054,6 @@ test_2 (_mm512_gf2p8affineinv_epi64_epi8, __m512i, = __m512i, __m512i, 1) > test_2 (_mm_gf2p8affine_epi64_epi8, __m128i, __m128i, __m128i, 1) > test_2 (_mm256_gf2p8affine_epi64_epi8, __m256i, __m256i, __m256i, 1) > test_2 (_mm512_gf2p8affine_epi64_epi8, __m512i, __m512i, __m512i, 1) > + > +/* sm3intrin.h */ > +test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1) > diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.t= arget/i386/sse-22.c > index 4982fde2a76..7537db1ac30 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-22.c > +++ b/gcc/testsuite/gcc.target/i386/sse-22.c > @@ -103,7 +103,7 @@ > > > #ifndef DIFFERENT_PRAGMAS > -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm= ,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsav= eopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,a= vx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512v= popcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk= ,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint= 8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16") > +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm= ,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsav= eopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,a= vx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512v= popcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk= ,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint= 8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3") > #endif > > /* Following intrinsics require immediate arguments. They > @@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int= , 1) > > /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */ > #ifdef DIFFERENT_PRAGMAS > -#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,a= vx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx51= 2vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf= 16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,wide= kl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-= complex,avxvnniint16") > +#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,a= vx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx51= 2vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf= 16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,wide= kl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-= complex,avxvnniint16,sm3") > #endif > #include > test_1 (_cvtss_sh, unsigned short, float, 1) > @@ -1099,3 +1099,6 @@ test_1 ( __bextri_u32, unsigned int, unsigned int, = 1) > #ifdef __x86_64__ > test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1) > #endif > + > +/* sm3intrin.h */ > +test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1) > diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.t= arget/i386/sse-23.c > index 7e9c9f2ca2b..3fc61b50fe6 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-23.c > +++ b/gcc/testsuite/gcc.target/i386/sse-23.c > @@ -847,6 +847,9 @@ > #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A,= B, C, 1) > #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd6= 4(A, B, C, 1) > > -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm= ,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,= xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,c= lflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx= 5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2= ,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2inters= ect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512f= p16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,am= x-complex,avxvnniint16") > +/* sm3intrin.h */ > +#define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A= , B, C, 1) > + > +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm= ,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,= xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,c= lflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx= 5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2= ,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2inters= ect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512f= p16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,am= x-complex,avxvnniint16,sm3") > > #include > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/ta= rget-supports.exp > index 60de239f1ce..c911a824d31 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -9868,6 +9868,21 @@ proc check_effective_target_avxvnniint16 { } { > } "-O0 -mavxvnniint16" ] > } > > +# Return 1 if sm3 instructions can be compiled. > +proc check_effective_target_sm3 { } { > + return [check_no_compiler_messages sm3 object { > + typedef long long __m128i __attribute__ ((__vector_size__ (16))); > + typedef int __v4si __attribute__ ((__vector_size__ (16))); > + __m128i > + _mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C) > + { > + return (__m128i) __builtin_ia32_vsm3msg1 ((__v4si) __A, > + (__v4si) __B, > + (__v4si) __C); > + } > + } "-msm3" ] > +} > + > # Return 1 if sse instructions can be compiled. > proc check_effective_target_sse { } { > return [check_no_compiler_messages sse object { > -- > 2.31.1 > --=20 BR, Hongtao