From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb29.google.com (mail-yb1-xb29.google.com [IPv6:2607:f8b0:4864:20::b29]) by sourceware.org (Postfix) with ESMTPS id 6C43E3857BB1 for ; Mon, 6 Jun 2022 05:25:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6C43E3857BB1 Received: by mail-yb1-xb29.google.com with SMTP id g4so23748688ybf.12 for ; Sun, 05 Jun 2022 22:25:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=uqESkZE3Jxm57yur+ZL+bHE4irmJVA2xbaZfkR1BHFU=; b=4d91RKWJC9KyAffZHpRwP0mBJivKkHinf9lKWBhp8ep9v6asxROoJn6wck+1hF7fBy 2DVBtLqAQ5kRt+G7c7oCvPuH/azF8X3bI+sQxAn8IQzs/8ircGzYjQ6fGWau9r31Zr98 PEUjqRJ2TgYoWjufkE80duThSX1gLB3OlEqJC92tcfKqkWZ+AVasjpsX6i00EJuuCrj1 fKB2+PI9vKJ4bwGjubSqAv9rrX9ZXXEZl6Di2WSmUyNp2W8jaFJ22RqkggtZYTiCayku RT2o9z6FKOwughcFcamCbmt6uOEi/99s4tI8o6oJrENJB0oHz2sWoUO7exlwlHxe0Bxp 0EOA== X-Gm-Message-State: AOAM531Nrsni6jq6zFG/dQgUBc4UAtmHTZdnOWgUYtCki15zlNb86/7I Fkk1LYFI4cAqg4XbAO96dPTGt6YOe+mizapW3n4= X-Google-Smtp-Source: ABdhPJwsJw3W3H2/zbWZUQ7APOwmg6aSN2E5NIIFQRzieVSmVJFQ+MtahQ718nxlYelejwP9xsl/p/dznR45RoBsIfI= X-Received: by 2002:a25:680e:0:b0:65c:bc72:94f4 with SMTP id d14-20020a25680e000000b0065cbc7294f4mr22438270ybc.251.1654493115683; Sun, 05 Jun 2022 22:25:15 -0700 (PDT) MIME-Version: 1.0 References: <20220601050606.3508-1-lili.cui@intel.com> In-Reply-To: From: Hongtao Liu Date: Mon, 6 Jun 2022 13:25:04 +0800 Message-ID: Subject: Re: [PATCH] Update {skylake,icelake,alderlake}_cost to add a bit preference to vector store. To: "H.J. Lu" Cc: "Cui,Lili" , Hongtao Liu , GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Jun 2022 05:25:18 -0000 On Wed, Jun 1, 2022 at 11:56 PM H.J. Lu via Gcc-patches wrote: > > On Tue, May 31, 2022 at 10:06 PM Cui,Lili wrote: > > > > This patch is to update {skylake,icelake,alderlake}_cost to add a bit preference to vector store. > > Since the interger vector construction cost has changed, we need to adjust the load and store costs for intel processers. > > > > With the patch applied > > 538.imagic_r:gets ~6% improvement on ADL for multicopy. > > 525.x264_r :gets ~2% improvement on ADL and ICX for multicopy. > > with no measurable changes for other benchmarks. > > > > Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. Ok for trunk? > > > > Thanks, > > Lili. > > > > gcc/ChangeLog > > > > PR target/105493 > > * config/i386/x86-tune-costs.h (skylake_cost): Raise the gpr load cost > > from 4 to 6 and gpr store cost from 6 to 8. Change SSE loads and > > unaligned loads cost from {6, 6, 6, 10, 20} to {8, 8, 8, 8, 16}. > > (icelake_cost): Ditto. > > (alderlake_cost): Raise the gpr store cost from 6 to 8 and SSE loads, > > stores and unaligned stores cost from {6, 6, 6, 10, 15} to > > {8, 8, 8, 10, 15}. > > > > gcc/testsuite/ > > > > PR target/105493 > > * gcc.target/i386/pr91446.c: Adjust to expect vectorization > > * gcc.target/i386/pr99881.c: XFAIL. > > --- > > gcc/config/i386/x86-tune-costs.h | 26 ++++++++++++------------- > > gcc/testsuite/gcc.target/i386/pr91446.c | 2 +- > > gcc/testsuite/gcc.target/i386/pr99881.c | 2 +- > > 3 files changed, 15 insertions(+), 15 deletions(-) > > > > diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h > > index ea34a939c68..6c9066c84cc 100644 > > --- a/gcc/config/i386/x86-tune-costs.h > > +++ b/gcc/config/i386/x86-tune-costs.h > > @@ -1897,15 +1897,15 @@ struct processor_costs skylake_cost = { > > 8, /* "large" insn */ > > 17, /* MOVE_RATIO */ > > 17, /* CLEAR_RATIO */ > > - {4, 4, 4}, /* cost of loading integer registers > > + {6, 6, 6}, /* cost of loading integer registers > > in QImode, HImode and SImode. > > Relative to reg-reg move (2). */ > > - {6, 6, 6}, /* cost of storing integer registers */ > > - {6, 6, 6, 10, 20}, /* cost of loading SSE register > > + {8, 8, 8}, /* cost of storing integer registers */ > > + {8, 8, 8, 8, 16}, /* cost of loading SSE register > > in 32bit, 64bit, 128bit, 256bit and 512bit */ > > {8, 8, 8, 8, 16}, /* cost of storing SSE register > > in 32bit, 64bit, 128bit, 256bit and 512bit */ > > - {6, 6, 6, 10, 20}, /* cost of unaligned loads. */ > > + {8, 8, 8, 8, 16}, /* cost of unaligned loads. */ > > {8, 8, 8, 8, 16}, /* cost of unaligned stores. */ > > 2, 2, 4, /* cost of moving XMM,YMM,ZMM register */ > > 6, /* cost of moving SSE register to integer. */ > > @@ -2023,15 +2023,15 @@ struct processor_costs icelake_cost = { > > 8, /* "large" insn */ > > 17, /* MOVE_RATIO */ > > 17, /* CLEAR_RATIO */ > > - {4, 4, 4}, /* cost of loading integer registers > > + {6, 6, 6}, /* cost of loading integer registers > > in QImode, HImode and SImode. > > Relative to reg-reg move (2). */ > > - {6, 6, 6}, /* cost of storing integer registers */ > > - {6, 6, 6, 10, 20}, /* cost of loading SSE register > > + {8, 8, 8}, /* cost of storing integer registers */ > > + {8, 8, 8, 8, 16}, /* cost of loading SSE register > > in 32bit, 64bit, 128bit, 256bit and 512bit */ > > {8, 8, 8, 8, 16}, /* cost of storing SSE register > > in 32bit, 64bit, 128bit, 256bit and 512bit */ > > - {6, 6, 6, 10, 20}, /* cost of unaligned loads. */ > > + {8, 8, 8, 8, 16}, /* cost of unaligned loads. */ > > {8, 8, 8, 8, 16}, /* cost of unaligned stores. */ > > 2, 2, 4, /* cost of moving XMM,YMM,ZMM register */ > > 6, /* cost of moving SSE register to integer. */ > > @@ -2146,13 +2146,13 @@ struct processor_costs alderlake_cost = { > > {6, 6, 6}, /* cost of loading integer registers > > in QImode, HImode and SImode. > > Relative to reg-reg move (2). */ > > - {6, 6, 6}, /* cost of storing integer registers */ > > - {6, 6, 6, 10, 15}, /* cost of loading SSE register > > + {8, 8, 8}, /* cost of storing integer registers */ > > + {8, 8, 8, 10, 15}, /* cost of loading SSE register > > in 32bit, 64bit, 128bit, 256bit and 512bit */ > > - {6, 6, 6, 10, 15}, /* cost of storing SSE register > > + {8, 8, 8, 10, 15}, /* cost of storing SSE register > > in 32bit, 64bit, 128bit, 256bit and 512bit */ > > - {6, 6, 6, 10, 15}, /* cost of unaligned loads. */ > > - {6, 6, 6, 10, 15}, /* cost of unaligned storess. */ > > + {8, 8, 8, 10, 15}, /* cost of unaligned loads. */ > > + {8, 8, 8, 10, 15}, /* cost of unaligned storess. */ > > 2, 3, 4, /* cost of moving XMM,YMM,ZMM register */ > > 6, /* cost of moving SSE register to integer. */ > > 18, 6, /* Gather load static, per_elt. */ > > diff --git a/gcc/testsuite/gcc.target/i386/pr91446.c b/gcc/testsuite/gcc.target/i386/pr91446.c > > index 067bf43f698..0243ca3ea68 100644 > > --- a/gcc/testsuite/gcc.target/i386/pr91446.c > > +++ b/gcc/testsuite/gcc.target/i386/pr91446.c > > @@ -21,4 +21,4 @@ foo (unsigned long long width, unsigned long long height, > > bar (&t); > > } > > > > -/* { dg-final { scan-assembler-times "xmm\[0-9\]" 0 } } */ > > +/* { dg-final { scan-assembler-times "vmovdqa\[^\n\r\]*xmm\[0-9\]" 2 } } */ > > diff --git a/gcc/testsuite/gcc.target/i386/pr99881.c b/gcc/testsuite/gcc.target/i386/pr99881.c > > index a1ec1d1ba8a..3e087eb2ed7 100644 > > --- a/gcc/testsuite/gcc.target/i386/pr99881.c > > +++ b/gcc/testsuite/gcc.target/i386/pr99881.c > > @@ -1,7 +1,7 @@ > > /* PR target/99881. */ > > /* { dg-do compile { target { ! ia32 } } } */ > > /* { dg-options "-Ofast -march=skylake" } */ > > -/* { dg-final { scan-assembler-not "xmm\[0-9\]" } } */ > > +/* { dg-final { scan-assembler-not "xmm\[0-9\]" { xfail *-*-* } } } */ > > > > void > > foo (int* __restrict a, int n, int c) > > -- > > 2.17.1 > > > > Should we add some tests to verify improvements? We can take pr99881.c as a unit test. Ok for the trunk. > > -- > H.J. -- BR, Hongtao