[PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

[PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

[Hongtao Liu]

[-- Attachment #1: Type: text/plain, Size: 1332 bytes --]

Hi Jeff:
  The following patch adds forgotten avx512f fpclass instrinsics for
masked scalar operations.

Bootstrapped/regtested on x86_64-linux and i686-linux (on skylake-avx512),
ok for trunk?

Changelog:

gcc/
+2019-03-24 Hongtao Liu <hongtao.liu@intel.com>
+
+ PR target/89803
+ * config/i386/avx512dqintrin.h
+ (_mm_mask_fpclass_ss_mask,_mm_mask_fpclass_sd_mask):
+ New intrinsics.
+ * config/i386/i386-builtin.def
+ (__builtin_ia32_fpclassss_mask, _builtin_ia32_fpclasssd_mask):
+ New builtins.
+ * config/i386/sse.md
+ (define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
+ Modified with mask.

gcc/testsuite
+2019-03-24 Hongtao Liu <hongtao.liu@intel.com>
+
+ PR target/89803
+ * gcc.target/i386/avx-1.c (__builtin_ia32_fpclassss_mask,
+ __builtin_ia32_fpclasssd_mask): Define.
+ * gcc.target/i386/sse-13.c (__builtin_ia32_fpclassss_mask,
+ __builtin_ia32_fpclasssd_mask): Likewise.
+ * gcc.target/i386/sse-23.c (__builtin_ia32_fpclassss_mask)
+ (__builtin_ia32_fpclasssd_mask): Likewise.
+ * gcc.target/i386/avx512dq-vfpclassss-2.c: New.
+ * gcc.target/i386/avx512dq-vfpclasssd-2.c: Likewise.
+ * gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test):
+ Add test for _mm_mask_fpclass_ss_mask.
+ * gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test):
+ Add test for _mm_mask_fpclass_sd_mask.

-- 
BR,
Hongtao

[-- Attachment #2: mask_fpclasss[sd].diff --]
[-- Type: text/x-patch, Size: 14958 bytes --]

Index: gcc/ChangeLog
===================================================================
--- gcc/ChangeLog	(revision 271853)
+++ gcc/ChangeLog	(working copy)
@@ -4706,6 +4706,19 @@
 	reprocessing.  Always call df_analyze before fixing up debug bind
 	insns.
 
+2019-03-24 Hongtao Liu	<hongtao.liu@intel.com>
+
+	PR target/89803
+	* config/i386/avx512dqintrin.h
+	(_mm_mask_fpclass_ss_mask,_mm_mask_fpclass_sd_mask):
+	New intrinsics.
+	* config/i386/i386-builtin.def
+	(__builtin_ia32_fpclassss_mask, _builtin_ia32_fpclasssd_mask):
+	New builtins.
+	* config/i386/sse.md
+	(define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
+	Modified with mask.
+
 2019-03-23  Segher Boessenkool  <segher@kernel.crashing.org>
 
 	* config/rs6000/xmmintrin.h (_mm_movemask_pi8): Implement for 32-bit
Index: gcc/config/i386/avx512dqintrin.h
===================================================================
--- gcc/config/i386/avx512dqintrin.h	(revision 271853)
+++ gcc/config/i386/avx512dqintrin.h	(working copy)
@@ -1372,6 +1372,20 @@
   return (__mmask8) __builtin_ia32_fpclasssd ((__v2df) __A, __imm);
 }
 
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_fpclass_ss_mask (__mmask8 __U, __m128 __A, const int __imm)
+{
+  return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm, __U);
+}
+
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const int __imm)
+{
+  return (__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) __A, __imm, __U);
+}
+
 extern __inline __m512i
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm512_cvtt_roundpd_epi64 (__m512d __A, const int __R)
@@ -2623,6 +2637,12 @@
 #define _mm_fpclass_sd_mask(X, C)						\
   ((__mmask8) __builtin_ia32_fpclasssd ((__v2df) (__m128d) (X), (int) (C))) \
 
+#define _mm_mask_fpclass_ss_mask(X, C, U)					\
+  ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X), (int) (C)), (__mmask8) (U))
+
+#define _mm_mask_fpclass_sd_mask(X, C, U)					\
+  ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), (int) (C)), (__mmask8) (U))
+
 #define _mm512_mask_fpclass_pd_mask(u, X, C)                            \
   ((__mmask8) __builtin_ia32_fpclasspd512_mask ((__v8df) (__m512d) (X), \
 						(int) (C), (__mmask8)(u)))
Index: gcc/config/i386/i386-builtin.def
===================================================================
--- gcc/config/i386/i386-builtin.def	(revision 271853)
+++ gcc/config/i386/i386-builtin.def	(working copy)
@@ -2086,9 +2086,11 @@
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT)
+BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv2df_mask, "__builtin_ia32_fpclasssd_mask", IX86_BUILTIN_FPCLASSSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT)
+BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv4sf_mask, "__builtin_ia32_fpclassss_mask", IX86_BUILTIN_FPCLASSSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) UHI_FTYPE_V16QI)
 BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) USI_FTYPE_V32QI)
 BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) UQI_FTYPE_V8HI)
Index: gcc/config/i386/sse.md
===================================================================
--- gcc/config/i386/sse.md	(revision 271853)
+++ gcc/config/i386/sse.md	(working copy)
@@ -21327,7 +21327,7 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "avx512dq_vmfpclass<mode>"
+(define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
 	(and:<avx512fmaskmode>
 	  (unspec:<avx512fmaskmode>
@@ -21336,7 +21336,7 @@
 	    UNSPEC_FPCLASS)
 	  (const_int 1)))]
    "TARGET_AVX512DQ"
-   "vfpclass<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
+   "vfpclass<ssescalarmodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}";
   [(set_attr "type" "sse")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "evex")
Index: gcc/testsuite/ChangeLog
===================================================================
--- gcc/testsuite/ChangeLog	(revision 271853)
+++ gcc/testsuite/ChangeLog	(working copy)
@@ -2847,6 +2847,22 @@
 	* gfortran.dg/altreturn_10.f90: New test.
 	* gfortran.dg/whole_file_3.f90: Change dg-warning to dg-error.
 
+2019-03-24 Hongtao Liu <hongtao.liu@intel.com>
+
+	PR target/89803
+	* gcc.target/i386/avx-1.c (__builtin_ia32_fpclassss_mask,
+	__builtin_ia32_fpclasssd_mask):	Define.
+	* gcc.target/i386/sse-13.c (__builtin_ia32_fpclassss_mask,
+	__builtin_ia32_fpclasssd_mask):	Likewise.
+	* gcc.target/i386/sse-23.c (__builtin_ia32_fpclassss_mask)
+	(__builtin_ia32_fpclasssd_mask): Likewise.
+	* gcc.target/i386/avx512dq-vfpclassss-2.c: New.
+	* gcc.target/i386/avx512dq-vfpclasssd-2.c: Likewise.
+	* gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test):
+	Add test for _mm_mask_fpclass_ss_mask.
+	* gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test):
+	Add test for _mm_mask_fpclass_sd_mask.
+
 2019-03-22  Vladimir Makarov  <vmakarov@redhat.com>
 
 	PR rtl-optimization/89676
Index: gcc/testsuite/gcc.target/i386/avx-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx-1.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/avx-1.c	(working copy)
@@ -446,6 +446,8 @@
 #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E)
 #define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1)
 #define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1)
+#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U)
+#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U)
 #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C)
 #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C)
 #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D)
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c	(working copy)
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mavx512dq -O2" } */
 /* { dg-final { scan-assembler-times "vfpclasssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
 
 #include <immintrin.h>
 
@@ -11,4 +12,5 @@
 avx512dq_test (void)
 {
   m8 = _mm_fpclass_sd_mask (x128, 13);
+  m8 = _mm_mask_fpclass_sd_mask (m8, x128, 13);
 }
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c	(nonexistent)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c	(working copy)
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512dq" } */
+/* { dg-require-effective-target avx512dq } */
+
+#define AVX512DQ
+#include "avx512f-helper.h"
+
+#include <math.h>
+#include <limits.h>
+#include <float.h>
+#define SIZE (128 / 64)
+#include "avx512f-mask-type.h"
+
+#ifndef __FPCLASSSD__
+#define __FPCLASSSD__
+int check_fp_class_dp (double src, int imm)
+{
+  int qNaN_res = isnan (src);
+  int sNaN_res = isnan (src);
+  int Pzero_res = (src == 0.0);
+  int Nzero_res = (src == -0.0);
+  int PInf_res = (isinf (src) == 1);
+  int NInf_res = (isinf (src) == -1);
+  int Denorm_res = (fpclassify (src) == FP_SUBNORMAL);
+  int FinNeg_res = __builtin_finite (src) && (src < 0);
+
+  int result = (((imm & 1) && qNaN_res)
+		|| (((imm >> 1) & 1) && Pzero_res)
+		|| (((imm >> 2) & 1) && Nzero_res)
+		|| (((imm >> 3) & 1) && PInf_res)
+		|| (((imm >> 4) & 1) && NInf_res)
+		|| (((imm >> 5) & 1) && Denorm_res)
+		|| (((imm >> 6) & 1) && FinNeg_res)
+		|| (((imm >> 7) & 1) && sNaN_res));
+  return result;
+}
+#endif
+
+__mmask8
+CALC (double *s1, int imm)
+{
+  int i;
+  __mmask8 res = 0;
+
+  if (check_fp_class_dp(s1[0], imm))
+    res = res | 1;
+
+  return res;
+}
+
+void
+TEST (void)
+{
+  int i;
+  union128d src;
+  __mmask8 res1, res2, res_ref = 0;
+  __mmask8 mask = MASK_VALUE;
+
+  src.a[0] = 1.0 / 0.0;
+  for (i = 1; i < SIZE; i++)
+    {
+      src.a[i] = -24.43 + 0.6 * i;
+    }
+
+  res1 = _mm_fpclass_sd_mask (src.x, 0xFF);
+  res2 = _mm_mask_fpclass_sd_mask (mask, src.x, 0xFF);
+
+  res_ref = CALC (src.a, 0xFF);
+
+  if (res_ref != res1)
+    abort ();
+
+  if ((res_ref & mask) != res2)
+    abort ();
+}
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c	(working copy)
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mavx512dq -O2" } */
 /* { dg-final { scan-assembler-times "vfpclassss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclassss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
 
 #include <immintrin.h>
 
@@ -11,4 +12,5 @@
 avx512dq_test (void)
 {
   m8 = _mm_fpclass_ss_mask (x128, 13);
+  m8 = _mm_mask_fpclass_ss_mask (m8, x128, 13);
 }
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c	(nonexistent)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c	(working copy)
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512dq" } */
+/* { dg-require-effective-target avx512dq } */
+
+#define AVX512DQ
+#include "avx512f-helper.h"
+
+#include <math.h>
+#include <limits.h>
+#include <float.h>
+#include "avx512f-mask-type.h"
+#define SIZE (128 / 32)
+
+#ifndef __FPCLASSSS__
+#define __FPCLASSSS__
+int check_fp_class_sp (float src, int imm)
+{
+  int qNaN_res = isnan (src);
+  int sNaN_res = isnan (src);
+  int Pzero_res = (src == 0.0);
+  int Nzero_res = (src == -0.0);
+  int PInf_res = (isinf (src) == 1);
+  int NInf_res = (isinf (src) == -1);
+  int Denorm_res = (fpclassify (src) == FP_SUBNORMAL);
+  int FinNeg_res = __builtin_finite (src) && (src < 0);
+
+  int result = (((imm & 1) && qNaN_res)
+		|| (((imm >> 1) & 1) && Pzero_res)
+		|| (((imm >> 2) & 1) && Nzero_res)
+		|| (((imm >> 3) & 1) && PInf_res)
+		|| (((imm >> 4) & 1) && NInf_res)
+		|| (((imm >> 5) & 1) && Denorm_res)
+		|| (((imm >> 6) & 1) && FinNeg_res)
+		|| (((imm >> 7) & 1) && sNaN_res));
+  return result;
+}
+#endif
+
+__mmask8
+CALC (float *s1, int imm)
+{
+  int i;
+  __mmask8 res = 0;
+
+  if (check_fp_class_sp(s1[0], imm))
+    res = res | 1;
+
+  return res;
+}
+
+void
+TEST (void)
+{
+  int i;
+  union128 src;
+  __mmask8 res1, res2, res_ref = 0;
+  __mmask8 mask = MASK_VALUE;
+
+  src.a[0] = 1.0 / 0.0;
+  for (i = 1; i < SIZE; i++)
+    {
+      src.a[i] = -24.43 + 0.6 * i;
+    }
+
+  res1 = _mm_fpclass_ss_mask (src.x, 0xFF);
+  res2 = _mm_mask_fpclass_ss_mask (mask, src.x, 0xFF);
+
+
+  res_ref = CALC (src.a, 0xFF);
+
+  if (res_ref != res1)
+    abort ();
+
+  if ((mask & res_ref) != res2)
+    abort ();
+}
Index: gcc/testsuite/gcc.target/i386/sse-13.c
===================================================================
--- gcc/testsuite/gcc.target/i386/sse-13.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/sse-13.c	(working copy)
@@ -463,6 +463,8 @@
 #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E)
 #define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1)
 #define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1)
+#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U)
+#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U)
 #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C)
 #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C)
 #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D)
Index: gcc/testsuite/gcc.target/i386/sse-23.c
===================================================================
--- gcc/testsuite/gcc.target/i386/sse-23.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/sse-23.c	(working copy)
@@ -462,6 +462,8 @@
 #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E)
 #define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1)
 #define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1)
+#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U)
+#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U)
 #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C)
 #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C)
 #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D)

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

[Jakub Jelinek]

On Mon, Jun 03, 2019 at 06:01:40PM +0800, Hongtao Liu wrote:
>   The following patch adds forgotten avx512f fpclass instrinsics for
> masked scalar operations.
> 
> Bootstrapped/regtested on x86_64-linux and i686-linux (on skylake-avx512),
> ok for trunk?
> 
> Changelog:
> 
> gcc/
> +2019-03-24 Hongtao Liu <hongtao.liu@intel.com>
> +
> + PR target/89803
> + * config/i386/avx512dqintrin.h
> + (_mm_mask_fpclass_ss_mask,_mm_mask_fpclass_sd_mask):
> + New intrinsics.
> + * config/i386/i386-builtin.def
> + (__builtin_ia32_fpclassss_mask, _builtin_ia32_fpclasssd_mask):
> + New builtins.
> + * config/i386/sse.md
> + (define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
> + Modified with mask.

Given that the __builtin_ia32_fpclasss[sd] builtins are AVX512DQ only,
wouldn't it make more sense to remove the __builtin_ia32_fpclasss[sd]
builtins rather than keep them, adjust _mm_mask_fpclass_ss/_mm_mask_fpclass_sd
so that they use these new builtins instead of old and pass in -1 and
make sure we emit the same code as before for those intrinsics?

We have way too many ia32 builtins.

	Jakub

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

[Hongtao Liu]

[-- Attachment #1: Type: text/plain, Size: 1290 bytes --]

On Mon, Jun 3, 2019 at 7:06 PM Jakub Jelinek <jakub@redhat.com> wrote:
>
> On Mon, Jun 03, 2019 at 06:01:40PM +0800, Hongtao Liu wrote:
> >   The following patch adds forgotten avx512f fpclass instrinsics for
> > masked scalar operations.
> >
> > Bootstrapped/regtested on x86_64-linux and i686-linux (on skylake-avx512),
> > ok for trunk?
> >
> > Changelog:
> >
> > gcc/
> > +2019-03-24 Hongtao Liu <hongtao.liu@intel.com>
> > +
> > + PR target/89803
> > + * config/i386/avx512dqintrin.h
> > + (_mm_mask_fpclass_ss_mask,_mm_mask_fpclass_sd_mask):
> > + New intrinsics.
> > + * config/i386/i386-builtin.def
> > + (__builtin_ia32_fpclassss_mask, _builtin_ia32_fpclasssd_mask):
> > + New builtins.
> > + * config/i386/sse.md
> > + (define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
> > + Modified with mask.
>
> Given that the __builtin_ia32_fpclasss[sd] builtins are AVX512DQ only,
> wouldn't it make more sense to remove the __builtin_ia32_fpclasss[sd]
> builtins rather than keep them, adjust _mm_mask_fpclass_ss/_mm_mask_fpclass_sd
> so that they use these new builtins instead of old and pass in -1 and
> make sure we emit the same code as before for those intrinsics?
>
> We have way too many ia32 builtins.
>
>         Jakub

Yes, here is updated patch.

-- 
BR,
Hongtao

[-- Attachment #2: mask_fpclasss[sd]_v2.diff --]
[-- Type: text/x-patch, Size: 17974 bytes --]

Index: gcc/ChangeLog
===================================================================
--- gcc/ChangeLog	(revision 271853)
+++ gcc/ChangeLog	(working copy)
@@ -4706,6 +4706,26 @@
 	reprocessing.  Always call df_analyze before fixing up debug bind
 	insns.
 
+2019-03-24 Hongtao Liu	<hongtao.liu@intel.com>
+
+	PR target/89803
+	* config/i386/avx512dqintrin.h
+	(_mm_mask_fpclass_ss_mask,_mm_mask_fpclass_sd_mask):
+	New intrinsics.
+	(_mm_fpclass_ss_mask,_mm_fpclass_sd_mask):
+	Modified, use new builtins.
+	* config/i386/i386-builtin.def
+	(__builtin_ia32_fpclassss_mask, _builtin_ia32_fpclasssd_mask):
+	New builtins.
+	(__builtin_ia32_fpclassss, _builtin_ia32_fpclasssd): Deleted.
+	* config/i386/i386-builtin-types.def:
+	Delete relate types.
+	* config/i386/i386-expand.c:
+	Ditto.
+	* config/i386/sse.md
+	(define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
+	Modified with mask.
+
 2019-03-23  Segher Boessenkool  <segher@kernel.crashing.org>
 
 	* config/rs6000/xmmintrin.h (_mm_movemask_pi8): Implement for 32-bit
Index: gcc/config/i386/avx512dqintrin.h
===================================================================
--- gcc/config/i386/avx512dqintrin.h	(revision 271853)
+++ gcc/config/i386/avx512dqintrin.h	(working copy)
@@ -1362,7 +1362,7 @@
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_fpclass_ss_mask (__m128 __A, const int __imm)
 {
-  return (__mmask8) __builtin_ia32_fpclassss ((__v4sf) __A, __imm);
+  return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm, -1);
 }
 
 extern __inline __mmask8
@@ -1369,9 +1369,23 @@
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_fpclass_sd_mask (__m128d __A, const int __imm)
 {
-  return (__mmask8) __builtin_ia32_fpclasssd ((__v2df) __A, __imm);
+  return (__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) __A, __imm, -1);
 }
 
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_fpclass_ss_mask (__mmask8 __U, __m128 __A, const int __imm)
+{
+  return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm, __U);
+}
+
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const int __imm)
+{
+  return (__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) __A, __imm, __U);
+}
+
 extern __inline __m512i
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm512_cvtt_roundpd_epi64 (__m512d __A, const int __R)
@@ -2618,11 +2632,17 @@
     (__mmask16)(U)))
 
 #define _mm_fpclass_ss_mask(X, C)						\
-  ((__mmask8) __builtin_ia32_fpclassss ((__v4sf) (__m128) (X), (int) (C)))  \
+  ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X), (int) (C), (__mmask8) (-1))) \
 
 #define _mm_fpclass_sd_mask(X, C)						\
-  ((__mmask8) __builtin_ia32_fpclasssd ((__v2df) (__m128d) (X), (int) (C))) \
+  ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), (int) (C), (__mmask8) (-1))) \
 
+#define _mm_mask_fpclass_ss_mask(X, C, U)					\
+  ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X), (int) (C), (__mmask8) (U)))
+
+#define _mm_mask_fpclass_sd_mask(X, C, U)					\
+  ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), (int) (C), (__mmask8) (U)))
+
 #define _mm512_mask_fpclass_pd_mask(u, X, C)                            \
   ((__mmask8) __builtin_ia32_fpclasspd512_mask ((__v8df) (__m512d) (X), \
 						(int) (C), (__mmask8)(u)))
Index: gcc/config/i386/i386-builtin-types.def
===================================================================
--- gcc/config/i386/i386-builtin-types.def	(revision 271853)
+++ gcc/config/i386/i386-builtin-types.def	(working copy)
@@ -964,11 +964,9 @@
 DEF_FUNCTION_TYPE (QI, V8DF, INT)
 DEF_FUNCTION_TYPE (QI, V4DF, INT)
 DEF_FUNCTION_TYPE (QI, V4DF, V4DF, INT, UQI)
-DEF_FUNCTION_TYPE (QI, V2DF, INT)
 DEF_FUNCTION_TYPE (HI, V16SF, INT)
 DEF_FUNCTION_TYPE (QI, V8SF, INT)
 DEF_FUNCTION_TYPE (QI, V8SF, V8SF, INT, UQI)
-DEF_FUNCTION_TYPE (QI, V4SF, INT)
 DEF_FUNCTION_TYPE (QI, V8DF, INT, UQI)
 DEF_FUNCTION_TYPE (QI, V4DF, INT, UQI)
 DEF_FUNCTION_TYPE (QI, V2DF, INT, UQI)
Index: gcc/config/i386/i386-builtin.def
===================================================================
--- gcc/config/i386/i386-builtin.def	(revision 271853)
+++ gcc/config/i386/i386-builtin.def	(working copy)
@@ -2085,10 +2085,10 @@
 BDESC (OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI)
-BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT)
+BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv2df_mask, "__builtin_ia32_fpclasssd_mask", IX86_BUILTIN_FPCLASSSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI)
-BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT)
+BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv4sf_mask, "__builtin_ia32_fpclassss_mask", IX86_BUILTIN_FPCLASSSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) UHI_FTYPE_V16QI)
 BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) USI_FTYPE_V32QI)
 BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) UQI_FTYPE_V8HI)
Index: gcc/config/i386/i386-expand.c
===================================================================
--- gcc/config/i386/i386-expand.c	(revision 271853)
+++ gcc/config/i386/i386-expand.c	(working copy)
@@ -9272,8 +9272,6 @@
     case V4DI_FTYPE_V4DI_INT:
     case V2DI_FTYPE_V4DI_INT:
     case V4DI_FTYPE_V8DI_INT:
-    case QI_FTYPE_V4SF_INT:
-    case QI_FTYPE_V2DF_INT:
     case UQI_FTYPE_UQI_UQI_CONST:
     case UHI_FTYPE_UHI_UQI:
     case USI_FTYPE_USI_UQI:
Index: gcc/config/i386/sse.md
===================================================================
--- gcc/config/i386/sse.md	(revision 271853)
+++ gcc/config/i386/sse.md	(working copy)
@@ -21327,7 +21327,7 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "avx512dq_vmfpclass<mode>"
+(define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
 	(and:<avx512fmaskmode>
 	  (unspec:<avx512fmaskmode>
@@ -21336,7 +21336,7 @@
 	    UNSPEC_FPCLASS)
 	  (const_int 1)))]
    "TARGET_AVX512DQ"
-   "vfpclass<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
+   "vfpclass<ssescalarmodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}";
   [(set_attr "type" "sse")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "evex")
Index: gcc/testsuite/ChangeLog
===================================================================
--- gcc/testsuite/ChangeLog	(revision 271853)
+++ gcc/testsuite/ChangeLog	(working copy)
@@ -2847,6 +2847,22 @@
 	* gfortran.dg/altreturn_10.f90: New test.
 	* gfortran.dg/whole_file_3.f90: Change dg-warning to dg-error.
 
+2019-03-24 Hongtao Liu <hongtao.liu@intel.com>
+
+	PR target/89803
+	* gcc.target/i386/avx-1.c
+	(__builtin_ia32_fpclasss[sd]): Replaced with builtin_ia32_fpclasss[sd]_mask.
+	* gcc.target/i386/sse-13.c:
+	(__builtin_ia32_fpclasss[sd]): Likewise.
+	* gcc.target/i386/sse-23.c
+	(__builtin_ia32_fpclasss[sd]): Likewise.
+	* gcc.target/i386/avx512dq-vfpclassss-2.c: New.
+	* gcc.target/i386/avx512dq-vfpclasssd-2.c: Likewise.
+	* gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test):
+	Add test for _mm_mask_fpclass_ss_mask.
+	* gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test):
+	Add test for _mm_mask_fpclass_sd_mask.
+
 2019-03-22  Vladimir Makarov  <vmakarov@redhat.com>
 
 	PR rtl-optimization/89676
Index: gcc/testsuite/gcc.target/i386/avx-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx-1.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/avx-1.c	(working copy)
@@ -444,8 +444,8 @@
 #define __builtin_ia32_inserti32x8_mask(A, B, F, D, E) __builtin_ia32_inserti32x8_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf64x2_512_mask(A, B, F, D, E) __builtin_ia32_insertf64x2_512_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E)
-#define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1)
-#define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1)
+#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U)
+#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U)
 #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C)
 #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C)
 #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D)
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c	(working copy)
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mavx512dq -O2" } */
 /* { dg-final { scan-assembler-times "vfpclasssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
 
 #include <immintrin.h>
 
@@ -11,4 +12,5 @@
 avx512dq_test (void)
 {
   m8 = _mm_fpclass_sd_mask (x128, 13);
+  m8 = _mm_mask_fpclass_sd_mask (m8, x128, 13);
 }
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c	(nonexistent)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c	(working copy)
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512dq" } */
+/* { dg-require-effective-target avx512dq } */
+
+#define AVX512DQ
+#include "avx512f-helper.h"
+
+#include <math.h>
+#include <limits.h>
+#include <float.h>
+#define SIZE (128 / 64)
+#include "avx512f-mask-type.h"
+
+#ifndef __FPCLASSSD__
+#define __FPCLASSSD__
+int check_fp_class_dp (double src, int imm)
+{
+  int qNaN_res = isnan (src);
+  int sNaN_res = isnan (src);
+  int Pzero_res = (src == 0.0);
+  int Nzero_res = (src == -0.0);
+  int PInf_res = (isinf (src) == 1);
+  int NInf_res = (isinf (src) == -1);
+  int Denorm_res = (fpclassify (src) == FP_SUBNORMAL);
+  int FinNeg_res = __builtin_finite (src) && (src < 0);
+
+  int result = (((imm & 1) && qNaN_res)
+		|| (((imm >> 1) & 1) && Pzero_res)
+		|| (((imm >> 2) & 1) && Nzero_res)
+		|| (((imm >> 3) & 1) && PInf_res)
+		|| (((imm >> 4) & 1) && NInf_res)
+		|| (((imm >> 5) & 1) && Denorm_res)
+		|| (((imm >> 6) & 1) && FinNeg_res)
+		|| (((imm >> 7) & 1) && sNaN_res));
+  return result;
+}
+#endif
+
+__mmask8
+CALC (double *s1, int imm)
+{
+  int i;
+  __mmask8 res = 0;
+
+  if (check_fp_class_dp(s1[0], imm))
+    res = res | 1;
+
+  return res;
+}
+
+void
+TEST (void)
+{
+  int i;
+  union128d src;
+  __mmask8 res1, res2, res_ref = 0;
+  __mmask8 mask = MASK_VALUE;
+
+  src.a[0] = 1.0 / 0.0;
+  for (i = 1; i < SIZE; i++)
+    {
+      src.a[i] = -24.43 + 0.6 * i;
+    }
+
+  res1 = _mm_fpclass_sd_mask (src.x, 0xFF);
+  res2 = _mm_mask_fpclass_sd_mask (mask, src.x, 0xFF);
+
+  res_ref = CALC (src.a, 0xFF);
+
+  if (res_ref != res1)
+    abort ();
+
+  if ((res_ref & mask) != res2)
+    abort ();
+}
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c	(working copy)
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mavx512dq -O2" } */
 /* { dg-final { scan-assembler-times "vfpclassss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclassss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
 
 #include <immintrin.h>
 
@@ -11,4 +12,5 @@
 avx512dq_test (void)
 {
   m8 = _mm_fpclass_ss_mask (x128, 13);
+  m8 = _mm_mask_fpclass_ss_mask (m8, x128, 13);
 }
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c	(nonexistent)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c	(working copy)
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512dq" } */
+/* { dg-require-effective-target avx512dq } */
+
+#define AVX512DQ
+#include "avx512f-helper.h"
+
+#include <math.h>
+#include <limits.h>
+#include <float.h>
+#include "avx512f-mask-type.h"
+#define SIZE (128 / 32)
+
+#ifndef __FPCLASSSS__
+#define __FPCLASSSS__
+int check_fp_class_sp (float src, int imm)
+{
+  int qNaN_res = isnan (src);
+  int sNaN_res = isnan (src);
+  int Pzero_res = (src == 0.0);
+  int Nzero_res = (src == -0.0);
+  int PInf_res = (isinf (src) == 1);
+  int NInf_res = (isinf (src) == -1);
+  int Denorm_res = (fpclassify (src) == FP_SUBNORMAL);
+  int FinNeg_res = __builtin_finite (src) && (src < 0);
+
+  int result = (((imm & 1) && qNaN_res)
+		|| (((imm >> 1) & 1) && Pzero_res)
+		|| (((imm >> 2) & 1) && Nzero_res)
+		|| (((imm >> 3) & 1) && PInf_res)
+		|| (((imm >> 4) & 1) && NInf_res)
+		|| (((imm >> 5) & 1) && Denorm_res)
+		|| (((imm >> 6) & 1) && FinNeg_res)
+		|| (((imm >> 7) & 1) && sNaN_res));
+  return result;
+}
+#endif
+
+__mmask8
+CALC (float *s1, int imm)
+{
+  int i;
+  __mmask8 res = 0;
+
+  if (check_fp_class_sp(s1[0], imm))
+    res = res | 1;
+
+  return res;
+}
+
+void
+TEST (void)
+{
+  int i;
+  union128 src;
+  __mmask8 res1, res2, res_ref = 0;
+  __mmask8 mask = MASK_VALUE;
+
+  src.a[0] = 1.0 / 0.0;
+  for (i = 1; i < SIZE; i++)
+    {
+      src.a[i] = -24.43 + 0.6 * i;
+    }
+
+  res1 = _mm_fpclass_ss_mask (src.x, 0xFF);
+  res2 = _mm_mask_fpclass_ss_mask (mask, src.x, 0xFF);
+
+
+  res_ref = CALC (src.a, 0xFF);
+
+  if (res_ref != res1)
+    abort ();
+
+  if ((mask & res_ref) != res2)
+    abort ();
+}
Index: gcc/testsuite/gcc.target/i386/sse-13.c
===================================================================
--- gcc/testsuite/gcc.target/i386/sse-13.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/sse-13.c	(working copy)
@@ -461,8 +461,8 @@
 #define __builtin_ia32_inserti32x8_mask(A, B, F, D, E) __builtin_ia32_inserti32x8_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf64x2_512_mask(A, B, F, D, E) __builtin_ia32_insertf64x2_512_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E)
-#define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1)
-#define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1)
+#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U)
+#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U)
 #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C)
 #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C)
 #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D)
Index: gcc/testsuite/gcc.target/i386/sse-23.c
===================================================================
--- gcc/testsuite/gcc.target/i386/sse-23.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/sse-23.c	(working copy)
@@ -460,8 +460,8 @@
 #define __builtin_ia32_inserti32x8_mask(A, B, F, D, E) __builtin_ia32_inserti32x8_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf64x2_512_mask(A, B, F, D, E) __builtin_ia32_insertf64x2_512_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E)
-#define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1)
-#define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1)
+#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U)
+#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U)
 #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C)
 #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C)
 #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D)

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

[Jakub Jelinek]

On Tue, Jun 04, 2019 at 03:38:08PM +0800, Hongtao Liu wrote:
> --- gcc/ChangeLog	(revision 271853)
> +++ gcc/ChangeLog	(working copy)
> @@ -4706,6 +4706,26 @@
>  	reprocessing.  Always call df_analyze before fixing up debug bind
>  	insns.
>  
> +2019-03-24 Hongtao Liu	<hongtao.liu@intel.com>

name should be separated from date and email by 2 spaces on each side,
you have just one space before and a tab after.

> +
> +	PR target/89803
> +	* config/i386/avx512dqintrin.h
> +	(_mm_mask_fpclass_ss_mask,_mm_mask_fpclass_sd_mask):
> +	New intrinsics.

There should be space after comma, and a line break should be there
only when it will not fit, so:

+	* config/i386/avx512dqintrin.h (_mm_mask_fpclass_ss_mask,
+	_mm_mask_fpclass_sd_mask): New intrinsics.

> +	(_mm_fpclass_ss_mask,_mm_fpclass_sd_mask):
> +	Modified, use new builtins.

Similarly.

> +	* config/i386/i386-builtin.def
> +	(__builtin_ia32_fpclassss_mask, _builtin_ia32_fpclasssd_mask):
> +	New builtins.

Again.

> +	(__builtin_ia32_fpclassss, _builtin_ia32_fpclasssd): Deleted.
> +	* config/i386/i386-builtin-types.def:
> +	Delete relate types.

You should say what exactly you've deleted, so

+	* config/i386/i386-builtin-types.def (QI_FTYPE_V2DF_INT,
+	QI_FTYPE_V4SF_INT): Remove.

> +	* config/i386/i386-expand.c:
> +	Ditto.

Mention what you've changed, so

+	* config/i386/i386-expand.c (ix86_expand_args_builtin): Remove
+	QI_FTYPE_V2DF_INT and QI_FTYPE_V4SF_INT cases.

> +	* config/i386/sse.md
> +	(define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
> +	Modified with mask.

That is not what you've done.

+	* config/i386/sse.md (avx512dq_vmfpclass<mode>): Rename to ...
+	(avx512dq_vmfpclass<mode><mask_scalar_merge_name>): ... this.  Add
+	<mask_scalar_merge_operand3> to insn template.

> --- gcc/config/i386/avx512dqintrin.h	(revision 271853)
> +++ gcc/config/i386/avx512dqintrin.h	(working copy)
> @@ -1362,7 +1362,7 @@
>  __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
>  _mm_fpclass_ss_mask (__m128 __A, const int __imm)
>  {
> -  return (__mmask8) __builtin_ia32_fpclassss ((__v4sf) __A, __imm);
> +  return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm, -1);

Most other avx512*.h code uses explicit (__mmaskN) -1 instead of just -1, so
perhaps for consistency use:
+  return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm,
+						    (_mmask8) -1);
?

>  }
>  
>  extern __inline __mmask8
> @@ -1369,9 +1369,23 @@
>  __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
>  _mm_fpclass_sd_mask (__m128d __A, const int __imm)
>  {
> -  return (__mmask8) __builtin_ia32_fpclasssd ((__v2df) __A, __imm);
> +  return (__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) __A, __imm, -1);
>  }

Likewise.

>  #define _mm_fpclass_ss_mask(X, C)						\
> -  ((__mmask8) __builtin_ia32_fpclassss ((__v4sf) (__m128) (X), (int) (C)))  \
> +  ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X), (int) (C), (__mmask8) (-1))) \
>  
>  #define _mm_fpclass_sd_mask(X, C)						\
> -  ((__mmask8) __builtin_ia32_fpclasssd ((__v2df) (__m128d) (X), (int) (C))) \
> +  ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), (int) (C), (__mmask8) (-1))) \
>  
> +#define _mm_mask_fpclass_ss_mask(X, C, U)					\
> +  ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X), (int) (C), (__mmask8) (U)))
> +
> +#define _mm_mask_fpclass_sd_mask(X, C, U)					\
> +  ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), (int) (C), (__mmask8) (U)))

Too long lines.

> +2019-03-24 Hongtao Liu <hongtao.liu@intel.com>
> +
> +	PR target/89803
> +	* gcc.target/i386/avx-1.c
> +	(__builtin_ia32_fpclasss[sd]): Replaced with builtin_ia32_fpclasss[sd]_mask.
> +	* gcc.target/i386/sse-13.c:
> +	(__builtin_ia32_fpclasss[sd]): Likewise.
> +	* gcc.target/i386/sse-23.c
> +	(__builtin_ia32_fpclasss[sd]): Likewise.

Similar problems in this ChangeLog as in gcc/ChangeLog, you don't want a
linebreak after the filename if the function name can fit in, too long line
too, sse-13.c has an extra : after it and I believe we don't allow wildcards
in the function names between
()s, so it should be:
+	* gcc.target/i386/avx-1.c (__builtin_ia32_fpclassss,
+	__builtin_ia32_fpclasssd): Remove.
+	(__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
etc.

	Jakub

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

[Hongtao Liu]

[-- Attachment #1: Type: text/plain, Size: 8179 bytes --]

On Tue, Jun 4, 2019 at 3:59 PM Jakub Jelinek <jakub@redhat.com> wrote:
>
> On Tue, Jun 04, 2019 at 03:38:08PM +0800, Hongtao Liu wrote:
> > --- gcc/ChangeLog     (revision 271853)
> > +++ gcc/ChangeLog     (working copy)
> > @@ -4706,6 +4706,26 @@
> >       reprocessing.  Always call df_analyze before fixing up debug bind
> >       insns.
> >
> > +2019-03-24 Hongtao Liu       <hongtao.liu@intel.com>
>
> name should be separated from date and email by 2 spaces on each side,
> you have just one space before and a tab after.
>
> > +
> > +     PR target/89803
> > +     * config/i386/avx512dqintrin.h
> > +     (_mm_mask_fpclass_ss_mask,_mm_mask_fpclass_sd_mask):
> > +     New intrinsics.
>
> There should be space after comma, and a line break should be there
> only when it will not fit, so:
>
> +       * config/i386/avx512dqintrin.h (_mm_mask_fpclass_ss_mask,
> +       _mm_mask_fpclass_sd_mask): New intrinsics.
>
> > +     (_mm_fpclass_ss_mask,_mm_fpclass_sd_mask):
> > +     Modified, use new builtins.
>
> Similarly.
>
> > +     * config/i386/i386-builtin.def
> > +     (__builtin_ia32_fpclassss_mask, _builtin_ia32_fpclasssd_mask):
> > +     New builtins.
>
> Again.
>
> > +     (__builtin_ia32_fpclassss, _builtin_ia32_fpclasssd): Deleted.
> > +     * config/i386/i386-builtin-types.def:
> > +     Delete relate types.
>
> You should say what exactly you've deleted, so
>
> +       * config/i386/i386-builtin-types.def (QI_FTYPE_V2DF_INT,
> +       QI_FTYPE_V4SF_INT): Remove.
>
> > +     * config/i386/i386-expand.c:
> > +     Ditto.
>
> Mention what you've changed, so
>
> +       * config/i386/i386-expand.c (ix86_expand_args_builtin): Remove
> +       QI_FTYPE_V2DF_INT and QI_FTYPE_V4SF_INT cases.
>
> > +     * config/i386/sse.md
> > +     (define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
> > +     Modified with mask.
>
> That is not what you've done.
>
> +       * config/i386/sse.md (avx512dq_vmfpclass<mode>): Rename to ...
> +       (avx512dq_vmfpclass<mode><mask_scalar_merge_name>): ... this.  Add
> +       <mask_scalar_merge_operand3> to insn template.
>
> > --- gcc/config/i386/avx512dqintrin.h  (revision 271853)
> > +++ gcc/config/i386/avx512dqintrin.h  (working copy)
> > @@ -1362,7 +1362,7 @@
> >  __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> >  _mm_fpclass_ss_mask (__m128 __A, const int __imm)
> >  {
> > -  return (__mmask8) __builtin_ia32_fpclassss ((__v4sf) __A, __imm);
> > +  return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm, -1);
>
> Most other avx512*.h code uses explicit (__mmaskN) -1 instead of just -1, so
> perhaps for consistency use:
> +  return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm,
> +                                                   (_mmask8) -1);
> ?
>
> >  }
> >
> >  extern __inline __mmask8
> > @@ -1369,9 +1369,23 @@
> >  __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> >  _mm_fpclass_sd_mask (__m128d __A, const int __imm)
> >  {
> > -  return (__mmask8) __builtin_ia32_fpclasssd ((__v2df) __A, __imm);
> > +  return (__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) __A, __imm, -1);
> >  }
>
> Likewise.
>
> >  #define _mm_fpclass_ss_mask(X, C)                                            \
> > -  ((__mmask8) __builtin_ia32_fpclassss ((__v4sf) (__m128) (X), (int) (C)))  \
> > +  ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X), (int) (C), (__mmask8) (-1))) \
> >
> >  #define _mm_fpclass_sd_mask(X, C)                                            \
> > -  ((__mmask8) __builtin_ia32_fpclasssd ((__v2df) (__m128d) (X), (int) (C))) \
> > +  ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), (int) (C), (__mmask8) (-1))) \
> >
> > +#define _mm_mask_fpclass_ss_mask(X, C, U)                                    \
> > +  ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X), (int) (C), (__mmask8) (U)))
> > +
> > +#define _mm_mask_fpclass_sd_mask(X, C, U)                                    \
> > +  ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), (int) (C), (__mmask8) (U)))
>
> Too long lines.
>
> > +2019-03-24 Hongtao Liu <hongtao.liu@intel.com>
> > +
> > +     PR target/89803
> > +     * gcc.target/i386/avx-1.c
> > +     (__builtin_ia32_fpclasss[sd]): Replaced with builtin_ia32_fpclasss[sd]_mask.
> > +     * gcc.target/i386/sse-13.c:
> > +     (__builtin_ia32_fpclasss[sd]): Likewise.
> > +     * gcc.target/i386/sse-23.c
> > +     (__builtin_ia32_fpclasss[sd]): Likewise.
>
> Similar problems in this ChangeLog as in gcc/ChangeLog, you don't want a
> linebreak after the filename if the function name can fit in, too long line
> too, sse-13.c has an extra : after it and I believe we don't allow wildcards
> in the function names between
> ()s, so it should be:
> +       * gcc.target/i386/avx-1.c (__builtin_ia32_fpclassss,
> +       __builtin_ia32_fpclasssd): Remove.
> +       (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
> etc.
>
>         Jakub

Thanks for reminding, Here is updated:

Index: gcc/ChangeLog
===================================================================
--- gcc/ChangeLog (revision 271853)
+++ gcc/ChangeLog (working copy)
@@ -4706,6 +4706,24 @@
  reprocessing.  Always call df_analyze before fixing up debug bind
  insns.

+2019-03-24  Hongtao Liu  <hongtao.liu@intel.com>
+
+ PR target/89803
+ * config/i386/avx512dqintrin.h (_mm_mask_fpclass_ss_mask,
+ _mm_mask_fpclass_sd_mask): New intrinsics.
+ (_mm_fpclass_ss_mask, _mm_fpclass_sd_mask): Modified, use new builtins.
+ * config/i386/i386-builtin.def
+ (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask):
+ New builtins.
+ (__builtin_ia32_fpclassss, __builtin_ia32_fpclasssd): Deleted.
+ * config/i386/i386-builtin-types.def (DEF_FUNCTION_TYPE (QI, V2DF, INT),
+ DEF_FUNCTION_TYPE (QI, V4SF, INT)): Deleted.
+ * config/i386/i386-expand.c (case QI_FTYPE_V4SF_INT,
+ case QI_FTYPE_V2SF_INT): Ditto.
+ * config/i386/sse.md
+ (define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
+ Extended to insnstructions with mask operands.
+

Index: gcc/config/i386/avx512dqintrin.h
===================================================================
--- gcc/config/i386/avx512dqintrin.h (revision 271853)
+++ gcc/config/i386/avx512dqintrin.h (working copy)
@@ -1362,7 +1362,8 @@
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_fpclass_ss_mask (__m128 __A, const int __imm)
 {
-  return (__mmask8) __builtin_ia32_fpclassss ((__v4sf) __A, __imm);
+  return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm,
+    (__mmask8) -1);
 }

 extern __inline __mmask8
@@ -1369,9 +1370,24 @@
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_fpclass_sd_mask (__m128d __A, const int __imm)
 {
-  return (__mmask8) __builtin_ia32_fpclasssd ((__v2df) __A, __imm);
+  return (__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) __A, __imm,
+    (__mmask8) -1);
 }

Index: gcc/testsuite/ChangeLog
===================================================================
--- gcc/testsuite/ChangeLog (revision 271853)
+++ gcc/testsuite/ChangeLog (working copy)
@@ -2847,6 +2847,25 @@
  * gfortran.dg/altreturn_10.f90: New test.
  * gfortran.dg/whole_file_3.f90: Change dg-warning to dg-error.

+2019-03-24 Hongtao Liu <hongtao.liu@intel.com>
+
+ PR target/89803
+ * gcc.target/i386/avx-1.c (__builtin_ia32_fpclasssss,
+ __builtin_ia32_fpclasssd): Removed.
+ (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
+ * gcc.target/i386/sse-13.c (__builtin_ia32_fpclasssss,
+ __builtin_ia32_fpclasssd): Removed.
+ (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
+ * gcc.target/i386/sse-23.c (__builtin_ia32_fpclasssss,
+ __builtin_ia32_fpclasssd): Removed.
+ (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
+ * gcc.target/i386/avx512dq-vfpclassss-2.c: New.
+ * gcc.target/i386/avx512dq-vfpclasssd-2.c: New.
+ * gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test):
+ Add test for _mm_mask_fpclass_ss_mask.
+ * gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test):
+ Add test for _mm_mask_fpclass_sd_mask.
+
-- 
BR,
Hongtao

[-- Attachment #2: mask_fpclasss[sd]_v3.diff --]
[-- Type: text/x-patch, Size: 18585 bytes --]

Index: gcc/ChangeLog
===================================================================
--- gcc/ChangeLog	(revision 271853)
+++ gcc/ChangeLog	(working copy)
@@ -4706,6 +4706,24 @@
 	reprocessing.  Always call df_analyze before fixing up debug bind
 	insns.
 
+2019-03-24  Hongtao Liu  <hongtao.liu@intel.com>
+
+	PR target/89803
+	* config/i386/avx512dqintrin.h (_mm_mask_fpclass_ss_mask,
+	_mm_mask_fpclass_sd_mask): New intrinsics.
+	(_mm_fpclass_ss_mask, _mm_fpclass_sd_mask): Modified, use new builtins.
+	* config/i386/i386-builtin.def
+	(__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask):
+	New builtins.
+	(__builtin_ia32_fpclassss, __builtin_ia32_fpclasssd): Deleted.
+	* config/i386/i386-builtin-types.def (DEF_FUNCTION_TYPE (QI, V2DF, INT),
+	DEF_FUNCTION_TYPE (QI, V4SF, INT)): Deleted.
+	* config/i386/i386-expand.c (case QI_FTYPE_V4SF_INT,
+	case QI_FTYPE_V2SF_INT): Ditto.
+	* config/i386/sse.md
+	(define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
+	Extended to insnstructions with mask operands.
+
 2019-03-23  Segher Boessenkool  <segher@kernel.crashing.org>
 
 	* config/rs6000/xmmintrin.h (_mm_movemask_pi8): Implement for 32-bit
Index: gcc/config/i386/avx512dqintrin.h
===================================================================
--- gcc/config/i386/avx512dqintrin.h	(revision 271853)
+++ gcc/config/i386/avx512dqintrin.h	(working copy)
@@ -1362,7 +1362,8 @@
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_fpclass_ss_mask (__m128 __A, const int __imm)
 {
-  return (__mmask8) __builtin_ia32_fpclassss ((__v4sf) __A, __imm);
+  return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm,
+						   (__mmask8) -1);
 }
 
 extern __inline __mmask8
@@ -1369,9 +1370,24 @@
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_fpclass_sd_mask (__m128d __A, const int __imm)
 {
-  return (__mmask8) __builtin_ia32_fpclasssd ((__v2df) __A, __imm);
+  return (__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) __A, __imm,
+						   (__mmask8) -1);
 }
 
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_fpclass_ss_mask (__mmask8 __U, __m128 __A, const int __imm)
+{
+  return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm, __U);
+}
+
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const int __imm)
+{
+  return (__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) __A, __imm, __U);
+}
+
 extern __inline __m512i
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm512_cvtt_roundpd_epi64 (__m512d __A, const int __R)
@@ -2617,12 +2633,22 @@
     (__v16si)(__m512i)_mm512_setzero_si512 (),\
     (__mmask16)(U)))
 
-#define _mm_fpclass_ss_mask(X, C)						\
-  ((__mmask8) __builtin_ia32_fpclassss ((__v4sf) (__m128) (X), (int) (C)))  \
+#define _mm_fpclass_ss_mask(X, C)					\
+  ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X),	\
+					     (int) (C), (__mmask8) (-1))) \
 
-#define _mm_fpclass_sd_mask(X, C)						\
-  ((__mmask8) __builtin_ia32_fpclasssd ((__v2df) (__m128d) (X), (int) (C))) \
+#define _mm_fpclass_sd_mask(X, C)					\
+  ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X),	\
+					     (int) (C), (__mmask8) (-1))) \
 
+#define _mm_mask_fpclass_ss_mask(X, C, U)				\
+  ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X),	\
+					     (int) (C), (__mmask8) (U)))
+
+#define _mm_mask_fpclass_sd_mask(X, C, U)				\
+  ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X),	\
+					     (int) (C), (__mmask8) (U)))
+
 #define _mm512_mask_fpclass_pd_mask(u, X, C)                            \
   ((__mmask8) __builtin_ia32_fpclasspd512_mask ((__v8df) (__m512d) (X), \
 						(int) (C), (__mmask8)(u)))
Index: gcc/config/i386/i386-builtin-types.def
===================================================================
--- gcc/config/i386/i386-builtin-types.def	(revision 271853)
+++ gcc/config/i386/i386-builtin-types.def	(working copy)
@@ -964,11 +964,9 @@
 DEF_FUNCTION_TYPE (QI, V8DF, INT)
 DEF_FUNCTION_TYPE (QI, V4DF, INT)
 DEF_FUNCTION_TYPE (QI, V4DF, V4DF, INT, UQI)
-DEF_FUNCTION_TYPE (QI, V2DF, INT)
 DEF_FUNCTION_TYPE (HI, V16SF, INT)
 DEF_FUNCTION_TYPE (QI, V8SF, INT)
 DEF_FUNCTION_TYPE (QI, V8SF, V8SF, INT, UQI)
-DEF_FUNCTION_TYPE (QI, V4SF, INT)
 DEF_FUNCTION_TYPE (QI, V8DF, INT, UQI)
 DEF_FUNCTION_TYPE (QI, V4DF, INT, UQI)
 DEF_FUNCTION_TYPE (QI, V2DF, INT, UQI)
Index: gcc/config/i386/i386-builtin.def
===================================================================
--- gcc/config/i386/i386-builtin.def	(revision 271853)
+++ gcc/config/i386/i386-builtin.def	(working copy)
@@ -2085,10 +2085,10 @@
 BDESC (OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI)
-BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT)
+BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv2df_mask, "__builtin_ia32_fpclasssd_mask", IX86_BUILTIN_FPCLASSSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI)
-BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT)
+BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv4sf_mask, "__builtin_ia32_fpclassss_mask", IX86_BUILTIN_FPCLASSSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI)
 BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) UHI_FTYPE_V16QI)
 BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) USI_FTYPE_V32QI)
 BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) UQI_FTYPE_V8HI)
Index: gcc/config/i386/i386-expand.c
===================================================================
--- gcc/config/i386/i386-expand.c	(revision 271853)
+++ gcc/config/i386/i386-expand.c	(working copy)
@@ -9272,8 +9272,6 @@
     case V4DI_FTYPE_V4DI_INT:
     case V2DI_FTYPE_V4DI_INT:
     case V4DI_FTYPE_V8DI_INT:
-    case QI_FTYPE_V4SF_INT:
-    case QI_FTYPE_V2DF_INT:
     case UQI_FTYPE_UQI_UQI_CONST:
     case UHI_FTYPE_UHI_UQI:
     case USI_FTYPE_USI_UQI:
Index: gcc/config/i386/sse.md
===================================================================
--- gcc/config/i386/sse.md	(revision 271853)
+++ gcc/config/i386/sse.md	(working copy)
@@ -21327,7 +21327,7 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "avx512dq_vmfpclass<mode>"
+(define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
 	(and:<avx512fmaskmode>
 	  (unspec:<avx512fmaskmode>
@@ -21336,7 +21336,7 @@
 	    UNSPEC_FPCLASS)
 	  (const_int 1)))]
    "TARGET_AVX512DQ"
-   "vfpclass<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
+   "vfpclass<ssescalarmodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}";
   [(set_attr "type" "sse")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "evex")
Index: gcc/testsuite/ChangeLog
===================================================================
--- gcc/testsuite/ChangeLog	(revision 271853)
+++ gcc/testsuite/ChangeLog	(working copy)
@@ -2847,6 +2847,25 @@
 	* gfortran.dg/altreturn_10.f90: New test.
 	* gfortran.dg/whole_file_3.f90: Change dg-warning to dg-error.
 
+2019-03-24  Hongtao Liu  <hongtao.liu@intel.com>
+
+	PR target/89803
+	* gcc.target/i386/avx-1.c (__builtin_ia32_fpclasssss,
+	__builtin_ia32_fpclasssd): Removed.
+	(__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
+	* gcc.target/i386/sse-13.c (__builtin_ia32_fpclasssss,
+	__builtin_ia32_fpclasssd): Removed.
+	(__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
+	* gcc.target/i386/sse-23.c (__builtin_ia32_fpclasssss,
+	__builtin_ia32_fpclasssd): Removed.
+	(__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
+	* gcc.target/i386/avx512dq-vfpclassss-2.c: New.
+	* gcc.target/i386/avx512dq-vfpclasssd-2.c: New.
+	* gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test):
+	Add test for _mm_mask_fpclass_ss_mask.
+	* gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test):
+	Add test for _mm_mask_fpclass_sd_mask.
+
 2019-03-22  Vladimir Makarov  <vmakarov@redhat.com>
 
 	PR rtl-optimization/89676
Index: gcc/testsuite/gcc.target/i386/avx-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx-1.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/avx-1.c	(working copy)
@@ -444,8 +444,8 @@
 #define __builtin_ia32_inserti32x8_mask(A, B, F, D, E) __builtin_ia32_inserti32x8_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf64x2_512_mask(A, B, F, D, E) __builtin_ia32_insertf64x2_512_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E)
-#define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1)
-#define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1)
+#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U)
+#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U)
 #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C)
 #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C)
 #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D)
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c	(working copy)
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mavx512dq -O2" } */
 /* { dg-final { scan-assembler-times "vfpclasssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
 
 #include <immintrin.h>
 
@@ -11,4 +12,5 @@
 avx512dq_test (void)
 {
   m8 = _mm_fpclass_sd_mask (x128, 13);
+  m8 = _mm_mask_fpclass_sd_mask (m8, x128, 13);
 }
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c	(nonexistent)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c	(working copy)
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512dq" } */
+/* { dg-require-effective-target avx512dq } */
+
+#define AVX512DQ
+#include "avx512f-helper.h"
+
+#include <math.h>
+#include <limits.h>
+#include <float.h>
+#define SIZE (128 / 64)
+#include "avx512f-mask-type.h"
+
+#ifndef __FPCLASSSD__
+#define __FPCLASSSD__
+int check_fp_class_dp (double src, int imm)
+{
+  int qNaN_res = isnan (src);
+  int sNaN_res = isnan (src);
+  int Pzero_res = (src == 0.0);
+  int Nzero_res = (src == -0.0);
+  int PInf_res = (isinf (src) == 1);
+  int NInf_res = (isinf (src) == -1);
+  int Denorm_res = (fpclassify (src) == FP_SUBNORMAL);
+  int FinNeg_res = __builtin_finite (src) && (src < 0);
+
+  int result = (((imm & 1) && qNaN_res)
+		|| (((imm >> 1) & 1) && Pzero_res)
+		|| (((imm >> 2) & 1) && Nzero_res)
+		|| (((imm >> 3) & 1) && PInf_res)
+		|| (((imm >> 4) & 1) && NInf_res)
+		|| (((imm >> 5) & 1) && Denorm_res)
+		|| (((imm >> 6) & 1) && FinNeg_res)
+		|| (((imm >> 7) & 1) && sNaN_res));
+  return result;
+}
+#endif
+
+__mmask8
+CALC (double *s1, int imm)
+{
+  int i;
+  __mmask8 res = 0;
+
+  if (check_fp_class_dp(s1[0], imm))
+    res = res | 1;
+
+  return res;
+}
+
+void
+TEST (void)
+{
+  int i;
+  union128d src;
+  __mmask8 res1, res2, res_ref = 0;
+  __mmask8 mask = MASK_VALUE;
+
+  src.a[0] = 1.0 / 0.0;
+  for (i = 1; i < SIZE; i++)
+    {
+      src.a[i] = -24.43 + 0.6 * i;
+    }
+
+  res1 = _mm_fpclass_sd_mask (src.x, 0xFF);
+  res2 = _mm_mask_fpclass_sd_mask (mask, src.x, 0xFF);
+
+  res_ref = CALC (src.a, 0xFF);
+
+  if (res_ref != res1)
+    abort ();
+
+  if ((res_ref & mask) != res2)
+    abort ();
+}
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c	(working copy)
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mavx512dq -O2" } */
 /* { dg-final { scan-assembler-times "vfpclassss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclassss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
 
 #include <immintrin.h>
 
@@ -11,4 +12,5 @@
 avx512dq_test (void)
 {
   m8 = _mm_fpclass_ss_mask (x128, 13);
+  m8 = _mm_mask_fpclass_ss_mask (m8, x128, 13);
 }
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c	(nonexistent)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c	(working copy)
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512dq" } */
+/* { dg-require-effective-target avx512dq } */
+
+#define AVX512DQ
+#include "avx512f-helper.h"
+
+#include <math.h>
+#include <limits.h>
+#include <float.h>
+#include "avx512f-mask-type.h"
+#define SIZE (128 / 32)
+
+#ifndef __FPCLASSSS__
+#define __FPCLASSSS__
+int check_fp_class_sp (float src, int imm)
+{
+  int qNaN_res = isnan (src);
+  int sNaN_res = isnan (src);
+  int Pzero_res = (src == 0.0);
+  int Nzero_res = (src == -0.0);
+  int PInf_res = (isinf (src) == 1);
+  int NInf_res = (isinf (src) == -1);
+  int Denorm_res = (fpclassify (src) == FP_SUBNORMAL);
+  int FinNeg_res = __builtin_finite (src) && (src < 0);
+
+  int result = (((imm & 1) && qNaN_res)
+		|| (((imm >> 1) & 1) && Pzero_res)
+		|| (((imm >> 2) & 1) && Nzero_res)
+		|| (((imm >> 3) & 1) && PInf_res)
+		|| (((imm >> 4) & 1) && NInf_res)
+		|| (((imm >> 5) & 1) && Denorm_res)
+		|| (((imm >> 6) & 1) && FinNeg_res)
+		|| (((imm >> 7) & 1) && sNaN_res));
+  return result;
+}
+#endif
+
+__mmask8
+CALC (float *s1, int imm)
+{
+  int i;
+  __mmask8 res = 0;
+
+  if (check_fp_class_sp(s1[0], imm))
+    res = res | 1;
+
+  return res;
+}
+
+void
+TEST (void)
+{
+  int i;
+  union128 src;
+  __mmask8 res1, res2, res_ref = 0;
+  __mmask8 mask = MASK_VALUE;
+
+  src.a[0] = 1.0 / 0.0;
+  for (i = 1; i < SIZE; i++)
+    {
+      src.a[i] = -24.43 + 0.6 * i;
+    }
+
+  res1 = _mm_fpclass_ss_mask (src.x, 0xFF);
+  res2 = _mm_mask_fpclass_ss_mask (mask, src.x, 0xFF);
+
+
+  res_ref = CALC (src.a, 0xFF);
+
+  if (res_ref != res1)
+    abort ();
+
+  if ((mask & res_ref) != res2)
+    abort ();
+}
Index: gcc/testsuite/gcc.target/i386/sse-13.c
===================================================================
--- gcc/testsuite/gcc.target/i386/sse-13.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/sse-13.c	(working copy)
@@ -461,8 +461,8 @@
 #define __builtin_ia32_inserti32x8_mask(A, B, F, D, E) __builtin_ia32_inserti32x8_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf64x2_512_mask(A, B, F, D, E) __builtin_ia32_insertf64x2_512_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E)
-#define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1)
-#define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1)
+#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U)
+#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U)
 #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C)
 #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C)
 #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D)
Index: gcc/testsuite/gcc.target/i386/sse-23.c
===================================================================
--- gcc/testsuite/gcc.target/i386/sse-23.c	(revision 271853)
+++ gcc/testsuite/gcc.target/i386/sse-23.c	(working copy)
@@ -460,8 +460,8 @@
 #define __builtin_ia32_inserti32x8_mask(A, B, F, D, E) __builtin_ia32_inserti32x8_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf64x2_512_mask(A, B, F, D, E) __builtin_ia32_insertf64x2_512_mask(A, B, 1, D, E)
 #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E)
-#define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1)
-#define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1)
+#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U)
+#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U)
 #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C)
 #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C)
 #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D)

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

[Jakub Jelinek]

On Tue, Jun 04, 2019 at 05:00:05PM +0800, Hongtao Liu wrote:
> Thanks for reminding, Here is updated:

You've missed some notes.  Ok for trunk with:
1) the following patch applied on top of your patch
2) the ChangeLog entries moved to the start of the ChangeLog (normally,
   ChangeLog entries are not added as part of the patch, but before the
   patch in text form, because the ChangeLog files are updated many times
   a day

--- mask_fpclasss[sd]_v3.diff	2019-06-04 11:11:31.007712339 +0200
+++ mask_fpclasss[sd]_v3.diff	2019-06-04 11:14:19.581047040 +0200
@@ -2,7 +2,7 @@ Index: gcc/ChangeLog
 ===================================================================
 --- gcc/ChangeLog	(revision 271853)
 +++ gcc/ChangeLog	(working copy)
-@@ -4706,6 +4706,24 @@
+@@ -4706,6 +4706,23 @@
  	reprocessing.  Always call df_analyze before fixing up debug bind
  	insns.
  
@@ -12,17 +12,16 @@ Index: gcc/ChangeLog
 +	* config/i386/avx512dqintrin.h (_mm_mask_fpclass_ss_mask,
 +	_mm_mask_fpclass_sd_mask): New intrinsics.
 +	(_mm_fpclass_ss_mask, _mm_fpclass_sd_mask): Modified, use new builtins.
-+	* config/i386/i386-builtin.def
-+	(__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask):
-+	New builtins.
++	* config/i386/i386-builtin.def (__builtin_ia32_fpclassss_mask,
++	__builtin_ia32_fpclasssd_mask): New builtins.
 +	(__builtin_ia32_fpclassss, __builtin_ia32_fpclasssd): Deleted.
 +	* config/i386/i386-builtin-types.def (DEF_FUNCTION_TYPE (QI, V2DF, INT),
 +	DEF_FUNCTION_TYPE (QI, V4SF, INT)): Deleted.
 +	* config/i386/i386-expand.c (case QI_FTYPE_V4SF_INT,
 +	case QI_FTYPE_V2SF_INT): Ditto.
-+	* config/i386/sse.md
-+	(define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
-+	Extended to insnstructions with mask operands.
++	* config/i386/sse.md (avx512dq_vmfpclass<mode>): Rename to ...
++	(avx512dq_vmfpclass<mode><mask_scalar_merge_name>): ... this.  Add
++	<mask_scalar_merge_operand3> to insn template.
 +
  2019-03-23  Segher Boessenkool  <segher@kernel.crashing.org>
  
@@ -184,10 +183,10 @@ Index: gcc/testsuite/ChangeLog
 +	(__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
 +	* gcc.target/i386/avx512dq-vfpclassss-2.c: New.
 +	* gcc.target/i386/avx512dq-vfpclasssd-2.c: New.
-+	* gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test):
-+	Add test for _mm_mask_fpclass_ss_mask.
-+	* gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test):
-+	Add test for _mm_mask_fpclass_sd_mask.
++	* gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test): Add test for
++	_mm_mask_fpclass_ss_mask.
++	* gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test): Add test for
++	_mm_mask_fpclass_sd_mask.
 +
  2019-03-22  Vladimir Makarov  <vmakarov@redhat.com>
  


	Jakub

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

[Hongtao Liu]

On Tue, Jun 4, 2019 at 5:21 PM Jakub Jelinek <jakub@redhat.com> wrote:
>
> On Tue, Jun 04, 2019 at 05:00:05PM +0800, Hongtao Liu wrote:
> > Thanks for reminding, Here is updated:
>
> You've missed some notes.  Ok for trunk with:
> 1) the following patch applied on top of your patch
> 2) the ChangeLog entries moved to the start of the ChangeLog (normally,
>    ChangeLog entries are not added as part of the patch, but before the
>    patch in text form, because the ChangeLog files are updated many times
>    a day
>

Ok, thanks.

> --- mask_fpclasss[sd]_v3.diff   2019-06-04 11:11:31.007712339 +0200
> +++ mask_fpclasss[sd]_v3.diff   2019-06-04 11:14:19.581047040 +0200
> @@ -2,7 +2,7 @@ Index: gcc/ChangeLog
>  ===================================================================
>  --- gcc/ChangeLog      (revision 271853)
>  +++ gcc/ChangeLog      (working copy)
> -@@ -4706,6 +4706,24 @@
> +@@ -4706,6 +4706,23 @@
>         reprocessing.  Always call df_analyze before fixing up debug bind
>         insns.
>
> @@ -12,17 +12,16 @@ Index: gcc/ChangeLog
>  +      * config/i386/avx512dqintrin.h (_mm_mask_fpclass_ss_mask,
>  +      _mm_mask_fpclass_sd_mask): New intrinsics.
>  +      (_mm_fpclass_ss_mask, _mm_fpclass_sd_mask): Modified, use new builtins.
> -+      * config/i386/i386-builtin.def
> -+      (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask):
> -+      New builtins.
> ++      * config/i386/i386-builtin.def (__builtin_ia32_fpclassss_mask,
> ++      __builtin_ia32_fpclasssd_mask): New builtins.
>  +      (__builtin_ia32_fpclassss, __builtin_ia32_fpclasssd): Deleted.
>  +      * config/i386/i386-builtin-types.def (DEF_FUNCTION_TYPE (QI, V2DF, INT),
>  +      DEF_FUNCTION_TYPE (QI, V4SF, INT)): Deleted.
>  +      * config/i386/i386-expand.c (case QI_FTYPE_V4SF_INT,
>  +      case QI_FTYPE_V2SF_INT): Ditto.
> -+      * config/i386/sse.md
> -+      (define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
> -+      Extended to insnstructions with mask operands.
> ++      * config/i386/sse.md (avx512dq_vmfpclass<mode>): Rename to ...
> ++      (avx512dq_vmfpclass<mode><mask_scalar_merge_name>): ... this.  Add
> ++      <mask_scalar_merge_operand3> to insn template.
>  +
>   2019-03-23  Segher Boessenkool  <segher@kernel.crashing.org>
>
> @@ -184,10 +183,10 @@ Index: gcc/testsuite/ChangeLog
>  +      (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
>  +      * gcc.target/i386/avx512dq-vfpclassss-2.c: New.
>  +      * gcc.target/i386/avx512dq-vfpclasssd-2.c: New.
> -+      * gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test):
> -+      Add test for _mm_mask_fpclass_ss_mask.
> -+      * gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test):
> -+      Add test for _mm_mask_fpclass_sd_mask.
> ++      * gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test): Add test for
> ++      _mm_mask_fpclass_ss_mask.
> ++      * gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test): Add test for
> ++      _mm_mask_fpclass_sd_mask.
>  +
>   2019-03-22  Vladimir Makarov  <vmakarov@redhat.com>
>
>
>
>         Jakub



-- 
BR,
Hongtao

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

[Hongtao Liu]

On Tue, Jun 4, 2019 at 5:56 PM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Tue, Jun 4, 2019 at 5:21 PM Jakub Jelinek <jakub@redhat.com> wrote:
> >
> > On Tue, Jun 04, 2019 at 05:00:05PM +0800, Hongtao Liu wrote:
> > > Thanks for reminding, Here is updated:
> >
> > You've missed some notes.  Ok for trunk with:
> > 1) the following patch applied on top of your patch
> > 2) the ChangeLog entries moved to the start of the ChangeLog (normally,
> >    ChangeLog entries are not added as part of the patch, but before the
> >    patch in text form, because the ChangeLog files are updated many times
> >    a day
> >
>
> Ok, thanks.
>
> > --- mask_fpclasss[sd]_v3.diff   2019-06-04 11:11:31.007712339 +0200
> > +++ mask_fpclasss[sd]_v3.diff   2019-06-04 11:14:19.581047040 +0200
> > @@ -2,7 +2,7 @@ Index: gcc/ChangeLog
> >  ===================================================================
> >  --- gcc/ChangeLog      (revision 271853)
> >  +++ gcc/ChangeLog      (working copy)
> > -@@ -4706,6 +4706,24 @@
> > +@@ -4706,6 +4706,23 @@
> >         reprocessing.  Always call df_analyze before fixing up debug bind
> >         insns.
> >
> > @@ -12,17 +12,16 @@ Index: gcc/ChangeLog
> >  +      * config/i386/avx512dqintrin.h (_mm_mask_fpclass_ss_mask,
> >  +      _mm_mask_fpclass_sd_mask): New intrinsics.
> >  +      (_mm_fpclass_ss_mask, _mm_fpclass_sd_mask): Modified, use new builtins.
> > -+      * config/i386/i386-builtin.def
> > -+      (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask):
> > -+      New builtins.
> > ++      * config/i386/i386-builtin.def (__builtin_ia32_fpclassss_mask,
> > ++      __builtin_ia32_fpclasssd_mask): New builtins.
> >  +      (__builtin_ia32_fpclassss, __builtin_ia32_fpclasssd): Deleted.
> >  +      * config/i386/i386-builtin-types.def (DEF_FUNCTION_TYPE (QI, V2DF, INT),
> >  +      DEF_FUNCTION_TYPE (QI, V4SF, INT)): Deleted.
> >  +      * config/i386/i386-expand.c (case QI_FTYPE_V4SF_INT,
> >  +      case QI_FTYPE_V2SF_INT): Ditto.
> > -+      * config/i386/sse.md
> > -+      (define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
> > -+      Extended to insnstructions with mask operands.
> > ++      * config/i386/sse.md (avx512dq_vmfpclass<mode>): Rename to ...
> > ++      (avx512dq_vmfpclass<mode><mask_scalar_merge_name>): ... this.  Add
> > ++      <mask_scalar_merge_operand3> to insn template.
> >  +
> >   2019-03-23  Segher Boessenkool  <segher@kernel.crashing.org>
> >
> > @@ -184,10 +183,10 @@ Index: gcc/testsuite/ChangeLog
> >  +      (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
> >  +      * gcc.target/i386/avx512dq-vfpclassss-2.c: New.
> >  +      * gcc.target/i386/avx512dq-vfpclasssd-2.c: New.
> > -+      * gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test):
> > -+      Add test for _mm_mask_fpclass_ss_mask.
> > -+      * gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test):
> > -+      Add test for _mm_mask_fpclass_sd_mask.
> > ++      * gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test): Add test for
> > ++      _mm_mask_fpclass_ss_mask.
> > ++      * gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test): Add test for
> > ++      _mm_mask_fpclass_sd_mask.
> >  +
> >   2019-03-22  Vladimir Makarov  <vmakarov@redhat.com>
> >
> >
> >
> >         Jakub
>
>
>
> --
> BR,
> Hongtao

Author: liuhongt
Date: Wed Jun  5 06:04:22 2019
New Revision: 271946

URL: https://gcc.gnu.org/viewcvs?rev=271946&root=gcc&view=rev
Log:
gcc/
2019-06-05  Hongtao Liu  <hongtao.liu@intel.com>

        PR target/89803
        * config/i386/avx512dqintrin.h (_mm_mask_fpclass_ss_mask,
        _mm_mask_fpclass_sd_mask): New intrinsics.
        (_mm_fpclass_ss_mask, _mm_fpclass_sd_mask): Modified, use new builtins.
        * config/i386/i386-builtin.def
        (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask):
        New builtins.
        (__builtin_ia32_fpclassss, __builtin_ia32_fpclasssd): Deleted.
        * config/i386/i386-builtin-types.def (DEF_FUNCTION_TYPE (QI, V2DF,
INT),
        DEF_FUNCTION_TYPE (QI, V4SF, INT)): Deleted.
        * config/i386/i386-expand.c (case QI_FTYPE_V4SF_INT,
        case QI_FTYPE_V2SF_INT): Ditto.
        * config/i386/sse.md
        (define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
        Extended to insnstructions with mask operands.

gcc/testsuite
2019-06-05  Hongtao Liu  <hongtao.liu@intel.com>

        PR target/89803
        * gcc.target/i386/avx-1.c (__builtin_ia32_fpclasssss,
        __builtin_ia32_fpclasssd): Removed.
        (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
        * gcc.target/i386/sse-13.c (__builtin_ia32_fpclasssss,
        __builtin_ia32_fpclasssd): Removed.
        (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
        * gcc.target/i386/sse-23.c (__builtin_ia32_fpclasssss,
        __builtin_ia32_fpclasssd): Removed.
        (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define.
        * gcc.target/i386/avx512dq-vfpclassss-2.c: New.
        * gcc.target/i386/avx512dq-vfpclasssd-2.c: New.
        * gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test):
        Add test for _mm_mask_fpclass_ss_mask.
        * gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test):
        Add test for _mm_mask_fpclass_sd_mask.

-- 
BR,
Hongtao

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

[Jeff Law]

On 6/3/19 5:06 AM, Jakub Jelinek wrote:
> On Mon, Jun 03, 2019 at 06:01:40PM +0800, Hongtao Liu wrote:
>>   The following patch adds forgotten avx512f fpclass instrinsics for
>> masked scalar operations.
>>
>> Bootstrapped/regtested on x86_64-linux and i686-linux (on skylake-avx512),
>> ok for trunk?
>>
>> Changelog:
>>
>> gcc/
>> +2019-03-24 Hongtao Liu <hongtao.liu@intel.com>
>> +
>> + PR target/89803
>> + * config/i386/avx512dqintrin.h
>> + (_mm_mask_fpclass_ss_mask,_mm_mask_fpclass_sd_mask):
>> + New intrinsics.
>> + * config/i386/i386-builtin.def
>> + (__builtin_ia32_fpclassss_mask, _builtin_ia32_fpclasssd_mask):
>> + New builtins.
>> + * config/i386/sse.md
>> + (define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>):
>> + Modified with mask.
> 
> Given that the __builtin_ia32_fpclasss[sd] builtins are AVX512DQ only,
> wouldn't it make more sense to remove the __builtin_ia32_fpclasss[sd]
> builtins rather than keep them, adjust _mm_mask_fpclass_ss/_mm_mask_fpclass_sd
> so that they use these new builtins instead of old and pass in -1 and
> make sure we emit the same code as before for those intrinsics?
> 
> We have way too many ia32 builtins.
Can't argue with the too many ia32 builtins.  If we easily collapse
things the way you suggest, it'd be better.

jeff