From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112a.google.com (mail-yw1-x112a.google.com [IPv6:2607:f8b0:4864:20::112a]) by sourceware.org (Postfix) with ESMTPS id D75B93858D35 for ; Mon, 7 Nov 2022 01:30:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D75B93858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x112a.google.com with SMTP id 00721157ae682-369426664f9so91301477b3.12 for ; Sun, 06 Nov 2022 17:30:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=GGc93ptPUAQxpDOHf8K4T0IFNtbvqh7VJ0ik9jIiJIg=; b=Q54+cpZXFMuSQ2rltYrbpcj1r7hU+lxmbt9iRRF+ed+PiOVVM2COze2tt4NUJ2IFaO G1ygG0PjFGk9NDvhqt+8CiLgsJtU7Ewmyxq199Kqt1jHYPM0JLO1fLja3XzN1Dfunj/k RSYdtPEXqc8Me4oraXVBTaWX9vfY3lqvKtuK+CzPwBSxrooH0Mly9n98Ma57vOM/boA4 XxtqLQu0aCAngsEa30CYVQjoM9ZKi5wURHu+6Fidw5T696LOuPuWYiuapiGkpyzbaPaw 7PArYtqDDn5DgSJnr5P0WUTqYpd7S6fjcuNSJKY9+3h6rwgqk2HNr88FpDYnmMaGHNKW LLvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=GGc93ptPUAQxpDOHf8K4T0IFNtbvqh7VJ0ik9jIiJIg=; b=znqcEaKAg0ZdHhhQ9Icqep/g4ZLKlU/f2FD2SClvbPzwStrTtRxrvxB8th/+OSnI4K p+Gzy3NXvDoJYAV4jFtddLwQFBwhvEBxPxQXtyBbbACbOV2wYmx5VmTPX1g1WldEf9ht s9c+2ENOAKd+dywwpvaJqvvpsH9XmKxeehBKLYg2k7RomcV95udb13S/mIya9lT0UdJV YVirTTzt9CrOuy828xWS0I+pbbxc6utHXDE5U/sKfTADdF6MvXJIwh/xCorKDh31zxDe taRJTudyqEJ6vbXcIklYiOQ4muYtatxRCu5XvOtbvUSk2/jzXH8W0w8AZsWi+gtR2V7r OD/w== X-Gm-Message-State: ACrzQf0fUQ9ID37hUYdGAxnA0sMR1GIi57tOzWKHUuqP3oE275CqVe/a gBpH6MrSOZ4y/3ObQpzyvLgs5Gn7dhw2a2tAV3A= X-Google-Smtp-Source: AMsMyM4nE9TWhlNvMcsrFMNSyBtsbbC3qjJk1dN3sRtjY5yt0+mk9Li5F6nmZWhtu4RzSIfXlz8ODSSJ2/O0ADepCWQ= X-Received: by 2002:a81:5244:0:b0:36a:2bc8:bac8 with SMTP id g65-20020a815244000000b0036a2bc8bac8mr44673240ywb.249.1667784627186; Sun, 06 Nov 2022 17:30:27 -0800 (PST) MIME-Version: 1.0 References: <20221106125651.501400-1-lingling.kong@intel.com> In-Reply-To: From: Hongtao Liu Date: Mon, 7 Nov 2022 09:33:35 +0800 Message-ID: Subject: Re: [PATCH] i386: Prefer remote atomic insn for atomic_fetch{add, and, or, xor} To: "Kong, Lingling" Cc: "Liu, Hongtao" , "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sun, Nov 6, 2022 at 9:00 PM Kong, Lingling via Gcc-patches wrote: > > Hi > > The patch is to add flag -mprefer-remote-atomic to control whether to generate raoint insn for atomic operations. > Ok for trunk? Ok with below 2 little adjustments. > > BRs, > Lingling > > gcc/ChangeLog: > > * config/i386/i386.opt:Add -mprefer-remote-atomic. Please also update *x86 options* in gcc/doc/invode.texi. > * config/i386/sync.md (atomic_): > New define_expand. > (atomic_add): Rename to below one. > (atomic_add_1): To this. > (atomic_): Ditto. > (atomic__1): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/raoint-atomic-fetch.c: New test. > --- > gcc/config/i386/i386.opt | 4 +++ > gcc/config/i386/sync.md | 29 ++++++++++++++++--- > .../gcc.target/i386/raoint-atomic-fetch.c | 29 +++++++++++++++++++ > 3 files changed, 58 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/raoint-atomic-fetch.c > > diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 415c52e1bb4..abb1e5ecbdc 100644 > --- a/gcc/config/i386/i386.opt > +++ b/gcc/config/i386/i386.opt > @@ -1246,3 +1246,7 @@ Support PREFETCHI built-in functions and code generation. > mraoint > Target Mask(ISA2_RAOINT) Var(ix86_isa_flags2) Save Support RAOINT built-in functions and code generation. > + > +mprefer-remote-atomic > +Target Var(flag_prefer_remote_atomic) Init(0) Prefer use remote atomic > +insn for atomic operations. > diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index e6543a5efb0..08e944fc9b7 100644 > --- a/gcc/config/i386/sync.md > +++ b/gcc/config/i386/sync.md > @@ -37,7 +37,7 @@ > UNSPECV_CMPXCHG > UNSPECV_XCHG > UNSPECV_LOCK > - > + Please remove this change. > ;; For CMPccXADD support > UNSPECV_CMPCCXADD > > @@ -791,7 +791,28 @@ > (define_code_iterator any_plus_logic [and ior xor plus]) (define_code_attr plus_logic [(and "and") (ior "or") (xor "xor") (plus "add")]) > > -(define_insn "rao_a" > +(define_expand "atomic_" > + [(match_operand:SWI 0 "memory_operand") > + (any_plus_logic:SWI (match_dup 0) > + (match_operand:SWI 1 "nonmemory_operand")) > + (match_operand:SI 2 "const_int_operand")] > + "" > +{ > + if (flag_prefer_remote_atomic > + && TARGET_RAOINT && operands[2] == const0_rtx > + && (mode == SImode || mode == DImode)) > + { > + if (CONST_INT_P (operands[1])) > + operands[1] = force_reg (mode, operands[1]); > + emit_insn (maybe_gen_rao_a (, mode, operands[0], > +operands[1])); > + } > + else > + emit_insn (gen_atomic__1 (operands[0], operands[1], > + operands[2])); > + DONE; > +}) > + > +(define_insn "@rao_a" > [(set (match_operand:SWI48 0 "memory_operand" "+m") > (unspec_volatile:SWI48 > [(any_plus_logic:SWI48 (match_dup 0) @@ -801,7 +822,7 @@ > "TARGET_RAOINT" > "a\t{%1, %0|%0, %1}") > > -(define_insn "atomic_add" > +(define_insn "atomic_add_1" > [(set (match_operand:SWI 0 "memory_operand" "+m") > (unspec_volatile:SWI > [(plus:SWI (match_dup 0) > @@ -855,7 +876,7 @@ > return "lock{%;} %K2sub{}\t{%1, %0|%0, %1}"; > }) > > -(define_insn "atomic_" > +(define_insn "atomic__1" > [(set (match_operand:SWI 0 "memory_operand" "+m") > (unspec_volatile:SWI > [(any_logic:SWI (match_dup 0) > diff --git a/gcc/testsuite/gcc.target/i386/raoint-atomic-fetch.c b/gcc/testsuite/gcc.target/i386/raoint-atomic-fetch.c > new file mode 100644 > index 00000000000..ac4099d888e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/raoint-atomic-fetch.c > @@ -0,0 +1,29 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mraoint -O2 -mprefer-remote-atomic" } */ > +/* { dg-final { scan-assembler-times "aadd" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "aand" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "aor" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "axor" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "aadd" 1 { target ia32 } } } */ > +/* { dg-final { scan-assembler-times "aand" 1 { target ia32 } } } */ > +/* { dg-final { scan-assembler-times "aor" 1 { target ia32 } } } */ > +/* { dg-final { scan-assembler-times "axor" 1 { target ia32 } } } */ > +volatile int x; volatile long long y; int *a; long long *b; > + > +void extern > +rao_int_test (void) > +{ > + __atomic_add_fetch (a, x, __ATOMIC_RELAXED); > + __atomic_and_fetch (a, x, __ATOMIC_RELAXED); > + __atomic_or_fetch (a, x, __ATOMIC_RELAXED); > + __atomic_xor_fetch (a, x, __ATOMIC_RELAXED); #ifdef __x86_64__ > + __atomic_add_fetch (b, y, __ATOMIC_RELAXED); > + __atomic_and_fetch (b, y, __ATOMIC_RELAXED); > + __atomic_or_fetch (b, y, __ATOMIC_RELAXED); > + __atomic_xor_fetch (b, y, __ATOMIC_RELAXED); #endif } > -- > 2.27.0 > -- BR, Hongtao