From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf29.google.com (mail-qv1-xf29.google.com [IPv6:2607:f8b0:4864:20::f29]) by sourceware.org (Postfix) with ESMTPS id 5DF613858D33 for ; Thu, 23 May 2024 08:05:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5DF613858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5DF613858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::f29 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716451525; cv=none; b=HPF7du3605fW/OQrCuqWDvZ6yQlEA5zQs6Q9VbL+mKaOAcynf/WzSjUmWc55s9BQxdrhdG5UCLlYE2RilgwwbBqXETFaZBc6GThBhnLdBzEOGcz9z8SyjwWzykwtjUBdjXyEAzD1yQ3z7l5H1EaZlKY7NwYyO+Ah9bzEpNKa5PE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716451525; c=relaxed/simple; bh=WwgE+DgdV5IwYb2B5XRHukIhyKzlJzrsCupSS1WQCik=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=PM3FO0Wtf7eHfq7aX50QvCVVbuC2tryV9ADs16xblX1pWTgglsb92XOm5ebzTK2zzASQ7hB0g6URQqHEn5CMpcwbWlKeQfCFSRI4VkkPdDoEqCU+zWaBTFsGXDRXL1FWZM7lqqFkknxAcmGb0O1e9IG7juVJ7aLyN5UqpR5Teug= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-qv1-xf29.google.com with SMTP id 6a1803df08f44-6aacd1d24deso17460096d6.1 for ; Thu, 23 May 2024 01:05:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716451514; x=1717056314; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=y70OE7kxrnMvvk+3cDGOe3o2u75zHBvNRqn8GXNojs8=; b=lDDmFqr3vhVDSMsZAETIVtMxOycZD+IXXwJ05tmnTH+RR5I/vg5JvS/H86FskZecJs EXju6+dbvR5h7ulo0N/LWAwRDukNJwEpm4aHMaId2u1Mnyknm4CoQj7y5REDgDRXXs5u jyjg1wtrDFB1cs5uRvuF12xHULvm0KGhkrKKEmn5usvefQS27fRO1uC6iRBNtwN2irRc s7jM4/Vtw8HFnh8rtMf7R3Wpif2gyDl01pq9dAHKCAHOaCVwFL3ujEhsI+LDKQtWo46K 1NiWFrUimHuJVPFdILBEaRlDghUCP+CPOk4nJLTNjVbAdkGDPd9jk9mRyXIvYmhivG/7 zs0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716451514; x=1717056314; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y70OE7kxrnMvvk+3cDGOe3o2u75zHBvNRqn8GXNojs8=; b=K6+6v/tAiwC7n26DVmyde0Lfj4LIlmCXYk4Ibo+Vxef/DvaJJWfpIEuZ57soukMpjb lfrUuY2Zm4tgYzzBlH+kRrAKz13APBkYR4jztux+bI7BK/9cF+qKokgd9Qw8x7MoV4Zx CG099SH45xYW2kA17dSa0xSW/0soLidQoL/I2RTnwapNt2tJTQ7B7bjrFqk23DkfbOHq zbNQhdr1FLdpyA5SwldOdGlNwy0KtFdt54Gh5jFreXSghztXX5GAmK1lc+16h6EBeNls gKdS2Ba5y14foSW4h1cD8IqexBZ5iqL3jJ+MJVvqIvbJ5Gdo0/876s9s7+/RhliQEDAv Bw3w== X-Gm-Message-State: AOJu0YyrJHYHhXeLijyTZbigYE+Hxr+e4bpmeown3t/UtFIB+snDHQk/ TYzdiGG8Ydq5bsESTRy1awfWh47Z3QpfujlUCORO+CvISL8tTHdHE84pbX9nyM06ujjpZ0cbII3 tnWlDGlXPUPMYR1ENWACn5z9UkWs= X-Google-Smtp-Source: AGHT+IE39Qxwjb9b1I8XKHjgCSzTVchJTZVNMAdQmCXOIFe52LQFCPrhKr7hg1j3Owg6dmDO1ywBEOmq9SBxpZco5cE= X-Received: by 2002:a05:6214:451a:b0:6a3:58a1:1e24 with SMTP id 6a1803df08f44-6ab8f60e230mr36773306d6.25.1716451514420; Thu, 23 May 2024 01:05:14 -0700 (PDT) MIME-Version: 1.0 References: <20240523063742.2333446-1-lin1.hu@intel.com> <20240523063742.2333446-4-lin1.hu@intel.com> In-Reply-To: From: Hongtao Liu Date: Thu, 23 May 2024 16:05:02 +0800 Message-ID: Subject: Re: [PATCH 3/3] vect: support direct conversion under x86-64-v3. To: "Hu, Lin1" Cc: "gcc-patches@gcc.gnu.org" , "Liu, Hongtao" , "ubizjak@gmail.com" , "rguenther@suse.de" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, May 23, 2024 at 3:17=E2=80=AFPM Hu, Lin1 wrote: > > > -----Original Message----- > > From: Hongtao Liu > > Sent: Thursday, May 23, 2024 2:42 PM > > To: Hu, Lin1 > > Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ; > > ubizjak@gmail.com; rguenther@suse.de > > Subject: Re: [PATCH 3/3] vect: support direct conversion under x86-64-v= 3. > > > > On Thu, May 23, 2024 at 2:38=E2=80=AFPM Hu, Lin1 wr= ote: > > > > > > gcc/ChangeLog: > > > > > > PR 107432 > > > * config/i386/i386-expand.cc (ix86_expand_trunc_with_avx2_noa= vx512f): > > > New function for generate a series of suitable insn. > > > * config/i386/i386-protos.h (ix86_expand_trunc_with_avx2_noav= x512f): > > > Define new function. > > > * config/i386/sse.md: Extend trunc2 for x86-64-v3= . > > I have some concern for this patch since > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D115069, let's hold on to= this > > patch. > > OK, maybe we need to modify ix86_expand_vec_perm_const_1, let it emit som= e better code. Maybe like clang (https://godbolt.org/z/rTKPq9oj5). > Or we can disable some of the optimization via vpermq. In pr107432-8.c, t= here are only 5 tests that use vpermq. After a second thought, we may go ahead with the patch, for PR115069, there's an alternative to avoid cross-lane truncation. But for this one, there's no alternative. Although cross-lane permutation is not very efficient, it should still be better than original code. > > BRs, > Lin > > > > gcc/testsuite/ChangeLog: > > > > > > PR 107432 > > > * gcc.target/i386/pr107432-8.c: New test. > > > * gcc.target/i386/pr107432-9.c: Ditto. > > > * gcc.target/i386/pr92645-4.c: Modify test. > > > --- > > > gcc/config/i386/i386-expand.cc | 47 +++++++- > > > gcc/config/i386/i386-protos.h | 3 + > > > gcc/config/i386/sse.md | 87 +++++++++++---- > > > gcc/testsuite/gcc.target/i386/pr107432-8.c | 73 +++++++++++++ > > > gcc/testsuite/gcc.target/i386/pr107432-9.c | 121 ++++++++++++++++++++= + > > > gcc/testsuite/gcc.target/i386/pr92645-4.c | 2 - > > > 6 files changed, 304 insertions(+), 29 deletions(-) create mode > > > 100644 gcc/testsuite/gcc.target/i386/pr107432-8.c > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr107432-9.c > > > > > > diff --git a/gcc/config/i386/i386-expand.cc > > > b/gcc/config/i386/i386-expand.cc index 2f27bfb484c..bca8b85c9d1 10064= 4 > > > --- a/gcc/config/i386/i386-expand.cc > > > +++ b/gcc/config/i386/i386-expand.cc > > > @@ -1896,10 +1896,6 @@ ix86_split_convert_uns_si_sse (rtx operands[]) > > > emit_insn (gen_xorv4si3 (value, value, large)); } > > > > > > -static bool ix86_expand_vector_init_one_nonzero (bool mmx_ok, > > > - machine_mode mode, r= tx target, > > > - rtx var, int one_var= ); > > > - > > > /* Convert an unsigned DImode value into a DFmode, using only SSE. > > > Expects the 64-bit DImode to be supplied in a pair of integral > > > registers. Requires SSE2; will use SSE3 if available. For > > > x86_32, @@ -16418,7 +16414,7 @@ ix86_expand_vector_init_duplicate (bo= ol > > mmx_ok, machine_mode mode, > > > whose ONE_VAR element is VAR, and other elements are zero. Retur= n true > > > if successful. */ > > > > > > -static bool > > > +bool > > > ix86_expand_vector_init_one_nonzero (bool mmx_ok, machine_mode mode, > > > rtx target, rtx var, int one_var= ) > > > { @@ -25551,4 +25547,45 @@ ix86_expand_fast_convert_bf_to_sf (rtx val= ) > > > return ret; > > > } > > > > > > +/* Trunc a vector to a narrow vector, like v4di -> v4si. */ > > > + > > > +bool > > > +ix86_expand_trunc_with_avx2_noavx512f (rtx output, rtx input) { > > > + machine_mode out_mode =3D GET_MODE (output); > > > + machine_mode in_mode =3D GET_MODE (input); > > > + int len =3D GET_MODE_SIZE (in_mode); > > > + gcc_assert (len =3D=3D 16 || len =3D=3D 32); > > > + machine_mode cvt_mode =3D (len =3D=3D 16) ? V16QImode : V32QImode; > > > + int in_innersize =3D GET_MODE_SIZE (GET_MODE_INNER (in_mode)); > > > + int out_innersize =3D GET_MODE_SIZE (GET_MODE_INNER (out_mode)); > > > + > > > + struct expand_vec_perm_d d; > > > + d.target =3D gen_reg_rtx (cvt_mode); > > > + d.op0 =3D lowpart_subreg (cvt_mode, force_reg (in_mode, input), > > > + in_mode); > > > + d.op1 =3D d.op0; > > > + d.vmode =3D cvt_mode; > > > + d.nelt =3D len; > > > + d.testing_p =3D false; > > > + d.one_operand_p =3D true; > > > + > > > + /* Init perm. Put the needed bits of input in order and > > > + fill the rest of bits by default. */ int tot =3D 0; for (int= i > > > + =3D 0; i < len; ++i) > > > + { > > > + d.perm[i] =3D i; > > > + if ((i % in_innersize) < out_innersize) > > > + d.perm[tot++] =3D i; > > > + } > > > + > > > + if (ix86_expand_vec_perm_const_1(&d)) > > > + { > > > + emit_move_insn (output, gen_lowpart (out_mode, d.target)); > > > + return true; > > > + } > > > + > > > + return false; > > > +} > > > + > > > #include "gt-i386-expand.h" > > > diff --git a/gcc/config/i386/i386-protos.h > > > b/gcc/config/i386/i386-protos.h index dbc861fb1ea..ac29fb34028 100644 > > > --- a/gcc/config/i386/i386-protos.h > > > +++ b/gcc/config/i386/i386-protos.h > > > @@ -242,6 +242,7 @@ extern void ix86_expand_atomic_fetch_op_loop (rtx= , > > > rtx, rtx, enum rtx_code, extern void ix86_expand_cmpxchg_loop (rtx *= , rtx, rtx, > > rtx, rtx, rtx, > > > bool, rtx_code_label *); exter= n > > > rtx ix86_expand_fast_convert_bf_to_sf (rtx); > > > +extern bool ix86_expand_trunc_with_avx2_noavx512f (rtx, rtx); > > > extern rtx ix86_memtag_untagged_pointer (rtx, rtx); extern bool > > > ix86_memtag_can_tag_addresses (void); > > > > > > @@ -288,6 +289,8 @@ extern void ix86_expand_sse2_mulvxdi3 (rtx, rtx, > > > rtx); extern void ix86_expand_sse2_abs (rtx, rtx); extern bool > > > ix86_expand_vector_init_duplicate (bool, machine_mode, rtx, > > > rtx); > > > +extern bool ix86_expand_vector_init_one_nonzero (bool, machine_mode, > > rtx, > > > + rtx, int); > > > extern bool ix86_extract_perm_from_pool_constant (int*, rtx); > > > > > > /* In i386-c.cc */ > > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index > > > f57f36ae380..0b14b3dc1ac 100644 > > > --- a/gcc/config/i386/sse.md > > > +++ b/gcc/config/i386/sse.md > > > @@ -14373,14 +14373,25 @@ (define_expand > > "avx512bw_v32hiv32qi2_mask_store" > > > > > > (define_mode_iterator PMOV_DST_MODE_2 > > > [V4SI V8HI (V16QI "TARGET_AVX512BW")]) > > > +(define_mode_iterator PMOV_DST_MODE_2_AVX2 > > > + [V4SI V8HI V16QI]) > > > (define_mode_attr pmov_suff_2 > > > [(V16QI "wb") (V8HI "dw") (V4SI "qd")]) > > > > > > (define_expand "trunc2" > > > - [(set (match_operand:PMOV_DST_MODE_2 0 "nonimmediate_operand") > > > - (truncate:PMOV_DST_MODE_2 > > > + [(set (match_operand:PMOV_DST_MODE_2_AVX2 0 > > "nonimmediate_operand") > > > + (truncate:PMOV_DST_MODE_2_AVX2 > > > (match_operand: 1 "register_operand")))] > > > - "TARGET_AVX512VL") > > > + "TARGET_AVX2" > > > +{ > > > + if (!TARGET_AVX512VL > > > + || (mode =3D=3D V16QImode && !TARGET_AVX512BW)) > > > + { > > > + bool ok =3D ix86_expand_trunc_with_avx2_noavx512f (operands[0]= , > > operands[1]); > > > + gcc_assert (ok); > > > + DONE; > > > + } > > > +}) > > > > > > (define_insn "*avx512vl_2" > > > [(set (match_operand:PMOV_DST_MODE_2 0 "nonimmediate_operand" > > > "=3Dv,m") @@ -14460,6 +14471,7 @@ (define_expand > > "_2_mask_store" > > > "TARGET_AVX512VL") > > > > > > (define_mode_iterator PMOV_SRC_MODE_3 [V4DI V2DI V8SI V4SI (V8HI > > > "TARGET_AVX512BW")]) > > > +(define_mode_iterator PMOV_SRC_MODE_3_AVX2 [V4DI V2DI V8SI V4SI > > > +V8HI]) > > > (define_mode_attr pmov_dst_3_lower > > > [(V4DI "v4qi") (V2DI "v2qi") (V8SI "v8qi") (V4SI "v4qi") (V8HI > > > "v8qi")]) (define_mode_attr pmov_dst_3 @@ -14472,16 +14484,26 @@ > > > (define_mode_attr pmov_suff_3 (define_expand > > > "trunc2" > > > [(set (match_operand: 0 "register_operand") > > > (truncate: > > > - (match_operand:PMOV_SRC_MODE_3 1 "register_operand")))] > > > - "TARGET_AVX512VL" > > > + (match_operand:PMOV_SRC_MODE_3_AVX2 1 "register_operand")))= ] > > > + "TARGET_AVX2" > > > { > > > - rtx op0 =3D gen_reg_rtx (V16QImode); > > > + if (TARGET_AVX512VL > > > + && (mode !=3D V8HImode || TARGET_AVX512BW)) > > > + { > > > + rtx op0 =3D gen_reg_rtx (V16QImode); > > > > > > - emit_insn (gen_avx512vl_truncatevqi2 > > > - (op0, operands[1], CONST0_RTX (mode))= ); > > > + emit_insn (gen_avx512vl_truncatevqi2 > > > + (op0, operands[1], CONST0_RTX > > > + (mode))); > > > + > > > + emit_move_insn (operands[0], > > > + lowpart_subreg (mode, op0, V16QImo= de)); > > > + } > > > + else > > > + { > > > + bool ok =3D ix86_expand_trunc_with_avx2_noavx512f (operands[0]= , > > operands[1]); > > > + gcc_assert (ok); > > > + } > > > > > > - emit_move_insn (operands[0], > > > - lowpart_subreg (mode, op0, V16QImode)); > > > DONE; > > > }) > > > > > > @@ -14853,15 +14875,24 @@ (define_expand > > "trunc2" > > > [(set (match_operand: 0 "register_operand") > > > (truncate: > > > (match_operand:PMOV_SRC_MODE_4 1 "register_operand")))] > > > - "TARGET_AVX512VL" > > > + "TARGET_AVX2" > > > { > > > - rtx op0 =3D gen_reg_rtx (V8HImode); > > > + if (TARGET_AVX512VL) > > > + { > > > + rtx op0 =3D gen_reg_rtx (V8HImode); > > > > > > - emit_insn (gen_avx512vl_truncatevhi2 > > > - (op0, operands[1], CONST0_RTX (mode))= ); > > > + emit_insn (gen_avx512vl_truncatevhi2 > > > + (op0, operands[1], CONST0_RTX > > > + (mode))); > > > > > > - emit_move_insn (operands[0], > > > - lowpart_subreg (mode, op0, V8HImode)); > > > + emit_move_insn (operands[0], > > > + lowpart_subreg (mode, op0, V8HImode= )); > > > + DONE; > > > + } > > > + else > > > + { > > > + bool ok =3D ix86_expand_trunc_with_avx2_noavx512f (operands[0]= , > > operands[1]); > > > + gcc_assert (ok); > > > + } > > > DONE; > > > }) > > > > > > @@ -15102,15 +15133,27 @@ (define_expand "truncv2div2si2" > > > [(set (match_operand:V2SI 0 "register_operand") > > > (truncate:V2SI > > > (match_operand:V2DI 1 "register_operand")))] > > > - "TARGET_AVX512VL" > > > + "TARGET_AVX2" > > > { > > > - rtx op0 =3D gen_reg_rtx (V4SImode); > > > + if (TARGET_AVX512VL) > > > + { > > > + rtx op0 =3D gen_reg_rtx (V4SImode); > > > > > > - emit_insn (gen_avx512vl_truncatev2div2si2 > > > - (op0, operands[1], CONST0_RTX (V2SImode))); > > > + emit_insn (gen_avx512vl_truncatev2div2si2 > > > + (op0, operands[1], CONST0_RTX (V2SImode))); > > > > > > - emit_move_insn (operands[0], > > > - lowpart_subreg (V2SImode, op0, V4SImode)); > > > + emit_move_insn (operands[0], > > > + lowpart_subreg (V2SImode, op0, V4SImode)); > > > + } > > > + else > > > + { > > > + rtx tmp =3D lowpart_subreg (V4SImode, > > > + force_reg (V2DImode, operands[1]), V2= DImode); > > > + rtx op0 =3D gen_reg_rtx (V4SImode); > > > + emit_insn (gen_sse_shufps_v4si (op0, tmp, tmp, const0_rtx, GEN= _INT (2), > > > + GEN_INT (6), GEN_INT (7))); > > > + emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, > > V4SImode)); > > > + } > > > DONE; > > > }) > > > > > > diff --git a/gcc/testsuite/gcc.target/i386/pr107432-8.c > > > b/gcc/testsuite/gcc.target/i386/pr107432-8.c > > > new file mode 100644 > > > index 00000000000..f0d1ab028f7 > > > --- /dev/null > > > +++ b/gcc/testsuite/gcc.target/i386/pr107432-8.c > > > @@ -0,0 +1,73 @@ > > > +/* { dg-do compile } */ > > > +/* { dg-options "-march=3Dx86-64-v3 -O2" } */ > > > +/* { dg-final { scan-assembler-times "vshufps" 1 } } */ > > > +/* { dg-final { scan-assembler-times "vpshufb" 15 } } */ > > > +/* { dg-final { scan-assembler-times "vpermd" 1 } } */ > > > +/* { dg-final { scan-assembler-times "vpermq" 5 } } */ > > > + > > > +#include > > > + > > > +typedef short __v2hi __attribute__ ((__vector_size__ (4))); typedef > > > +char __v2qi __attribute__ ((__vector_size__ (2))); typedef char > > > +__v4qi __attribute__ ((__vector_size__ (4))); typedef char __v8qi > > > +__attribute__ ((__vector_size__ (8))); > > > + > > > +__v2si mm_cvtepi64_epi32_builtin_convertvector(__v2di a) { > > > + return __builtin_convertvector((__v2di)a, __v2si); } > > > + > > > +__v4si mm256_cvtepi64_epi32_builtin_convertvector(__v4di a) { > > > + return __builtin_convertvector((__v4di)a, __v4si); } > > > + > > > +__v2hi mm_cvtepi64_epi16_builtin_convertvector(__m128i a) { > > > + return __builtin_convertvector((__v2di)a, __v2hi); } > > > + > > > +__v4hi mm256_cvtepi64_epi16_builtin_convertvector(__m256i a) { > > > + return __builtin_convertvector((__v4di)a, __v4hi); } > > > + > > > +__v4hi mm_cvtepi32_epi16_builtin_convertvector(__m128i a) { > > > + return __builtin_convertvector((__v4si)a, __v4hi); } > > > + > > > +__v8hi mm256_cvtepi32_epi16_builtin_convertvector(__v8si a) { > > > + return __builtin_convertvector((__v8si)a, __v8hi); } > > > + > > > +__v2qi mm_cvtepi64_epi8_builtin_convertvector(__m128i a) { > > > + return __builtin_convertvector((__v2di)a, __v2qi); } > > > + > > > +__v4qi mm256_cvtepi64_epi8_builtin_convertvector(__m256i a) { > > > + return __builtin_convertvector((__v4di)a, __v4qi); } > > > + > > > +__v4qi mm_cvtepi32_epi8_builtin_convertvector(__m128i a) { > > > + return __builtin_convertvector((__v4si)a, __v4qi); } > > > + > > > +__v8qi mm256_cvtepi32_epi8_builtin_convertvector(__m256i a) { > > > + return __builtin_convertvector((__v8si)a, __v8qi); } > > > + > > > +__v8qi mm_cvtepi16_epi8_builtin_convertvector(__m128i a) { > > > + return __builtin_convertvector((__v8hi)a, __v8qi); } > > > + > > > +__v16qi mm256_cvtepi16_epi8_builtin_convertvector(__v16hi a) > > > +{ > > > + return __builtin_convertvector((__v16hi)a, __v16qi); } > > > diff --git a/gcc/testsuite/gcc.target/i386/pr107432-9.c > > > b/gcc/testsuite/gcc.target/i386/pr107432-9.c > > > new file mode 100644 > > > index 00000000000..650d352b945 > > > --- /dev/null > > > +++ b/gcc/testsuite/gcc.target/i386/pr107432-9.c > > > @@ -0,0 +1,121 @@ > > > +/* { dg-do run } */ > > > +/* { dg-options "-march=3Dx86-64-v3 -O2 -flax-vector-conversions" } = */ > > > +#include > > > + > > > +#include "avx-check.h" > > > + > > > +#ifndef TEST > > > +#define TEST avx_test > > > +#endif > > > + > > > +typedef short __v2hi __attribute__ ((__vector_size__ (4))); typedef > > > +char __v2qi __attribute__ ((__vector_size__ (2))); typedef char > > > +__v4qi __attribute__ ((__vector_size__ (4))); typedef char __v8qi > > > +__attribute__ ((__vector_size__ (8))); > > > + > > > +typedef union > > > +{ > > > + __v2si x; > > > + int a[2]; > > > +} union64i_d; > > > + > > > +typedef union > > > +{ > > > + __v2hi x; > > > + short a[2]; > > > +} union32i_w; > > > + > > > +typedef union > > > +{ > > > + __v4hi x; > > > + short a[4]; > > > +} union64i_w; > > > + > > > +typedef union > > > +{ > > > + __v2qi x; > > > + char a[2]; > > > +} union16i_b; > > > + > > > +typedef union > > > +{ > > > + __v4qi x; > > > + char a[4]; > > > +} union32i_b; > > > + > > > +typedef union > > > +{ > > > + __v8qi x; > > > + char a[8]; > > > +} union64i_b; > > > + > > > +#define CHECK_EXP_LESS128(UNION_TYPE, VALUE_TYPE, FMT) \ > > > +static int \ > > > +__attribute__((noinline, unused)) \ > > > +check_##UNION_TYPE (UNION_TYPE u, const VALUE_TYPE * v) \ > > > +{ \ > > > + int i; \ > > > + int err =3D 0; \ > > > + \ > > > + for (i =3D 0; i < ARRAY_SIZE (u.a); i++) \ > > > + if (u.a[i] !=3D v[i]) \ > > > + { \ > > > + err++; \ > > > + PRINTF ("%i: " FMT " !=3D " FMT "\n", \ > > > + i, v[i], u.a[i]); \ > > > + } \ > > > + return err; \ > > > +} > > > + > > > +CHECK_EXP_LESS128 (union64i_d, int, "%d"); > > > +CHECK_EXP_LESS128 (union32i_w, short, "%d"); > > > +CHECK_EXP_LESS128 (union64i_w, short, "%d"); > > > +CHECK_EXP_LESS128 (union16i_b, char, "%d"); > > > +CHECK_EXP_LESS128 (union32i_b, char, "%d"); > > > +CHECK_EXP_LESS128 (union64i_b, char, "%d"); > > > + > > > +#define SUBTEST(INPUT_TYPE, OUTPUT_TYPE, OUTPUT_INNER, INIT_TYPE, > > CVT_TYPE) \ > > > +void do_test##INIT_TYPE##CVT_TYPE () \ > > > +{ \ > > > + INPUT_TYPE s; \ > > > + OUTPUT_TYPE r, ref; \ > > > + for (int i =3D 0; i < ARRAY_SIZE (s.a); i++) \ > > > + { \ > > > + s.a[i] =3D (i + 23415) * (i + 341); \ > > > + ref.a[i] =3D (OUTPUT_INNER) s.a[i]; \ > > > + } \ > > > + r.x =3D __builtin_convertvector((INIT_TYPE)s.x, CVT_TYPE); \ > > > + \ > > > + if (check_##OUTPUT_TYPE (r, ref.a)) \ > > > + abort (); \ > > > + return; \ > > > +} > > > + > > > +SUBTEST(union128i_q, union64i_d, int, __v2di, __v2si); > > > +SUBTEST(union256i_q, union128i_d, int, __v4di, __v4si); > > > +SUBTEST(union128i_q, union32i_w, short, __v2di, __v2hi); > > > +SUBTEST(union256i_q, union64i_w, short, __v4di, __v4hi); > > > +SUBTEST(union128i_d, union64i_w, short, __v4si, __v4hi); > > > +SUBTEST(union256i_d, union128i_w, short, __v8si, __v8hi); > > > +SUBTEST(union128i_q, union16i_b, char, __v2di, __v2qi); > > > +SUBTEST(union256i_q, union32i_b, char, __v4di,__v4qi); > > > +SUBTEST(union128i_d, union32i_b, char, __v4si, __v4qi); > > > +SUBTEST(union256i_d, union64i_b, char, __v8si, __v8qi); > > > +SUBTEST(union128i_w, union64i_b, char, __v8hi, __v8qi); > > > +SUBTEST(union256i_w, union128i_b, char, __v16hi, __v16qi); > > > + > > > +void TEST (void) > > > +{ > > > + do_test__v2di__v2si (); > > > + do_test__v2di__v2hi (); > > > + do_test__v2di__v2qi (); > > > + do_test__v4di__v4si (); > > > + do_test__v4di__v4hi (); > > > + do_test__v4di__v4qi (); > > > + do_test__v4si__v4hi (); > > > + do_test__v4si__v4qi (); > > > + do_test__v8si__v8hi (); > > > + do_test__v8si__v8qi (); > > > + do_test__v8hi__v8qi (); > > > + do_test__v16hi__v16qi (); > > > +} > > > diff --git a/gcc/testsuite/gcc.target/i386/pr92645-4.c > > > b/gcc/testsuite/gcc.target/i386/pr92645-4.c > > > index 28a3f9a3527..3aa49a3b654 100644 > > > --- a/gcc/testsuite/gcc.target/i386/pr92645-4.c > > > +++ b/gcc/testsuite/gcc.target/i386/pr92645-4.c > > > @@ -52,5 +52,3 @@ void f(char *dst, char *src, unsigned long n, unsig= ned c) > > > a uniform CTOR with a vector promotion to a CTOR on a promoted > > > element. */ > > > /* { dg-final { scan-tree-dump-times "\\(vector\\(16\\) short > > > unsigned int\\)" 2 "optimized" { xfail *-*-* } } } */ > > > -/* { dg-final { scan-tree-dump-times "VEC_PACK_TRUNC" 1 "optimized" = } > > > } */ > > > -/* { dg-final { scan-tree-dump-times "BIT_FIELD_REF" 2 "optimized" } > > > } */ > > > -- > > > 2.31.1 > > > > > > > > > -- > > BR, > > Hongtao --=20 BR, Hongtao