From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb33.google.com (mail-yb1-xb33.google.com [IPv6:2607:f8b0:4864:20::b33]) by sourceware.org (Postfix) with ESMTPS id 358E83858D20 for ; Wed, 9 Aug 2023 08:24:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 358E83858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yb1-xb33.google.com with SMTP id 3f1490d57ef6-d414540af6bso5126338276.2 for ; Wed, 09 Aug 2023 01:24:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1691569494; x=1692174294; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=AMlh2j+6V8OXWVYQ+qRHG39Awp7AdC9YVCJ5H1O/dss=; b=KEvGgaDYSnEhAWFqwQmjhnHSnI+9+5g9AcHyM8TJr91lmxmlY3Rz6kGM7bCoJxRLq6 x5eIlCr9aFLFoib06ExXTM3mxgOMNJwAEcq8RWl+P50iDltHol5FvlD45VRBfJ6AxIXT 457kEHeEMufnKn7yGYnHFbUisteBmI7IUyiTfRpv8h+oPAVNRJ9u48GqbgqdM3d3nYFm LpigHb3yZRiFFI87gYXaA6Gy3poaWTLP7EoCIyyXzZYvWWSX+zBAPLTuATlF0dh8akva c8OSU08ph4RndInLi0verNiminX2QiQf05VdVr8LlWZKoiknRsEV5I1fG1VujJOlF+S8 VMhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691569494; x=1692174294; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AMlh2j+6V8OXWVYQ+qRHG39Awp7AdC9YVCJ5H1O/dss=; b=NpSvpOsGlzurNLje1fVkeSaVhSRnYvOoLPANlWw8mvjE0tHQ6OfpxZ7WYvQkkxKWW4 /WB3llBGiCdOptazzP+SDTkesEeSt1esSvCvEhTj/JOhEk1iP4SHauiuapgnUrMxdOjN oxvX/spMHVwv58RNakhVglNGLMFzWMK4kzORYkTbWTIGcHnRYBweeZ4aqj2at+bYgDeN ct5sd9Ps7b7s047tqI3JGJyyXqJ2DAiSGjWaPbxuT3msM//L1GgIhIVPrmcgv0Wvc4Mg D2ZsDsPk8rVjhrmkFcrcKuVz04tpGEhTvrjHFnLnac7yB+F82iigj0l1O8+BCcUCHYhu mZmA== X-Gm-Message-State: AOJu0YwRaoqQCcqZx97BeSFSjp6XoRqb1q2xxD1u1zrYx0Gj4RbA2HU2 M2bDq+NfArmS0GhLTL4E5EyMYzp4qeRnko9VKmU= X-Google-Smtp-Source: AGHT+IFaliuyIu0lVpxY/RjJS2inQ1ivR5XVMBPbmxMiiG+OW/TGkF4cZV0D0RXUxqNlp04jB689dc6bXdgRowiExDE= X-Received: by 2002:a25:d156:0:b0:d4d:b9ec:ca8c with SMTP id i83-20020a25d156000000b00d4db9ecca8cmr2075572ybg.8.1691569494480; Wed, 09 Aug 2023 01:24:54 -0700 (PDT) MIME-Version: 1.0 References: <728A7331-C23F-463E-932E-FCE48CCFEB46@gmail.com> <87pm3w1vkp.fsf@oldenburg.str.redhat.com> In-Reply-To: <87pm3w1vkp.fsf@oldenburg.str.redhat.com> From: Hongtao Liu Date: Wed, 9 Aug 2023 16:24:43 +0800 Message-ID: Subject: Re: Intel AVX10.1 Compiler Design and Support To: Florian Weimer Cc: Richard Biener via Gcc-patches , Phoebe Wang , Richard Biener , Joseph Myers , Haochen Jiang , ubizjak@gmail.com, hongtao.liu@intel.com, "Zhang, Annita" , phoebe.wang@intel.com, x86-64-abi , llvm-dev , Craig Topper Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Aug 9, 2023 at 4:14=E2=80=AFPM Florian Weimer = wrote: > > * Richard Biener via Gcc-patches: > > > I don=E2=80=99t think we can realistically change the ABI. If we could > > passing them in two 256bit registers would be possible as well. > > > > Note I fully expect intel to turn around and implement 512 bits on a > > 256 but data path on the E cores in 5 years. And it will take at > > least that time for AVX10 to take off (look at AVX512 for this and how > > they cautionously chose to include bf16 to cut off Zen4). So IMHO we > > shouldn=E2=80=99t worry at all and just wait and see for AVX42 to arriv= e. > > Yes, the direction is a bit unclear. In retrospect, we could have > defined x86-64-v4 to use 256 bit vector width, so it could eventually be > compatible with AVX10; it's also what current Intel CPUs prefer (and NOTE, avx10.x-256 also inhibit the usage of 64-bit kmask which is supposed to be only used by zmm instructions. But in theory, those 64-bit kmask intrinsics can be used standalone .i.e. kshift/kand/kor. > past, with the exception of the Xeon Phi line). But in the meantime, > AMD has started to ship CPUs that seem to prefer 512 bit vectors, > despite having a double pumped implementation. (Disclaimer: All CPU > preferences inferred from current compiler tuning defaults, not actual > experiments. 8-/) > > To me, this looks like we may have defined x86-64-v4 prematurely, and > this suggests we should wait a bit to see where things are heading. > > Thanks, > Florian > --=20 BR, Hongtao