From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112f.google.com (mail-yw1-x112f.google.com [IPv6:2607:f8b0:4864:20::112f]) by sourceware.org (Postfix) with ESMTPS id 6A51A3858D1E for ; Fri, 11 Nov 2022 01:49:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6A51A3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x112f.google.com with SMTP id 00721157ae682-369426664f9so32336397b3.12 for ; Thu, 10 Nov 2022 17:49:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=HtJBZpmi9Woaf5VGo8BFZG8nJBJFLofqWu1WKCh0mFA=; b=MVSFcFaUyVfReGgb9pFPZOpWEMbRGzaLD8fcphvqy6zKgqdhtI5TVPZzD95LFGkJJG GKQDZONPdlQgEDkmgbnUX/M/1ft7q5ElEuSrncivny2/jBVOJZbe1KEgzMSsUFegj5HU wkIPEQ2GfSalu7jJxlzTY1VziKBGxcyzn1VgWS1v0o/BaBlcMKukvIMKhDm069VJMsWI 3PKijcriAa/AwFRgUei0VMCQjjGe2SI/iqRj54p0fxfHQLD+vSoNBwX3461MnvJb5cLB arvQygY6RiL7YMk2hWUd74686gklsGNSlpDF48yFpXohGthZLjUdw+7U6vvYd06LNAF9 fp1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=HtJBZpmi9Woaf5VGo8BFZG8nJBJFLofqWu1WKCh0mFA=; b=W7mNF0FD0BPZ288Mz49/j/XjS3dAQIQck8JCYWKP1BVN7UM4mS1hbVL5293fHQdUvi O37+9XdJF7oY2aq9h8FlrqjmxMppQve1JfZE4y4b+v1opHEk7dplFXVQlh0mw45KpUdQ LzLMkNmdLGqplcu6t0F24jRKPLw3VSoqfql8WcVtMl9EArjlxk5pyzS5TsFNE3b4vO3d ruCHFvYLCIOh9QwS8xlcOyU9stIWBahyij3acy7qs3+zTsd5XAvUbdgwStlSma22QB2L HbP6hPcupkNRmym/W7hZQA7i1Ou149vVx9OvEQzqluRYbOpYc9olN5aIDRQsuX8rrfRM Dn0A== X-Gm-Message-State: ACrzQf1wAfC6LBwGPn/DoBWlvnD0En4ChiN0CScumpk3PN9uLwr7La65 G7RdlNmrBDA2M8+yMiRMVb+8RmtcSnlO8llXefg= X-Google-Smtp-Source: AMsMyM7uudEeXo3WPnf8fHzhOJMNxAt0qLNO9p2SrHyl7RYkWiq26jZPI4DIIydGP+wnu703VxpPC9YqtFfpgCT33Uc= X-Received: by 2002:a81:4fc9:0:b0:36b:1a78:723b with SMTP id d192-20020a814fc9000000b0036b1a78723bmr64239328ywb.241.1668131387805; Thu, 10 Nov 2022 17:49:47 -0800 (PST) MIME-Version: 1.0 References: <20221109071302.78435-1-haochen.jiang@intel.com> In-Reply-To: <20221109071302.78435-1-haochen.jiang@intel.com> From: Hongtao Liu Date: Fri, 11 Nov 2022 09:52:56 +0800 Message-ID: Subject: Re: [PATCH] i386: Add ISA check for newly introduced prefetch builtins. To: Haochen Jiang Cc: gcc-patches@gcc.gnu.org, ubizjak@gmail.com, jakub@redhat.com, hongtao.liu@intel.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Nov 9, 2022 at 3:15 PM Haochen Jiang via Gcc-patches wrote: > > Hi all, > > As Hongtao said, the fail on pentiumpro is caused by missing ISA check > since we are using emit_insn () through new builtins and it won't check > if the TARGET matches. Previously, the builtin in middle-end will check > that. > > On pentiumpro, we won't have anything that supports any prefetch so that > it dropped into the pattern and then failed. > > I have added the restrictions just like what middle-end builtin_prefetch > does. Also I added missing checks for PREFETCHI. Ok for trunk? Ok. > > BRs, > Haochen > > gcc/ChangeLog: > > * config/i386/i386-builtin.def (BDESC): Add > OPTION_MASK_ISA2_PREFETCHI for prefetchi builtin. > * config/i386/i386-expand.cc (ix86_expand_builtin): > Add ISA check before emit_insn. > * config/i386/prfchiintrin.h: Add target for intrin. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/prefetchi-5.c: New test. > --- > gcc/config/i386/i386-builtin.def | 2 +- > gcc/config/i386/i386-expand.cc | 11 +++++++++-- > gcc/config/i386/prfchiintrin.h | 14 +++++++++++++- > gcc/testsuite/gcc.target/i386/prefetchi-5.c | 4 ++++ > 4 files changed, 27 insertions(+), 4 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/prefetchi-5.c > > diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def > index ea3aff7f125..5e0461acc00 100644 > --- a/gcc/config/i386/i386-builtin.def > +++ b/gcc/config/i386/i386-builtin.def > @@ -498,7 +498,7 @@ BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_nothing, "__builtin_ia32_aesencwide1 > BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_nothing, "__builtin_ia32_aesencwide256kl_u8", IX86_BUILTIN_AESENCWIDE256KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_PCV2DI_PCVOID) > > /* PREFETCHI */ > -BDESC (0, 0, CODE_FOR_prefetchi, "__builtin_ia32_prefetchi", IX86_BUILTIN_PREFETCHI, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT) > +BDESC (0, OPTION_MASK_ISA2_PREFETCHI, CODE_FOR_prefetchi, "__builtin_ia32_prefetchi", IX86_BUILTIN_PREFETCHI, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT) > BDESC (0, 0, CODE_FOR_nothing, "__builtin_ia32_prefetch", IX86_BUILTIN_PREFETCH, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT_INT_INT) > > BDESC_END (SPECIAL_ARGS, PURE_ARGS) > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc > index 9c92b07d5cd..0e45c195390 100644 > --- a/gcc/config/i386/i386-expand.cc > +++ b/gcc/config/i386/i386-expand.cc > @@ -13131,7 +13131,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, > > if (INTVAL (op3) == 1) > { > - if (TARGET_64BIT > + if (TARGET_64BIT && TARGET_PREFETCHI > && local_func_symbolic_operand (op0, GET_MODE (op0))) > emit_insn (gen_prefetchi (op0, op2)); > else > @@ -13150,7 +13150,14 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, > op0 = convert_memory_address (Pmode, op0); > op0 = copy_addr_to_reg (op0); > } > - emit_insn (gen_prefetch (op0, op1, op2)); > + > + if (TARGET_3DNOW || TARGET_PREFETCH_SSE > + || TARGET_PRFCHW || TARGET_PREFETCHWT1) > + emit_insn (gen_prefetch (op0, op1, op2)); > + else if (!MEM_P (op0) && side_effects_p (op0)) > + /* Don't do anything with direct references to volatile memory, > + but generate code to handle other side effects. */ > + emit_insn (op0); > } > > return 0; > diff --git a/gcc/config/i386/prfchiintrin.h b/gcc/config/i386/prfchiintrin.h > index 06deef488ba..996a4be1aba 100644 > --- a/gcc/config/i386/prfchiintrin.h > +++ b/gcc/config/i386/prfchiintrin.h > @@ -30,6 +30,13 @@ > > #ifdef __x86_64__ > > + > +#ifndef __PREFETCHI__ > +#pragma GCC push_options > +#pragma GCC target("prefetchi") > +#define __DISABLE_PREFETCHI__ > +#endif /* __PREFETCHI__ */ > + > extern __inline void > __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > _m_prefetchit0 (void* __P) > @@ -44,6 +51,11 @@ _m_prefetchit1 (void* __P) > __builtin_ia32_prefetchi (__P, 2); > } > > -#endif > +#ifdef __DISABLE_PREFETCHI__ > +#undef __DISABLE_PREFETCHI__ > +#pragma GCC pop_options > +#endif /* __DISABLE_PREFETCHI__ */ > + > +#endif /* __x86_64__ */ > > #endif /* _PRFCHIINTRIN_H_INCLUDED */ > diff --git a/gcc/testsuite/gcc.target/i386/prefetchi-5.c b/gcc/testsuite/gcc.target/i386/prefetchi-5.c > new file mode 100644 > index 00000000000..8c26540f96a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/prefetchi-5.c > @@ -0,0 +1,4 @@ > +/* { dg-do compile { target { ia32 } } } */ > +/* { dg-options "-O0 -march=pentiumpro" } */ > + > +#include "prefetchi-4.c" > -- > 2.18.1 > -- BR, Hongtao