From: Hongtao Liu <crazylht@gmail.com>
To: liuhongt <hongtao.liu@intel.com>
Cc: gcc-patches@gcc.gnu.org, hjl.tools@gmail.com
Subject: Re: [PATCH] Fix target_clone ("arch=graniterapids-d") and target_clone ("arch=arrowlake-s")
Date: Thu, 24 Aug 2023 11:39:11 +0800 [thread overview]
Message-ID: <CAMZc-byLKC3ZeLfWQpU06+eX5ON3CPAJuHdHstz7AtR-L6zr2w@mail.gmail.com> (raw)
In-Reply-To: <20230823043118.4118801-1-hongtao.liu@intel.com>
On Wed, Aug 23, 2023 at 12:31 PM liuhongt <hongtao.liu@intel.com> wrote:
>
> Both "graniterapid-d" and "graniterapids" are attached with
> PROCESSOR_GRANITERAPID in processor_alias_table but mapped to
> different __cpu_subtype in get_intel_cpu.
>
> And get_builtin_code_for_version will try to match the first
> PROCESSOR_GRANITERAPIDS in processor_alias_table which maps to
> "granitepraids" here.
>
> 861 else if (new_target->arch_specified && new_target->arch > 0)
> 1862 for (i = 0; i < pta_size; i++)
> 1863 if (processor_alias_table[i].processor == new_target->arch)
> 1864 {
> 1865 const pta *arch_info = &processor_alias_table[i];
> 1866 switch (arch_info->priority)
> 1867 {
> 1868 default:
> 1869 arg_str = arch_info->name;
>
> This mismatch makes dispatch_function_versions check the preidcate
> of__builtin_cpu_is ("graniterapids") for "graniterapids-d" and causes
> the issue.
> The patch explicitly adds PROCESSOR_ARROWLAKE_S and
> PROCESSOR_GRANITERAPIDS_D to make a distinction.
>
> For "alderlake","raptorlake", "meteorlake" they share same isa, cost,
> tuning, and mapped to the same __cpu_type/__cpu_subtype in
> get_intel_cpu, so no need to add PROCESSOR_RAPTORLAKE and others.
>
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu.
> Ok for trunk(and backport graniterapids-d part to GCC13)?
Push to trunk and backport to GCC13 release branch.
>
> gcc/ChangeLog:
>
> * common/config/i386/i386-common.cc (processor_names): Add new
> member graniterapids-s and arrowlake-s.
> * config/i386/i386-options.cc (processor_alias_table): Update
> table with PROCESSOR_ARROWLAKE_S and
> PROCESSOR_GRANITERAPIDS_D.
> (m_GRANITERAPID_D): New macro.
> (m_ARROWLAKE_S): Ditto.
> (m_CORE_AVX512): Add m_GRANITERAPIDS_D.
> (processor_cost_table): Add icelake_cost for
> PROCESSOR_GRANITERAPIDS_D and alderlake_cost for
> PROCESSOR_ARROWLAKE_S.
> * config/i386/x86-tune.def: Hanlde m_ARROWLAKE_S same as
> m_ARROWLAKE.
> * config/i386/i386.h (enum processor_type): Add new member
> PROCESSOR_GRANITERAPIDS_D and PROCESSOR_ARROWLAKE_S.
> * config/i386/i386-c.cc (ix86_target_macros_internal): Handle
> PROCESSOR_GRANITERAPIDS_D and PROCESSOR_ARROWLAKE_S
> ---
> gcc/common/config/i386/i386-common.cc | 11 +++--
> gcc/config/i386/i386-c.cc | 15 +++++++
> gcc/config/i386/i386-options.cc | 6 ++-
> gcc/config/i386/i386.h | 4 +-
> gcc/config/i386/x86-tune.def | 63 ++++++++++++++-------------
> 5 files changed, 62 insertions(+), 37 deletions(-)
>
> diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
> index 12a01704a73..1e11163004b 100644
> --- a/gcc/common/config/i386/i386-common.cc
> +++ b/gcc/common/config/i386/i386-common.cc
> @@ -2155,7 +2155,9 @@ const char *const processor_names[] =
> "alderlake",
> "rocketlake",
> "graniterapids",
> + "graniterapids-d",
> "arrowlake",
> + "arrowlake-s",
> "intel",
> "lujiazui",
> "geode",
> @@ -2279,13 +2281,14 @@ const pta processor_alias_table[] =
> M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
> {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS,
> M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX512F},
> - {"graniterapids-d", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS_D,
> - M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D), P_PROC_AVX512F},
> + {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D, CPU_HASWELL,
> + PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D),
> + P_PROC_AVX512F},
> {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE,
> M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2},
> - {"arrowlake-s", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE_S,
> + {"arrowlake-s", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
> M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
> - {"lunarlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE_S,
> + {"lunarlake", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
> M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
> {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
> M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
> diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
> index caef5531593..0e11709ebc5 100644
> --- a/gcc/config/i386/i386-c.cc
> +++ b/gcc/config/i386/i386-c.cc
> @@ -258,6 +258,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
> def_or_undef (parse_in, "__graniterapids");
> def_or_undef (parse_in, "__graniterapids__");
> break;
> + case PROCESSOR_GRANITERAPIDS_D:
> + def_or_undef (parse_in, "__graniterapids_d");
> + def_or_undef (parse_in, "__graniterapids_d__");
> + break;
> case PROCESSOR_ALDERLAKE:
> def_or_undef (parse_in, "__alderlake");
> def_or_undef (parse_in, "__alderlake__");
> @@ -270,6 +274,11 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
> def_or_undef (parse_in, "__arrowlake");
> def_or_undef (parse_in, "__arrowlake__");
> break;
> + case PROCESSOR_ARROWLAKE_S:
> + def_or_undef (parse_in, "__arrowlake_s");
> + def_or_undef (parse_in, "__arrowlake_s__");
> + break;
> +
> /* use PROCESSOR_max to not set/unset the arch macro. */
> case PROCESSOR_max:
> break;
> @@ -451,9 +460,15 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
> case PROCESSOR_GRANITERAPIDS:
> def_or_undef (parse_in, "__tune_graniterapids__");
> break;
> + case PROCESSOR_GRANITERAPIDS_D:
> + def_or_undef (parse_in, "__tune_graniterapids_d__");
> + break;
> case PROCESSOR_ARROWLAKE:
> def_or_undef (parse_in, "__tune_arrowlake__");
> break;
> + case PROCESSOR_ARROWLAKE_S:
> + def_or_undef (parse_in, "__tune_arrowlake_s__");
> + break;
> case PROCESSOR_INTEL:
> case PROCESSOR_GENERIC:
> break;
> diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
> index f48112d4aa6..9af4f910143 100644
> --- a/gcc/config/i386/i386-options.cc
> +++ b/gcc/config/i386/i386-options.cc
> @@ -127,10 +127,11 @@ along with GCC; see the file COPYING3. If not see
> #define m_ALDERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_ALDERLAKE)
> #define m_ROCKETLAKE (HOST_WIDE_INT_1U<<PROCESSOR_ROCKETLAKE)
> #define m_GRANITERAPIDS (HOST_WIDE_INT_1U<<PROCESSOR_GRANITERAPIDS)
> +#define m_GRANITERAPIDS_D (HOST_WIDE_INT_1U<<PROCESSOR_GRANITERAPIDS_D)
> #define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \
> | m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE \
> | m_TIGERLAKE | m_COOPERLAKE | m_SAPPHIRERAPIDS \
> - | m_ROCKETLAKE | m_GRANITERAPIDS)
> + | m_ROCKETLAKE | m_GRANITERAPIDS | m_GRANITERAPIDS_D)
> #define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512)
> #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2)
> #define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
> @@ -139,6 +140,7 @@ along with GCC; see the file COPYING3. If not see
> #define m_SIERRAFOREST (HOST_WIDE_INT_1U<<PROCESSOR_SIERRAFOREST)
> #define m_GRANDRIDGE (HOST_WIDE_INT_1U<<PROCESSOR_GRANDRIDGE)
> #define m_ARROWLAKE (HOST_WIDE_INT_1U<<PROCESSOR_ARROWLAKE)
> +#define m_ARROWLAKE_S (HOST_WIDE_INT_1U<<PROCESSOR_ARROWLAKE_S)
> #define m_CORE_ATOM (m_SIERRAFOREST | m_GRANDRIDGE)
> #define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL)
> /* Gather Data Sampling / CVE-2022-40982 / INTEL-SA-00828.
> @@ -778,6 +780,8 @@ static const struct processor_costs *processor_cost_table[] =
> &alderlake_cost,
> &icelake_cost,
> &icelake_cost,
> + &icelake_cost,
> + &alderlake_cost,
> &alderlake_cost,
> &intel_cost,
> &lujiazui_cost,
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index f5fb6fe9be9..470963868bd 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -2203,7 +2203,7 @@ extern int const svr4_debugger_register_map[FIRST_PSEUDO_REGISTER];
> #define DEFAULT_LARGE_SECTION_THRESHOLD 65536
>
> /* Which processor to tune code generation for. These must be in sync
> - with processor_target_table in i386.cc. */
> + with processor_cost_table in i386-options.cc. */
>
> enum processor_type
> {
> @@ -2240,7 +2240,9 @@ enum processor_type
> PROCESSOR_ALDERLAKE,
> PROCESSOR_ROCKETLAKE,
> PROCESSOR_GRANITERAPIDS,
> + PROCESSOR_GRANITERAPIDS_D,
> PROCESSOR_ARROWLAKE,
> + PROCESSOR_ARROWLAKE_S,
> PROCESSOR_INTEL,
> PROCESSOR_LUJIAZUI,
> PROCESSOR_GEODE,
> diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
> index 735d6635eba..4b2c5d59a95 100644
> --- a/gcc/config/i386/x86-tune.def
> +++ b/gcc/config/i386/x86-tune.def
> @@ -43,7 +43,7 @@ DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
> m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
> | m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
> | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
> - | m_CORE_ATOM | m_GENERIC)
> + | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
> on modern chips. Prefer stores affecting whole integer register
> @@ -53,7 +53,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
> m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2
> | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
> | m_KNL | m_KNM | m_AMD_MULTIPLE | m_LUJIAZUI | m_TREMONT
> - | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)
> + | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
> destinations to be 128bit to allow register renaming on 128bit SSE units,
> @@ -64,7 +64,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
> DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
> m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
> | m_BDVER | m_ZNVER | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE
> - | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)
> + | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids
> partial write to the destination in scalar SSE conversion from FP
> @@ -73,7 +73,7 @@ DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY,
> "sse_partial_reg_fp_converts_dependency",
> m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
> | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_ARROWLAKE
> - | m_CORE_ATOM | m_GENERIC)
> + | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial
> write to the destination in scalar SSE conversion from integer to FP. */
> @@ -81,14 +81,14 @@ DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY,
> "sse_partial_reg_converts_dependency",
> m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
> | m_BDVER | m_ZNVER | m_LUJIAZUI | m_ALDERLAKE | m_ARROWLAKE
> - | m_CORE_ATOM | m_GENERIC)
> + | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before
> several insns to break false dependency on the dest register for GLC
> micro-architecture. */
> DEF_TUNE (X86_TUNE_DEST_FALSE_DEP_FOR_GLC,
> "dest_false_dep_for_glc", m_SAPPHIRERAPIDS | m_ALDERLAKE | m_ARROWLAKE
> - | m_CORE_ATOM)
> + | m_ARROWLAKE_S | m_CORE_ATOM)
>
> /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
> are resolved on SSE register parts instead of whole registers, so we may
> @@ -115,14 +115,14 @@ DEF_TUNE (X86_TUNE_MOVX, "movx",
> | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL
> | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
> | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
> - | m_CORE_ATOM | m_GENERIC)
> + | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
> full sized loads. */
> DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
> m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
> | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE
> - | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
> + | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S
> | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
> @@ -179,14 +179,15 @@ DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move",
> /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits. */
> DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
> m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
> - | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)
> + | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S
> + | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
> Some chips, like 486 and Pentium works faster with separate load
> and push instructions. */
> DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
> m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
> - | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
> + | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S
> | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
> @@ -258,7 +259,7 @@ DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
> ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
> | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GOLDMONT
> | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
> - | m_CORE_ATOM | m_LUJIAZUI | m_GENERIC))
> + | m_ARROWLAKE_S | m_CORE_ATOM | m_LUJIAZUI | m_GENERIC))
>
> /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
> for DFmode copies */
> @@ -266,7 +267,7 @@ DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
> ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
> | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_LUJIAZUI
> | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
> - | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC))
> + | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC))
>
> /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
> will impact LEA instruction selection. */
> @@ -304,7 +305,7 @@ DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA)
> move/set sequences of bytes with known size. */
> DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB,
> "prefer_known_rep_movsb_stosb",
> - m_SKYLAKE | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM
> + m_SKYLAKE | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM
> | m_TREMONT | m_CORE_AVX512 | m_LUJIAZUI)
>
> /* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of
> @@ -315,14 +316,14 @@ DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB,
> DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
> "misaligned_move_string_pro_epilogues",
> m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_LUJIAZUI | m_TREMONT
> - | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)
> + | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_USE_SAHF: Controls use of SAHF. */
> DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
> m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
> | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
> | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS
> - | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM
> + | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S| m_CORE_ATOM
> | m_GENERIC)
>
> /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
> @@ -335,7 +336,7 @@ DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
> m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
> | m_LAKEMONT | m_AMD_MULTIPLE | m_LUJIAZUI | m_GOLDMONT
> | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
> - | m_CORE_ATOM | m_GENERIC)
> + | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
> for bit-manipulation instructions. */
> @@ -355,12 +356,12 @@ DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4)
> DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
> m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
> | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
> - | m_CORE_ATOM | m_LUJIAZUI | m_GENERIC)
> + | m_ARROWLAKE_S | m_CORE_ATOM | m_LUJIAZUI | m_GENERIC)
>
> /* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */
> DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
> m_CORE_ALL | m_BDVER | m_ZNVER | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE
> - | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)
> + | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
> generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
> @@ -385,7 +386,7 @@ DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
> ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
> | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE
> | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
> - | m_ALDERLAKE | m_ARROWLAKE | m_CORE_ATOM
> + | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM
> | m_GENERIC))
>
> /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */
> @@ -396,7 +397,7 @@ DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
> m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
> | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_LUJIAZUI
> | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
> - | m_CORE_ATOM | m_GENERIC)
> + | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC)
>
> /*****************************************************************************/
> /* SSE instruction selection tuning */
> @@ -412,7 +413,7 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
> DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
> m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
> | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
> - | m_ARROWLAKE | m_CORE_ATOM | m_AMDFAM10 | m_BDVER
> + | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_AMDFAM10 | m_BDVER
> | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GENERIC)
>
> /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores
> @@ -420,7 +421,7 @@ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
> DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
> m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
> | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
> - | m_ARROWLAKE | m_CORE_ATOM | m_BDVER | m_ZNVER
> + | m_ARROWLAKE | m_ARROWLAKE_S| m_CORE_ATOM | m_BDVER | m_ZNVER
> | m_LUJIAZUI | m_GENERIC)
>
> /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
> @@ -431,13 +432,13 @@ DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optim
> /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */
> DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
> m_AMD_MULTIPLE | m_LUJIAZUI | m_CORE_ALL | m_TREMONT | m_ALDERLAKE
> - | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC)
> + | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
> xorps/xorpd and other variants. */
> DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
> m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
> - | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE
> + | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S
> | m_CORE_ATOM | m_GENERIC)
>
> /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
> @@ -485,13 +486,13 @@ DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb",
> /* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */
> DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes",
> m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
> - | m_ARROWLAKE | m_CORE_ATOM | m_INTEL)
> + | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_INTEL)
>
> /* X86_TUNE_USE_GATHER_2PARTS: Use gather instructions for vectors with 2
> elements. */
> DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts",
> ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE
> - | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC | m_GDS))
> + | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC | m_GDS))
>
> /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2
> elements. */
> @@ -502,7 +503,7 @@ DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts",
> elements. */
> DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts",
> ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE
> - | m_ARROWLAKE | m_CORE_ATOM | m_GENERIC | m_GDS))
> + | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC | m_GDS))
>
> /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4
> elements. */
> @@ -513,7 +514,7 @@ DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts",
> elements. */
> DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "use_gather_8parts",
> ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER4 | m_ALDERLAKE | m_ARROWLAKE
> - | m_CORE_ATOM | m_GENERIC | m_GDS))
> + | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC | m_GDS))
>
> /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more
> elements. */
> @@ -527,7 +528,7 @@ DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER1 | m_ZNVER2
> /* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or
> smaller FMA chain. */
> DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains", m_ZNVER2 | m_ZNVER3
> - | m_ALDERLAKE | m_ARROWLAKE | m_SAPPHIRERAPIDS
> + | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S | m_SAPPHIRERAPIDS
> | m_CORE_ATOM)
>
> /* X86_TUNE_AVOID_512FMA_CHAINS: Avoid creating loops with tight 512bit or
> @@ -572,13 +573,13 @@ DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4)
> /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
> AVX instructions. */
> DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
> - m_ALDERLAKE | m_ARROWLAKE | m_CORE_AVX2 | m_ZNVER1
> + m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_AVX2 | m_ZNVER1
> | m_ZNVER2 | m_ZNVER3)
>
> /* X86_TUNE_AVX256_STORE_BY_PIECES: Optimize store_by_pieces with 256-bit
> AVX instructions. */
> DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES, "avx256_store_by_pieces",
> - m_ALDERLAKE | m_ARROWLAKE | m_CORE_AVX2 | m_ZNVER1
> + m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_AVX2 | m_ZNVER1
> | m_ZNVER2 | m_ZNVER3)
>
> /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
> --
> 2.31.1
>
--
BR,
Hongtao
prev parent reply other threads:[~2023-08-24 3:39 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-23 4:31 liuhongt
2023-08-24 3:39 ` Hongtao Liu [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAMZc-byLKC3ZeLfWQpU06+eX5ON3CPAJuHdHstz7AtR-L6zr2w@mail.gmail.com \
--to=crazylht@gmail.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=hjl.tools@gmail.com \
--cc=hongtao.liu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).