From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb2e.google.com (mail-yb1-xb2e.google.com [IPv6:2607:f8b0:4864:20::b2e]) by sourceware.org (Postfix) with ESMTPS id 8F985385829C for ; Fri, 15 Mar 2024 03:35:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8F985385829C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8F985385829C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::b2e ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1710473726; cv=none; b=ZUPsK5WLvtsQoD3InHjm+iqiaGBi3HjDZFGcaB0wpGMxTn+UsEMMS+vZ036MjFPq/Et01HzDxLCh0ZDyavjmlCmqfvIxD2N8sMWEim0PntJDtNhBWsOWqo8AkrY0sEPwgYpNVWUDEDcYnRUZDJGFZaCQ9Af3AKVkC9HtVpGqz64= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1710473726; c=relaxed/simple; bh=s3hKrDHUsWGMCwIo+IzGxftBW41V3z4eMeTE83q4Elw=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=f+S5C78WeijGC9mEJelGtQGtzuaF0MRr+W+AaRZ723ptMTFntlGqVVNjdoJ9+O3zgnr9UQLdEGPtj4NafxE61AC9QHOUCA2UKO/7e5g43cnGy0PEjZ7b8gIjXYi6I8kKFP1FYkEwIVEHu+b8IulACkYh5RLJws3NCsCBkv9fh0A= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-yb1-xb2e.google.com with SMTP id 3f1490d57ef6-dc6dcd9124bso1621417276.1 for ; Thu, 14 Mar 2024 20:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1710473723; x=1711078523; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=76dmkTGmwE9gi1kjpvcUvIvvFye+Y0/WLeT2Ofqf1AQ=; b=mfLS8c4iLUFvkdlZmY9iYyO6i+zz5X0G6ovLnX7ginDWczQv8CQi5f04suKhT6CkYO NlkwRFTp/eigwwx1ZxTJCzUnL2cEwCzDnfxVTkAVz2EcH2SiXtUJoEYDb4GSYh+50FoS oQO2yJx4PVv4WX2mxq3y3PYIryJGz27kFNIw+nKYo+bWXPumigyQlxxGIpGdb350Xlfa t9YTMZarT42PpXE0exYH/W7XzcZGiDnMxGCzwWFsDHS4ry6UGhiNAZzLElMi83FQUWlK 1tcIaMBgipiGF9kwCcWFqV5bjXcTGsjgNFA1/QodYWQqYV+XhacbdnGjcV8FeNLF30LT gl3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710473723; x=1711078523; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=76dmkTGmwE9gi1kjpvcUvIvvFye+Y0/WLeT2Ofqf1AQ=; b=ujA8rVPRM9LxSKZZmSr31u+YAxQfC+zt6yeU5dnc5AnZRTFu71IN8Y0zu1cOnrblM8 T6oWe6Rlw/svPBeZpLodohSWD/MlbsaKMdlJAhPaJLw7xAI5opTEQIk05KIbdv89ff5M ghquZYUTVq69/wrwd75OcWTBrrEzOyh4cdD/z5+0NOoCZhkrwrJ2BPdulqli3Eu/RyR2 GC91nnP98UZzoIdP0XlgAFKhRt08fwFhXOZz2xitlaWNErKb1zX0dR2yUxMvXqesokkx 6Fe+uDTZh4vVMYx/wtkU7RbIQDBJyOpE8jqS4GUfVLMjNESQUzivYFP+dSs4rbwIyBkx D1Sw== X-Gm-Message-State: AOJu0YyM8QgbhSO3H2vfVsyVzOs4lqJHQoTzi4/Y7I+kmh/cwf7ggW65 mq3LaYWKXeQdgyv5c5GnzMylohkV/Ru3Zvk8giT+6xP1QMqz37HjEugC7TI2DRhJFQoi7pk+18Y +5r79EqyM+eVnLzpQhhMez4UrT9s= X-Google-Smtp-Source: AGHT+IFgV3fsRKzLbCQU6kEjSaZ11sA0M/uXPtmId+Ul2RGWqj2fIPWiQXTI6HCqI9FZqR2rPvDQjcTlsl7xC66282I= X-Received: by 2002:a25:ab8e:0:b0:dcc:140a:a71f with SMTP id v14-20020a25ab8e000000b00dcc140aa71fmr894966ybi.60.1710473722537; Thu, 14 Mar 2024 20:35:22 -0700 (PDT) MIME-Version: 1.0 References: <20240314154153.263896-1-ams@baylibre.com> In-Reply-To: <20240314154153.263896-1-ams@baylibre.com> From: Hongtao Liu Date: Fri, 15 Mar 2024 11:45:58 +0800 Message-ID: Subject: Re: [PATCH] vect: Use xor to invert oversized vector masks To: Andrew Stubbs Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Mar 14, 2024 at 11:42=E2=80=AFPM Andrew Stubbs w= rote: > > Don't enable excess lanes when inverting vector bit-masks smaller than th= e > integer mode. This is yet another case of wrong-code due to mishandling > of oversized bitmasks. > > This issue shows up in vect/tsvc/vect-tsvc-s278.c and > vect/tsvc/vect-tsvc-s279.c if I set the preferred vector size to V32 > (down from V64) on amdgcn. > > OK for mainline? > > Andrew > > gcc/ChangeLog: > > * expr.cc (expand_expr_real_2): Use xor to invert vector masks. > --- > gcc/expr.cc | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/gcc/expr.cc b/gcc/expr.cc > index 403eeaa108e4..3540327d879e 100644 > --- a/gcc/expr.cc > +++ b/gcc/expr.cc > @@ -10497,6 +10497,17 @@ expand_expr_real_2 (sepops ops, rtx target, mach= ine_mode tmode, > immed_wide_int_const (mask, int_mode), > target, 1, OPTAB_LIB_WIDEN); > } > + /* If it's a vector mask don't enable excess bits. */ > + else if (VECTOR_BOOLEAN_TYPE_P (type) > + && SCALAR_INT_MODE_P (mode) > + && maybe_ne (GET_MODE_PRECISION (mode), > + TYPE_VECTOR_SUBPARTS (type).to_constant ())) > + { > + auto nunits =3D TYPE_VECTOR_SUBPARTS (type).to_constant (); > + temp =3D expand_binop (mode, xor_optab, op0, > + GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1)= , > + target, true, OPTAB_WIDEN); > + } Not review, just curious, should the issue be fixed by the commit in PR1135= 76. Also wonder besides cbranch, excess land bits also matter? https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113576#c35 > else > temp =3D expand_unop (mode, one_cmpl_optab, op0, target, 1); > gcc_assert (temp); > -- > 2.41.0 > --=20 BR, Hongtao