From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa35.google.com (mail-vk1-xa35.google.com [IPv6:2607:f8b0:4864:20::a35]) by sourceware.org (Postfix) with ESMTPS id B8BDE3858423 for ; Mon, 7 Mar 2022 02:15:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B8BDE3858423 Received: by mail-vk1-xa35.google.com with SMTP id j201so7231632vke.11 for ; Sun, 06 Mar 2022 18:15:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=f1sogOIgK/Bqf/o+nahDY3HSgHpnhznzpSNTdG/6qE0=; b=HA4x+kLxu3Z3iLMPYqe6cO7awx6sZheBi4tBP0l9hLsJvdPEjWGRwBokQd/OCHHEaS hpp8IDuMAYaU74ECSwep/NrGeWkEAm7DahVK3C4lxEIpPD5k3tG4dJdLMxpmtXZWtDGn qCgdbH/klkUR9LguM/gQNk4Yc3zl5oDgbAWO6e8HfobM1rdoPjXGkIxCndhzsBrVZ35r sZaWJSKNUFFmn6RQBWLjKIHx/YPhtTIXKOtWAv0X1j/Vz5eZL7mPouKTSS626oCZVlbo Dr8PQPRxsgrljdklO8ikr4ZNEG8S5DkHf2SiFBuR1byQ2wWap9HNg5uc2b9Nyf9lh3Sv LNBQ== X-Gm-Message-State: AOAM531iwEOOrPS4lP/WBxsQyj3IdZNAeWvxSt3TZwG8d19EEF7i5XzS 5prsHh+0A0aYSusmyC6rCuDakxf4i0WQzhWjJPWtAU5/VlKQ2g== X-Google-Smtp-Source: ABdhPJxyGagrMFzeEOB6e5uOo6/esq526a7sEp/Z5LLg60WoOOOaH6mr2zjUaIBvLfEee0m+94k72X8ks32ngTsHBOU= X-Received: by 2002:a05:6122:1079:b0:32c:a52c:88a5 with SMTP id k25-20020a056122107900b0032ca52c88a5mr3213595vko.19.1646619359255; Sun, 06 Mar 2022 18:15:59 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Hongtao Liu Date: Mon, 7 Mar 2022 10:15:48 +0800 Message-ID: Subject: Re: [PATCH] i386: Fix up cond_{and,ior,xor,mul}* [PR104779] To: Jakub Jelinek Cc: Uros Bizjak , GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Mar 2022 02:16:02 -0000 On Sat, Mar 5, 2022 at 4:05 PM Jakub Jelinek wrote: > > Hi! > > The following testcase ICEs, because the cond_andv* expander > has vector_operand predicates in both of the commutative inputs > and calls gen_andv*_mask which calls ix86_binary_operator_ok > in its condition, but nothing calls ix86_fixup_binary_operands_no_copy > during the expansion, which means cond_* accepts even operands > like 2 MEMs which then can't be matched. > > The following patch handles it like most other insns that the other > cond_* patterns use - by having a separate define_expand that calls > ix86_fixup_binary_operands_no_copy and define_ins with > ix86_binary_operator_ok. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? Ok. > > Note, the predicates on cond_fma* and other FMA variants look all wrong to > me, usually the fma instructions require nonimmediate_operand operands, > but the cond_* patterns use vector_operand. Besides what this patch --------cut from predicate.md--------- 1142; Return true when OP is operand acceptable for vector memory operand. 1143; Only AVX can have misaligned memory operand. 1144(define_predicate "vector_memory_operand" 1145 (and (match_operand 0 "memory_operand") 1146 (ior (match_test "TARGET_AVX") 1147 (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)")))) 1148 1149; Return true when OP is register_operand or vector_memory_operand. 1150(define_predicate "vector_operand" 1151 (ior (match_operand 0 "register_operand") 1152 (match_operand 0 "vector_memory_operand"))) --------cut end------------------------ vector_operand is a subset of nonimmediate_operands, so it's more like a potential optimization issue rather than a correctness one? > fixes and the unfixed fma which I don't have spare cycles for right > now I went through all the other cond_* patterns checking for predicate > mismatches or similar missing ix86_fixup_binary_operands* issues and > didn't find other problems. > > 2022-03-05 Jakub Jelinek > > PR target/104779 > * config/i386/sse.md (avx512dq_mul3): New > define_expand pattern. Rename define_insn to ... > (*avx512dq_mul3): ... this. > (3_mask): New any_logic define_expand pattern. > (3): Rename to ... > (*3): ... this. > > * gcc.target/i386/pr104779.c: New test. > > --- gcc/config/i386/sse.md.jj 2022-02-24 15:27:14.722743984 +0100 > +++ gcc/config/i386/sse.md 2022-03-04 13:56:34.863572916 +0100 > @@ -15210,7 +15210,15 @@ (define_expand "cond_mul" > DONE; > }) > > -(define_insn "avx512dq_mul3" > +(define_expand "avx512dq_mul3" > + [(set (match_operand:VI8_AVX512VL 0 "register_operand") > + (mult:VI8_AVX512VL > + (match_operand:VI8_AVX512VL 1 "bcst_vector_operand") > + (match_operand:VI8_AVX512VL 2 "bcst_vector_operand")))] > + "TARGET_AVX512DQ && " > + "ix86_fixup_binary_operands_no_copy (MULT, mode, operands);") > + > +(define_insn "*avx512dq_mul3" > [(set (match_operand:VI8_AVX512VL 0 "register_operand" "=v") > (mult:VI8_AVX512VL > (match_operand:VI8_AVX512VL 1 "bcst_vector_operand" "%v") > @@ -16824,7 +16832,18 @@ (define_expand "cond_" > DONE; > }) > > -(define_insn "3" > +(define_expand "3_mask" > + [(set (match_operand:VI48_AVX512VL 0 "register_operand") > + (vec_merge:VI48_AVX512VL > + (any_logic:VI48_AVX512VL > + (match_operand:VI48_AVX512VL 1 "bcst_vector_operand") > + (match_operand:VI48_AVX512VL 2 "bcst_vector_operand")) > + (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand") > + (match_operand: 4 "register_operand")))] > + "TARGET_AVX512F" > + "ix86_fixup_binary_operands_no_copy (, mode, operands);") > + > +(define_insn "*3" > [(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,x,v") > (any_logic:VI48_AVX_AVX512F > (match_operand:VI48_AVX_AVX512F 1 "bcst_vector_operand" "%0,x,v") > --- gcc/testsuite/gcc.target/i386/pr104779.c.jj 2022-03-04 14:09:03.278961269 +0100 > +++ gcc/testsuite/gcc.target/i386/pr104779.c 2022-03-04 14:08:38.063318794 +0100 > @@ -0,0 +1,27 @@ > +/* PR target/104779 */ > +/* { dg-do compile } */ > +/* { dg-options "-O1 --param sccvn-max-alias-queries-per-access=0" } */ > + > +__attribute__ ((simd)) int > +foo (int x, int y, int z) > +{ > + return (x & y) * !!z; > +} > + > +__attribute__ ((simd)) int > +bar (int x, int y, int z) > +{ > + return (x | y) * !!z; > +} > + > +__attribute__ ((simd)) int > +baz (int x, int y, int z) > +{ > + return (x ^ y) * !!z; > +} > + > +__attribute__ ((simd, target ("avx512dq"))) long > +qux (long x, long y, long z) > +{ > + return (x * y) * !!z; > +} > > Jakub > -- BR, Hongtao