From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112f.google.com (mail-yw1-x112f.google.com [IPv6:2607:f8b0:4864:20::112f]) by sourceware.org (Postfix) with ESMTPS id 524973888829 for ; Tue, 15 Nov 2022 09:37:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 524973888829 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x112f.google.com with SMTP id 00721157ae682-381662c78a9so50895267b3.7 for ; Tue, 15 Nov 2022 01:37:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=t3+cC/Z4BLoZ+J94v+x0QdT14fSbj2cxsMAeuHfoxTs=; b=HS7lDpGMWClTG14674kZWIiTJdv9MaNtVMo3utcDh4Snbdlr0MeHOxIkSPpbeOcWdw a5pYnd5z26Z17pTqZhF2VXxTLVokFhlww0reRlDDp9WxXeXC1yKzFWZFamGvbd+QOdRD RNo/SrjjGTWiPDD4UTLiHTrMieD/giygNRrpKbW0dIGnnOXyJI+0gN9vgOq6vJVgDD7T sPVWC58uZH84pN6/Ymobq/EfLJF+3YQbsgqvqtYmsGm8fuCoPgE6COjSynT1xCidRpgU h24Zbr+vVQb/2LEfa50hmyQDkdeoilZzsRFAH/tHmtsOrF8vSBaPZDCQdHGL0sgQaxl2 /GCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t3+cC/Z4BLoZ+J94v+x0QdT14fSbj2cxsMAeuHfoxTs=; b=AaxZKGkMFQCuSNJwPca/DpPmoHbdLBhUnMh1NctzA0nAL0Ui5AiQRibEEQovfApNg9 GwJsuydzeYcbn9JZDTNs6ZVMYhYl4Hzy1SJdzXaupLi0mb0Jv5CBVpGtgXQ2IxaY/icE Swes1oYnpDf6KYrV61UY9FtVyaVpPX8l0dAhX0TvEKthe5hIZepZF7XuXolWwRd6cL5/ XU6P5tvnBGDM1QCyzUZCCEJAzbTQbiLELw0vrMpKQYyAr1S4pSQMFjOEzJQetY7pXPVq DapwU3L+Kc+TLgo6dhmWgIoCIW1qLWxFNHmnJkyeJI3s2V7S5erg4X4Lz7IddPneBGoI LHwQ== X-Gm-Message-State: ANoB5pkAqtyyD9EplL1+eO2o4Uc4Ac2WMywsKpFddZl8lVs9e9rw4qxU avP7jxrlG5VDUKfhPxEYTmJL2ECgK/NTe3w9epA= X-Google-Smtp-Source: AA0mqf5F7ePvMnjHcI2axoz5oMsScFJqY0Zt7dLAakXgcaDMn81+F3wh0HMfTTNnN6xlY9fbRuJD4sERWINNISj/Q68= X-Received: by 2002:a81:5045:0:b0:377:54e7:ef44 with SMTP id e66-20020a815045000000b0037754e7ef44mr16692934ywb.486.1668505056711; Tue, 15 Nov 2022 01:37:36 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Hongtao Liu Date: Tue, 15 Nov 2022 17:37:24 +0800 Message-ID: Subject: Re: [PATCH 3/8]middle-end: Support extractions of subvectors from arbitrary element position inside a vector To: Tamar Christina Cc: Richard Sandiford , Tamar Christina via Gcc-patches , nd , "rguenther@suse.de" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Nov 15, 2022 at 4:51 PM Tamar Christina w= rote: > > > -----Original Message----- > > From: Hongtao Liu > > Sent: Tuesday, November 15, 2022 8:36 AM > > To: Tamar Christina > > Cc: Richard Sandiford ; Tamar Christina via > > Gcc-patches ; nd ; > > rguenther@suse.de > > Subject: Re: [PATCH 3/8]middle-end: Support extractions of subvectors f= rom > > arbitrary element position inside a vector > > > > Hi: > > I'm from https://gcc.gnu.org/pipermail/gcc-patches/2022- > > November/606040.html. > > > } > > > > > > /* See if we can get a better vector mode before extracting. */ > > > diff --git a/gcc/optabs.cc b/gcc/optabs.cc index > > > > > cff37ccb0dfc3dd79b97d0abfd872f340855dc96..f338df410265dfe55b689616009 > > 0 > > > a453cc6a28d9 100644 > > > --- a/gcc/optabs.cc > > > +++ b/gcc/optabs.cc > > > @@ -6267,6 +6267,7 @@ expand_vec_perm_const (machine_mode mode, > > rtx v0, rtx v1, > > > v0_qi =3D gen_lowpart (qimode, v0); > > > v1_qi =3D gen_lowpart (qimode, v1); > > > if (targetm.vectorize.vec_perm_const !=3D NULL > > > + && targetm.can_change_mode_class (mode, qimode, ALL_REGS) > > It looks like you want to guard gen_lowpart, shouldn't it be better to = use > > validate_subreg or (tmp =3D gen_lowpart_if_possible (mode, target_qi))= . > > IMHO, targetm.can_change_mode_class is mostly used for RA, but not to > > guard gen_lowpart. > > Hmm I don't think this is quite true, there are existing usages in expr.c= c and rtanal.cc > That do this and aren't part of RA. As I mentioned before for instance t= he > canoncalization of vec_select to subreg in rtlanal for instances uses thi= s. In theory, we need to iterate through all reg classes that can be assigned for both qimode and mode, if any regclass returns true for targetm.can_change_mode_class, the bitcast(validate_subreg) should be ok. Here we just passed ALL_REGS. > > So there are already existing precedence for this. And the documentation= for > the hook says: > > "This hook returns true if it is possible to bitcast values held in regis= ters of class rclass from mode from to mode to and if doing so preserves th= e low-order bits that are common to both modes. The result is only meaningf= ul if rclass has registers that can hold both from and to. The default impl= ementation returns true" > > So it looks like it's use outside of RA is perfectly valid.. and the docu= mentation also mentions > in the example the use from the mid-end as an example. > > But if the mid-end maintainers are happy I'll use something else. > > Tamar > > > I did similar things in > > https://gcc.gnu.org/pipermail/gcc-patches/2021-September/579296.html > > (and ALL_REGS doesn't cover all cases for registers which are both avai= lable > > for qimode and mode, ALL_REGS fail doesn't mean it can't be subreg, it = just > > means parts of ALL_REGS can't be subreg. but with a subset of ALL_REGS, > > there could be a reg class which return true for > > targetm.can_change_mode_class) > > > && targetm.vectorize.vec_perm_const (qimode, qimode, target= _qi, > > v0_qi, > > > v1_qi, qimode_indices)= ) > > > return gen_lowpart (mode, target_qi); @@ -6311,7 +6312,8 @@ > > > expand_vec_perm_const (machine_mode mode, rtx v0, rtx v1, > > > } > > > > > > if (qimode !=3D VOIDmode > > > - && selector_fits_mode_p (qimode, qimode_indices)) > > > + && selector_fits_mode_p (qimode, qimode_indices) > > > + && targetm.can_change_mode_class (mode, qimode, ALL_REGS)) > > > { > > > icode =3D direct_optab_handler (vec_perm_optab, qimode); > > > if (icode !=3D CODE_FOR_nothing) > > > diff --git a/gcc/testsuite/gcc.target/aarch64/ext_1.c > > > b/gcc/testsuite/gcc.target/aarch64/ext_1.c > > > new file mode 100644 > > > index > > > > > 0000000000000000000000000000000000000000..18a10a14f1161584267a8472e5 > > 71 > > > b3bc2ddf887a > > > > > > > > > > -- > > BR, > > Hongtao --=20 BR, Hongtao