From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb36.google.com (mail-yb1-xb36.google.com [IPv6:2607:f8b0:4864:20::b36]) by sourceware.org (Postfix) with ESMTPS id 4AF0C3858C98 for ; Mon, 26 Feb 2024 03:31:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4AF0C3858C98 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4AF0C3858C98 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::b36 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708918285; cv=none; b=oF9D6FwG/8fHSKqSPX0JyhjCkZ7JKeKVmq+lxg/rJGTrEE5MT4qEisV0FFa9RrVwTR5tu9DOygx5kTvhOl2Mz8kwa50YGEZ2sXzO7BPDiRDVZtrjHq4RFmizW7mhZdzkNwoSLlvCn2KxjpXHhPQdUQkinrRNedJ8/s7UL5r3h0E= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708918285; c=relaxed/simple; bh=EgS7icws40QRWKYDInW0RmrC0TnjZPWgqTbvTLvk5QM=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=olUT52U7g2WlwyE4gRwjSS43WrBSFDTCgEXophKlSR3z7NN5CnmCxQH8GPZ0QYufvTnfEFj0Ewkh6IzG3sNWWeCALQ9DakyjNhLjPM8f4GOIrj3xDCjYN3EXgDmXRINWXfxsmfvKPfs1201cStmSBwLhnRim+ZOd3ZtrrMLLqCA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-yb1-xb36.google.com with SMTP id 3f1490d57ef6-dc6d9a8815fso2325072276.3 for ; Sun, 25 Feb 2024 19:31:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1708918282; x=1709523082; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=WwOq74ayHwJckpRRvDvQi32ebQwjd812JqnqUPY3PvE=; b=GY7cfKqYkGqAilTypxKEts7U7ch+1z7szobKT9OYTbRfat3ZwcpRFyDOUZHIqy3tCU fO9OG4PXUlzq9O1dWQ/MqzzCalL16TwE6/Xg/4yHprn/BsFEZQLa7dIo90ErZR3Su3u1 L65JYzyyRhhqWMN2pSzK56LtIzCCNF5JO2g0wEjpSXbA9dXBFsrKFYWagPUpTVuvQizk Jb+A2yspn3xwYm4rl/neY3p2I+FwZbdRsYRu3zyO1Q1GDY3lrdpW1Bv2njBvMci2Nacd 93wwffGWb2c/89BU3rdGUsrW3zPMiVsQ26MmSQvXspm9S3X8i41edtFdP5PmG261AHIk RXTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708918282; x=1709523082; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WwOq74ayHwJckpRRvDvQi32ebQwjd812JqnqUPY3PvE=; b=syiXSPkxb+JUz1QGQWml2MdEtz9mMN73Xhb76UE3y3DgKV59jZy+rEmw/p8+52MQal zBP1d8eenKZw8pwwlZ9Dv4JJ7t1TUh6rd2h2XtVPoQWTgLAfR4fdUBgbztkcTil7ax1c EeGykZonxzXGWKNp83HEnnUr4rFMrc6hEQ9lqtIkCmIhVJeCUOOWsOWyfqtDOIFx3BnJ HPRndz0ZzQJ9SL9syaWyYZseXy9Zppir22Z7y3gA4q1YB1usYjAYYBTE9xTS1F0vGp6v Riu/19toVo+gbm+wtHgZZ68hWxvCNBOyAXOXkcB3vxf0lG/ajUDMEoB6Zr4pKsp8psAa 3x8w== X-Gm-Message-State: AOJu0YzbFCvOT7dBZ23Q4FsyxsMyO0oWW25/m+/cfeJ4/SbBsLIQBMDH wzhHzf4esKbE31PlYL9DJ5Zan7tsuHTXiy9xXQuYT8lLY3/YpoN/NHvyFShnyTft17rV+mJMdFo OoB2V4gc9n/n2ootb9Ayfj8DrGOA= X-Google-Smtp-Source: AGHT+IEaesoVa8xZ9AvWYvsZwAiuDB7SXqNqDo/ECpPXizp3xMX1gbkWVL4UcAVb1X6eeU5mEwhkVXq/pw1X7X5H5LA= X-Received: by 2002:a25:add0:0:b0:dc6:ba11:6edd with SMTP id d16-20020a25add0000000b00dc6ba116eddmr4373182ybe.8.1708918282527; Sun, 25 Feb 2024 19:31:22 -0800 (PST) MIME-Version: 1.0 References: <20240226032558.587912-1-pan2.li@intel.com> In-Reply-To: <20240226032558.587912-1-pan2.li@intel.com> From: Hongtao Liu Date: Mon, 26 Feb 2024 11:41:16 +0800 Message-ID: Subject: Re: [PATCH v1] RTL: Bugfix ICE after allow vector type in DSE To: pan2.li@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, richard.guenther@gmail.com, yanzhang.wang@intel.com, rdapp.gcc@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Feb 26, 2024 at 11:26=E2=80=AFAM wrote: > > From: Pan Li > > We allowed vector type for get_stored_val when read is less than or > equal to store in previous. Unfortunately, we missed to adjust the > validate_subreg part accordingly. For vector type, we don't need to > restrict the mode size is greater than the vector register size. > > Thus, for example when gen_lowpart from E_V2SFmode to E_V4QImode, it > will have NULL_RTX(of course ICE after that) because of the mode size > is less than vector register size. That also explain that gen_lowpart > from E_V8SFmode to E_V16QImode is valid here. > > This patch would like to remove the the restriction for vector mode, to > rid of the ICE when gen_lowpart because of validate_subreg fails. Be Careful, It may regresses some other backend. > > The below test are passed for this patch: > > * The X86 bootstrap test. > * The fully riscv regression tests. > > gcc/ChangeLog: > > * emit-rtl.cc (validate_subreg): Bypass register size check > if the mode is vector. > > gcc/testsuite/ChangeLog: > > * gcc.dg/tree-ssa/ssa-fre-44.c: Add ftree-vectorize to trigger > the ICE. > * gcc.target/riscv/rvv/base/bug-6.c: New test. > > Signed-off-by: Pan Li > --- > gcc/emit-rtl.cc | 3 ++- > gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c | 2 +- > .../gcc.target/riscv/rvv/base/bug-6.c | 22 +++++++++++++++++++ > 3 files changed, 25 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c > > diff --git a/gcc/emit-rtl.cc b/gcc/emit-rtl.cc > index 1856fa4884f..45c6301b487 100644 > --- a/gcc/emit-rtl.cc > +++ b/gcc/emit-rtl.cc > @@ -934,7 +934,8 @@ validate_subreg (machine_mode omode, machine_mode imo= de, > ; > /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_fi= eld > is the culprit here, and not the backends. */ > - else if (known_ge (osize, regsize) && known_ge (isize, osize)) > + else if (known_ge (isize, osize) && (known_ge (osize, regsize) > + || (VECTOR_MODE_P (imode) || VECTOR_MODE_P (omode)))) > ; > /* Allow component subregs of complex and vector. Though given the be= low > extraction rules, it's not always clear what that means. */ > diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c b/gcc/testsuite/g= cc.dg/tree-ssa/ssa-fre-44.c > index f79b4c142ae..624a00a4f32 100644 > --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c > +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O -fdump-tree-fre1" } */ > +/* { dg-options "-O -fdump-tree-fre1 -O3 -ftree-vectorize" } */ > > struct A { float x, y; }; > struct B { struct A u; }; > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/bug-6.c > new file mode 100644 > index 00000000000..5bb00b8f587 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c > @@ -0,0 +1,22 @@ > +/* Test that we do not have ice when compile */ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O3 -ftree-vectorize" } = */ > + > +struct A { float x, y; }; > +struct B { struct A u; }; > + > +extern void bar (struct A *); > + > +float > +f3 (struct B *x, int y) > +{ > + struct A p =3D {1.0f, 2.0f}; > + struct A *q =3D &x[y].u; > + > + __builtin_memcpy (&q->x, &p.x, sizeof (float)); > + __builtin_memcpy (&q->y, &p.y, sizeof (float)); > + > + bar (&p); > + > + return x[y].u.x + x[y].u.y; > +} > -- > 2.34.1 > --=20 BR, Hongtao