From: Hongtao Liu <crazylht@gmail.com>
To: Hongyu Wang <hongyu.wang@intel.com>
Cc: gcc-patches@gcc.gnu.org, ubizjak@gmail.com, vmakarov@redhat.com,
jakub@redhat.com
Subject: Re: [PATCH v2 00/13] Support Intel APX EGPR
Date: Mon, 25 Sep 2023 10:02:13 +0800 [thread overview]
Message-ID: <CAMZc-bzDtAtLN40D40gkqjAYJANPzNmPXdj-m3d+HCoGZ7WVLA@mail.gmail.com> (raw)
In-Reply-To: <20230922105631.2298849-1-hongyu.wang@intel.com>
On Fri, Sep 22, 2023 at 6:56 PM Hongyu Wang <hongyu.wang@intel.com> wrote:
>
> Hi,
>
> This is a v2 patch for APX support which follows-up previous discussion in
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628904.html
>
> As discussed in previous thread, the inverse approach to extend base/index reg
> support with new memory constraints requrires much more effort both in
> middle-end and backend, so we keep the backend implementation logic. Also for
> inline asm, it is hard to provide memory constraint to use EGPR by force due to
> the limitation of base/index reg class hook, so we just add one register class
> that allows EGPR usage by force.
>
> The major changes are
>
> 1. Add new macros INSN_BASE_REG_CLASS/REGNO_OK_FOR_INSN_BASE_P instead of
> using old MODE_CODE macros.
> 2. Add a series of constraints that prohibits EGPR as counterparts of common
> constraints that may involve register/memory/address. All those are prefixed
> with "j" to avoid confilts with previous constraints.
> 3. Support constraint mapping for all gpr related common constraints in
> inline asm.
>
> Bootstrapped/regtested x86_64-linux-gnu.
> Ok for trunk?
I've pushed the patches to a vendor branch
b6dcc29fe45c214629bdb3ff9cf5bb08d06c0b81 refs/vendors/ix86/heads/apx
>
> Hongyu Wang (2):
> [APX EGPR] middle-end: Add index_reg_class with insn argument.
> [APX EGPR] Handle GPR16 only vector move insns
>
> Kong Lingling (11):
> [APX EGPR] middle-end: Add insn argument to base_reg_class
> [APX_EGPR] Initial support for APX_F
> [APX EGPR] Add 16 new integer general purpose registers
> [APX EGPR] Add register and memory constraints that disallow EGPR
> [APX EGPR] Add backend hook for base_reg_class/index_reg_class.
> [APX EGPR] Map reg/mem constraints in inline asm to non-EGPR
> constraint.
> [APX EGPR] Handle legacy insn that only support GPR16 (1/5)
> [APX EGPR] Handle legacy insns that only support GPR16 (2/5)
> [APX EGPR] Handle legacy insns that only support GPR16 (3/5)
> [APX_EGPR] Handle legacy insns that only support GPR16 (4/5)
> [APX EGPR] Handle vex insns that only support GPR16 (5/5)
>
> gcc/addresses.h | 29 +-
> gcc/common/config/i386/cpuinfo.h | 12 +-
> gcc/common/config/i386/i386-common.cc | 17 +
> gcc/common/config/i386/i386-cpuinfo.h | 1 +
> gcc/common/config/i386/i386-isas.h | 1 +
> gcc/config/i386/constraints.md | 65 +-
> gcc/config/i386/cpuid.h | 1 +
> gcc/config/i386/i386-isa.def | 1 +
> gcc/config/i386/i386-options.cc | 18 +
> gcc/config/i386/i386-opts.h | 8 +
> gcc/config/i386/i386-protos.h | 5 +
> gcc/config/i386/i386.cc | 303 ++++++-
> gcc/config/i386/i386.h | 69 +-
> gcc/config/i386/i386.md | 131 ++-
> gcc/config/i386/i386.opt | 30 +
> gcc/config/i386/mmx.md | 154 ++--
> gcc/config/i386/sse.md | 792 ++++++++++++------
> gcc/doc/invoke.texi | 11 +-
> gcc/doc/tm.texi | 21 +
> gcc/doc/tm.texi.in | 21 +
> gcc/lra-constraints.cc | 32 +-
> gcc/reload.cc | 34 +-
> gcc/reload1.cc | 2 +-
> gcc/testsuite/gcc.target/i386/apx-1.c | 8 +
> .../gcc.target/i386/apx-egprs-names.c | 17 +
> .../gcc.target/i386/apx-inline-gpr-norex2.c | 25 +
> .../gcc.target/i386/apx-interrupt-1.c | 102 +++
> .../i386/apx-legacy-insn-check-norex2-asm.c | 5 +
> .../i386/apx-legacy-insn-check-norex2.c | 181 ++++
> .../gcc.target/i386/apx-spill_to_egprs-1.c | 25 +
> gcc/testsuite/lib/target-supports.exp | 10 +
> 31 files changed, 1683 insertions(+), 448 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/apx-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/apx-egprs-names.c
> create mode 100644 gcc/testsuite/gcc.target/i386/apx-inline-gpr-norex2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/apx-interrupt-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c
> create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/apx-spill_to_egprs-1.c
>
> --
> 2.31.1
>
--
BR,
Hongtao
prev parent reply other threads:[~2023-09-25 2:02 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-22 10:56 Hongyu Wang
2023-09-22 10:56 ` [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class Hongyu Wang
2023-09-22 16:02 ` Vladimir Makarov
2023-10-07 8:22 ` Hongyu Wang
2023-09-22 10:56 ` [PATCH 02/13] [APX EGPR] middle-end: Add index_reg_class with insn argument Hongyu Wang
2023-09-22 16:03 ` Vladimir Makarov
2023-09-22 10:56 ` [PATCH 03/13] [APX_EGPR] Initial support for APX_F Hongyu Wang
2023-10-07 2:35 ` Hongtao Liu
2023-09-22 10:56 ` [PATCH 04/13] [APX EGPR] Add 16 new integer general purpose registers Hongyu Wang
2023-09-22 10:56 ` [PATCH 05/13] [APX EGPR] Add register and memory constraints that disallow EGPR Hongyu Wang
2023-09-22 10:56 ` [PATCH 06/13] [APX EGPR] Add backend hook for base_reg_class/index_reg_class Hongyu Wang
2023-09-22 10:56 ` [PATCH 07/13] [APX EGPR] Map reg/mem constraints in inline asm to non-EGPR constraint Hongyu Wang
2023-09-22 10:56 ` [PATCH 08/13] [APX EGPR] Handle GPR16 only vector move insns Hongyu Wang
2023-09-22 10:56 ` [PATCH 09/13] [APX EGPR] Handle legacy insn that only support GPR16 (1/5) Hongyu Wang
2023-09-22 10:56 ` [PATCH 10/13] [APX EGPR] Handle legacy insns that only support GPR16 (2/5) Hongyu Wang
2023-09-22 10:56 ` [PATCH 11/13] [APX EGPR] Handle legacy insns that only support GPR16 (3/5) Hongyu Wang
2023-09-22 10:56 ` [PATCH 12/13] [APX_EGPR] Handle legacy insns that only support GPR16 (4/5) Hongyu Wang
2023-09-22 10:56 ` [PATCH 13/13] [APX EGPR] Handle vex insns that only support GPR16 (5/5) Hongyu Wang
2023-09-25 2:02 ` Hongtao Liu [this message]
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