From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb30.google.com (mail-yb1-xb30.google.com [IPv6:2607:f8b0:4864:20::b30]) by sourceware.org (Postfix) with ESMTPS id 1118A3858D1E for ; Mon, 26 Feb 2024 05:04:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1118A3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1118A3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::b30 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708923847; cv=none; b=XmJuR3r1Tq4pmuqLyf6oh/mFlmkF+7o3gThP/8cJ9icyKDqOKNdzelZM1rGQk85UlMOBACd9A98zzAZHNr1NoSwXfI8UE5KafvYGjTcm8jPYhTPKHrGo7nT1bv0ZFGKXPWakolbhxf9yU9WEn4o7LlzW3OPQOtfQRME1lVVXyBk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708923847; c=relaxed/simple; bh=K9UfMT6o4Zp5v6fkIcvlrU00FRK7PCrafi5R6WVmVNk=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=cZzVHJcEcdU24g8Tv5vhTE2DHOMd0Y71mHilfAva8+tJUp9yitfrFNIQQyuH0qjpryqNgVIecunFHPbLEbR1PjrrZo85+x9jrDMXY/s2SOEi19R66bLCTq8mdnrKUp8BHcvDmb2NVPrRcac6dieS6Zf/Y5ALAkFe+CZktmPZgCo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-yb1-xb30.google.com with SMTP id 3f1490d57ef6-dcbc00f6c04so2677032276.3 for ; Sun, 25 Feb 2024 21:04:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1708923845; x=1709528645; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=RRNsy6+uBzxdPyEOrmEs+iZ7dx2JHIXzevrPK9PlEO4=; b=Ff32LhFmTQrZJi+3lOEk3buT/ZCQ0hJeZlkN2nIqWZ+Q724+T6NzSev3gANIgusLaX F857ILxzOhs2bjnRoyS5daliGNpcqn0VljZrEG6Zfyaj7VBelzKVaZuz92jEuLsWeG4A FW9MLFt9eu7YlXjX0H6rMtwpz++L4uEtxLNmq5tZYoTo7OozTzmrNhxbJezrRBI7opcm BQmHhwHai1oiQ2OH5Oc/cWZb9ssCsVrptBuxAMB2J2NPVqfUgQ8s07Kh+luAEShJeSd1 esRd11xIMnGp1yj6O9otwDnObzHuj8+jOgrDR16WFDx86CXls/AiigeUcWpFQQTash7h R0cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708923845; x=1709528645; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RRNsy6+uBzxdPyEOrmEs+iZ7dx2JHIXzevrPK9PlEO4=; b=wWJyyHLL/nKI0UApAJefQp/GgfLYCqpH/I4gzFSEBbzsyAqbct3lkKtix9R3hBKL2T sO9iBAOfo5CRX1e1cNght7pOCUEdcmNeahZVPVEYEpBYyOprGYvTjqWkTJR4YrB7fT7k u/iGFdW7CwZwuHoCiLx6Ei1WdRUHfkWplAFerfSxE1xg1KxD7BVpf9UuaspnLUBKfW0N qbWwDD6N2+qOuSy3o5Rc0LagxLuLE4fHnI9i63Z5gwboNHNHjILS5O4ut8yoA8Ti848/ sUeN7SiCaANNdpIyCx6zTrAlpuSpFmUZbD15dyoZ2MTRuWqgdxhTK+0Q+pJh/O6RO/kZ NMeg== X-Gm-Message-State: AOJu0YxBqgKbPFra54/O8FjBXuY8QHrjomnnaAqYuV3QIN5hrdp+oCOM GYyKOuYIyGM6I5FKkX6Vu3PLFIEYRKk5eU2rgLh6aVUrq0VYbuhSgupUVPTQB3HQrgw9g6Hwmlt ZeccmAV6YDdGVrmfjnqsEDBaefbM= X-Google-Smtp-Source: AGHT+IFd1v12w0IxIe7FhqIUkeDOjy9N835VtFfaoStCFch/plw2fsCz0T7dePRzRK07hEoHMekV8lSxmWhsYvPsQ18= X-Received: by 2002:a25:71c3:0:b0:dc6:a223:bb3b with SMTP id m186-20020a2571c3000000b00dc6a223bb3bmr3756671ybc.46.1708923845437; Sun, 25 Feb 2024 21:04:05 -0800 (PST) MIME-Version: 1.0 References: <20240226032558.587912-1-pan2.li@intel.com> In-Reply-To: From: Hongtao Liu Date: Mon, 26 Feb 2024 13:13:59 +0800 Message-ID: Subject: Re: [PATCH v1] RTL: Bugfix ICE after allow vector type in DSE To: "Li, Pan2" Cc: "gcc-patches@gcc.gnu.org" , "juzhe.zhong@rivai.ai" , "kito.cheng@gmail.com" , "richard.guenther@gmail.com" , "Wang, Yanzhang" , "rdapp.gcc@gmail.com" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Feb 26, 2024 at 11:42=E2=80=AFAM Li, Pan2 wrote= : > > > Be Careful, It may regresses some other backend. > > Thanks Hongtao, how about take INNER_MODE here for regsize. Currently it = will be the whole vector register when comparation. > > poly_uint64 regsize =3D REGMODE_NATURAL_SIZE (imode); > > Pan > > -----Original Message----- > From: Hongtao Liu > Sent: Monday, February 26, 2024 11:41 AM > To: Li, Pan2 > Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@gmail.com; = richard.guenther@gmail.com; Wang, Yanzhang ; rdapp= .gcc@gmail.com > Subject: Re: [PATCH v1] RTL: Bugfix ICE after allow vector type in DSE > > On Mon, Feb 26, 2024 at 11:26=E2=80=AFAM wrote: > > > > From: Pan Li > > > > We allowed vector type for get_stored_val when read is less than or > > equal to store in previous. Unfortunately, we missed to adjust the > > validate_subreg part accordingly. For vector type, we don't need to > > restrict the mode size is greater than the vector register size. > > > > Thus, for example when gen_lowpart from E_V2SFmode to E_V4QImode, it > > will have NULL_RTX(of course ICE after that) because of the mode size > > is less than vector register size. That also explain that gen_lowpart > > from E_V8SFmode to E_V16QImode is valid here. > > > > This patch would like to remove the the restriction for vector mode, to > > rid of the ICE when gen_lowpart because of validate_subreg fails. > Be Careful, It may regresses some other backend. The related thread. https://gcc.gnu.org/pipermail/gcc-patches/2021-August/578466.html > > > > The below test are passed for this patch: > > > > * The X86 bootstrap test. > > * The fully riscv regression tests. > > > > gcc/ChangeLog: > > > > * emit-rtl.cc (validate_subreg): Bypass register size check > > if the mode is vector. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.dg/tree-ssa/ssa-fre-44.c: Add ftree-vectorize to trigger > > the ICE. > > * gcc.target/riscv/rvv/base/bug-6.c: New test. > > > > Signed-off-by: Pan Li > > --- > > gcc/emit-rtl.cc | 3 ++- > > gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c | 2 +- > > .../gcc.target/riscv/rvv/base/bug-6.c | 22 +++++++++++++++++++ > > 3 files changed, 25 insertions(+), 2 deletions(-) > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c > > > > diff --git a/gcc/emit-rtl.cc b/gcc/emit-rtl.cc > > index 1856fa4884f..45c6301b487 100644 > > --- a/gcc/emit-rtl.cc > > +++ b/gcc/emit-rtl.cc > > @@ -934,7 +934,8 @@ validate_subreg (machine_mode omode, machine_mode i= mode, > > ; > > /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_= field > > is the culprit here, and not the backends. */ > > - else if (known_ge (osize, regsize) && known_ge (isize, osize)) > > + else if (known_ge (isize, osize) && (known_ge (osize, regsize) > > + || (VECTOR_MODE_P (imode) || VECTOR_MODE_P (omode)))) > > ; > > /* Allow component subregs of complex and vector. Though given the = below > > extraction rules, it's not always clear what that means. */ > > diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c b/gcc/testsuite= /gcc.dg/tree-ssa/ssa-fre-44.c > > index f79b4c142ae..624a00a4f32 100644 > > --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c > > +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c > > @@ -1,5 +1,5 @@ > > /* { dg-do compile } */ > > -/* { dg-options "-O -fdump-tree-fre1" } */ > > +/* { dg-options "-O -fdump-tree-fre1 -O3 -ftree-vectorize" } */ > > > > struct A { float x, y; }; > > struct B { struct A u; }; > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c b/gcc/test= suite/gcc.target/riscv/rvv/base/bug-6.c > > new file mode 100644 > > index 00000000000..5bb00b8f587 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c > > @@ -0,0 +1,22 @@ > > +/* Test that we do not have ice when compile */ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O3 -ftree-vectorize" = } */ > > + > > +struct A { float x, y; }; > > +struct B { struct A u; }; > > + > > +extern void bar (struct A *); > > + > > +float > > +f3 (struct B *x, int y) > > +{ > > + struct A p =3D {1.0f, 2.0f}; > > + struct A *q =3D &x[y].u; > > + > > + __builtin_memcpy (&q->x, &p.x, sizeof (float)); > > + __builtin_memcpy (&q->y, &p.y, sizeof (float)); > > + > > + bar (&p); > > + > > + return x[y].u.x + x[y].u.y; > > +} > > -- > > 2.34.1 > > > > > -- > BR, > Hongtao -- BR, Hongtao