From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb36.google.com (mail-yb1-xb36.google.com [IPv6:2607:f8b0:4864:20::b36]) by sourceware.org (Postfix) with ESMTPS id A09EC3858CDA for ; Tue, 11 Jul 2023 03:24:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A09EC3858CDA Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yb1-xb36.google.com with SMTP id 3f1490d57ef6-c84fd44593aso2055616276.0 for ; Mon, 10 Jul 2023 20:24:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689045842; x=1691637842; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=KmIXFC61tFegil5BTrt4o1STTYLRhXEUQAgxa62irUs=; b=NgjbMsxPi8QNjYbCFElpyHNVqe9YZ2JVl1Y+KiLJf69nDMbFn6oVCZWPvLqyt75cab pXPrW38V4TKSVihywyNAYl9Q/mvXXdfpMujVijQjhxqfNIKAFxOIDbDPw9ZujEeMibu9 yFsBWhHq25Jgw7YgL0+du6rVXm6W1hIyXAHD5mOH25/8ny7yHSjwQxgXLEyCJh1SX9+C BfWcdJi7CBlmcj9AyQ+PB6qgqokwJlscqXNz7WdDwNUG2gPKuOjTHMQ/KokSxGOGzZ+K 8Cbc5Jvm8MmIXCaRcH+zneeF0igETYhlF9RyxUTFkbiAa7sZMVZeyZ5ypCQAMjOInWkO SRTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689045842; x=1691637842; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KmIXFC61tFegil5BTrt4o1STTYLRhXEUQAgxa62irUs=; b=Gt0+nWgZs0Xbd4HHsrjilUD/yNVUIre1X+kNIQ9HpuvWETE7oe45aJWYx1qdZwKXTx IZKDNTXM6D4hFjYk7m+4jy09E1kcj6cl5ay0qIR3n+S0jRV+8GViCN8RX/c+SR/gVFKO Hgxy+0Kne2QzVwAXhB3OA3L8w+WramUTyJsw+3jUgq70NtX8QX2eYYUwgQCftrLTBy5u N1H0XRwFxUrjdj6INn7SV4KBjzwlVPfz/il34FpWiE+/D0AEZQ/ZxVc86ZJKC9o2fwpL QgkybPlo9BcXR00v+3b8Xyt2qUO1JGO7y25PwKbNzSJW04OubTKSF3uGL4aRQVt+789U PgXg== X-Gm-Message-State: ABy/qLaDe5Sxa11mnvz7MPMW7lYwb/JYXTGo65YwkdMM+iTCRgXcHYZv fYEX0nBr5J+oSY2NKcHxOLIVDlgF1mX5F6bICVs= X-Google-Smtp-Source: APBJJlGGXQBkW++tb64IkFgbpbbAtYCnnhQl5upeC+3qaPDtDJnfo2cBO/JtZNacaSTXCzyfYKOMNzpRcsYuDgUcr0M= X-Received: by 2002:a25:8c8f:0:b0:c66:abeb:de04 with SMTP id m15-20020a258c8f000000b00c66abebde04mr12730574ybl.18.1689045841826; Mon, 10 Jul 2023 20:24:01 -0700 (PDT) MIME-Version: 1.0 References: <20230711031356.3066611-1-hongtao.liu@intel.com> In-Reply-To: <20230711031356.3066611-1-hongtao.liu@intel.com> From: Hongtao Liu Date: Tue, 11 Jul 2023 11:23:50 +0800 Message-ID: Subject: Re: [PATCH] Add peephole to eliminate redundant comparison after cmpccxadd. To: liuhongt Cc: gcc-patches@gcc.gnu.org, ubizjak@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Please ignore this patch, I'm testing another patch to separate non swap operands case where a setcc is not needed in the peephole2. On Tue, Jul 11, 2023 at 11:14=E2=80=AFAM liuhongt via Gcc-patches wrote: > > Similar like we did for cmpxchg, but extended to all > ix86_comparison_int_operator since cmpccxadd set EFLAGS exactly same > as CMP. > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}, > Ok for trunk? > > gcc/ChangeLog: > > PR target/110591 > * config/i386/sync.md (cmpccxadd_): Add a new > define_peephole2 after the pattern. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/pr110591.c: New test. > --- > gcc/config/i386/sync.md | 56 ++++++++++++++++++++ > gcc/testsuite/gcc.target/i386/pr110591.c | 66 ++++++++++++++++++++++++ > 2 files changed, 122 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/i386/pr110591.c > > diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md > index e1fa1504deb..43f6421bcb8 100644 > --- a/gcc/config/i386/sync.md > +++ b/gcc/config/i386/sync.md > @@ -1105,3 +1105,59 @@ (define_insn "cmpccxadd_" > output_asm_insn (buf, operands); > return ""; > }) > + > +(define_peephole2 > + [(set (match_operand:SWI48x 0 "register_operand") > + (match_operand:SWI48x 1 "x86_64_general_operand")) > + (parallel [(set (match_dup 0) > + (unspec_volatile:SWI48x > + [(match_operand:SWI48x 2 "memory_operand") > + (match_dup 0) > + (match_operand:SWI48x 3 "register_operand") > + (match_operand:SI 4 "const_int_operand")] > + UNSPECV_CMPCCXADD)) > + (set (match_dup 2) > + (unspec_volatile:SWI48x [(const_int 0)] UNSPECV_CMPCCX= ADD)) > + (clobber (reg:CC FLAGS_REG))]) > + (set (reg FLAGS_REG) > + (compare (match_operand:SWI48x 5 "register_operand") > + (match_operand:SWI48x 6 "x86_64_general_operand"))) > + (set (match_operand:QI 7 "nonimmediate_operand") > + (match_operator:QI 8 "ix86_comparison_int_operator" > + [(reg FLAGS_REG) (const_int 0)]))] > + "TARGET_CMPCCXADD && TARGET_64BIT > + && ((rtx_equal_p (operands[0], operands[5]) > + && rtx_equal_p (operands[1], operands[6])) > + || ((rtx_equal_p (operands[0], operands[6]) > + && rtx_equal_p (operands[1], operands[5])) > + && peep2_regno_dead_p (4, FLAGS_REG)))" > + [(set (match_dup 0) > + (match_dup 1)) > + (parallel [(set (match_dup 0) > + (unspec_volatile:SWI48x > + [(match_dup 2) > + (match_dup 0) > + (match_dup 3) > + (match_dup 4)] > + UNSPECV_CMPCCXADD)) > + (set (match_dup 2) > + (unspec_volatile:SWI48x [(const_int 0)] UNSPECV_CMPCCX= ADD)) > + (clobber (reg:CC FLAGS_REG))]) > + (set (match_dup 7) > + (match_op_dup 8 > + [(match_dup 9) (const_int 0)]))] > +{ > + operands[9] =3D gen_rtx_REG (GET_MODE (XEXP (operands[8], 0)), FLAGS_R= EG); > + if (rtx_equal_p (operands[0], operands[6]) > + && rtx_equal_p (operands[1], operands[5]) > + && swap_condition (GET_CODE (operands[8])) !=3D GET_CODE (operands[= 8])) > + { > + operands[8] =3D shallow_copy_rtx (operands[8]); > + enum rtx_code ccode =3D swap_condition (GET_CODE (operands[8])); > + PUT_CODE (operands[8], ccode); > + operands[9] =3D gen_rtx_REG (SELECT_CC_MODE (ccode, > + operands[6], > + operands[5]), > + FLAGS_REG); > + } > +}) > diff --git a/gcc/testsuite/gcc.target/i386/pr110591.c b/gcc/testsuite/gcc= .target/i386/pr110591.c > new file mode 100644 > index 00000000000..32a515b429e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr110591.c > @@ -0,0 +1,66 @@ > +/* { dg-do compile { target { ! ia32 } } } */ > +/* { dg-options "-mcmpccxadd -O2" } */ > +/* { dg-final { scan-assembler-not {cmp[lq]?[ \t]+} } } */ > +/* { dg-final { scan-assembler-times {cmpoxadd[ \t]+} 12 } } */ > + > +#include > + > +_Bool foo_setg (int *ptr, int v) > +{ > + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) > v; > +} > + > +_Bool foo_setl (int *ptr, int v) > +{ > + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) < v; > +} > + > +_Bool foo_sete(int *ptr, int v) > +{ > + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) =3D=3D v; > +} > + > +_Bool foo_setne(int *ptr, int v) > +{ > + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) !=3D v; > +} > + > +_Bool foo_setge(int *ptr, int v) > +{ > + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) >=3D v; > +} > + > +_Bool foo_setle(int *ptr, int v) > +{ > + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) <=3D v; > +} > + > +_Bool fooq_setg (long long *ptr, long long v) > +{ > + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) > v; > +} > + > +_Bool fooq_setl (long long *ptr, long long v) > +{ > + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) < v; > +} > + > +_Bool fooq_sete(long long *ptr, long long v) > +{ > + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) =3D=3D v; > +} > + > +_Bool fooq_setne(long long *ptr, long long v) > +{ > + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) !=3D v; > +} > + > +_Bool fooq_setge(long long *ptr, long long v) > +{ > + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) >=3D v; > +} > + > +_Bool fooq_setle(long long *ptr, long long v) > +{ > + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) <=3D v; > +} > -- > 2.39.1.388.g2fc9e9ca3c > --=20 BR, Hongtao