From: Hongtao Liu <crazylht@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Haochen Jiang <haochen.jiang@intel.com>,
gcc-patches@gcc.gnu.org, ubizjak@gmail.com,
hongtao.liu@intel.com, "Zhang, Annita" <annita.zhang@intel.com>,
phoebe.wang@intel.com, x86-64-abi <x86-64-abi@googlegroups.com>,
llvm-dev <llvm-dev@lists.llvm.org>,
Craig Topper <craig.topper@gmail.com>,
Joseph Myers <joseph@codesourcery.com>
Subject: Re: Intel AVX10.1 Compiler Design and Support
Date: Wed, 9 Aug 2023 15:38:12 +0800 [thread overview]
Message-ID: <CAMZc-bzTanvRWab0Vm0yYBhFT3_cJ4nifsBkM0mkWri8A2qctA@mail.gmail.com> (raw)
In-Reply-To: <9061aee4-514d-8cc3-2792-cd1ef53d4f6b@suse.com>
On Wed, Aug 9, 2023 at 3:17 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 09.08.2023 04:14, Hongtao Liu wrote:
> > On Wed, Aug 9, 2023 at 9:21 AM Hongtao Liu <crazylht@gmail.com> wrote:
> >>
> >> On Wed, Aug 9, 2023 at 3:55 AM Joseph Myers <joseph@codesourcery.com> wrote:
> >>>
> >>> Do you have any comments on the interaction of AVX10 with the
> >>> micro-architecture levels defined in the ABI (and supported with
> >>> glibc-hwcaps directories in glibc)? Given that the levels are cumulative,
> >>> should we take it that any future levels will be ones supporting 512-bit
> >>> vector width for AVX10 (because x86-64-v4 requires the current AVX512F,
> >>> AVX512BW, AVX512CD, AVX512DQ and AVX512VL) - and so any future processors
> >>> that only support 256-bit vector width will be considered to match the
> >>> x86-64-v3 micro-architecture level but not any higher level?
> >> This is actually something we really want to discuss in the community,
> >> our proposal for x86-64-v5: AVX10.2-256(Implying AVX10.1-256) + APX.
> >> One big reason is Intel E-core will only support AVX10 256-bit, if we
> >> want to use x86-64-v5 accross server and client, it's better to
> >> 256-bit default.
>
> Aiui these ABI levels were intended to be incremental, i.e. higher versions
> would include everything earlier ones cover. Without such a guarantee, how
> would you propose compatibility checks to be implemented in a way
Are there many software implemenation based on this assumption?
At least in GCC, it's not a big problem, we can adjust code for the
new micro-architecture level.
> applicable both forwards and backwards? If a new level is wanted here, then
> I guess it could only be something like v3.5.
But if we use avx10.1 as v3.5, it's still not subset of
x86-64-v4(avx10.1 contains avx512fp16,avx512bf16 .etc which are not in
x86-64-v4), there will be still a diverge.
Then 256-bit of x86-64-v4 as v3.5? that's too weired to me.
Our main proposal is to make AVX10.x as new micro-architecture level
with 256-bit default, either v3.5 or v5 would be acceptable if it's
just the name.
>
> Jan
--
BR,
Hongtao
next prev parent reply other threads:[~2023-08-09 7:38 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-08 7:13 Haochen Jiang
2023-08-08 7:13 ` [PATCH 1/3] Initial support for AVX10.1 Haochen Jiang
2023-08-16 2:29 ` Hongtao Liu
2023-08-08 7:13 ` [PATCH 2/3] Emit a warning when disabling AVX512 with AVX10 enabled or disabling AVX10 with AVX512 enabled Haochen Jiang
2023-08-16 2:30 ` Hongtao Liu
2023-08-08 7:13 ` [PATCH 3/3] Emit a warning when AVX10 options conflict in vector width Haochen Jiang
2023-08-16 2:30 ` Hongtao Liu
2023-08-08 7:19 ` [PATCH 1/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins Haochen Jiang
2023-08-08 7:20 ` [PATCH 2/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 3/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 4/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 5/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 6/6] " Haochen Jiang
2023-08-16 2:36 ` Hongtao Liu
2023-08-08 7:42 ` Intel AVX10.1 Compiler Design and Support Jakub Jelinek
2023-08-08 8:14 ` Jiang, Haochen
2023-08-08 12:44 ` Richard Biener
2023-08-09 2:06 ` Hongtao Liu
2023-08-09 2:08 ` Hongtao Liu
2023-08-09 6:30 ` Jiang, Haochen
2023-08-08 19:55 ` Joseph Myers
2023-08-09 1:21 ` Hongtao Liu
2023-08-09 2:14 ` Hongtao Liu
2023-08-09 2:18 ` Hongtao Liu
2023-08-09 3:59 ` Wang, Phoebe
2023-08-09 20:43 ` Joseph Myers
2023-08-09 20:49 ` Jakub Jelinek
2023-08-10 12:36 ` Phoebe Wang
2023-08-10 12:45 ` Richard Biener
2023-08-10 13:12 ` Phoebe Wang
2023-08-10 13:30 ` Jan Beulich
2023-08-10 13:52 ` Richard Biener
2023-08-10 14:15 ` Jiang, Haochen
2023-08-10 15:08 ` Zhang, Annita
2023-08-10 15:18 ` Jakub Jelinek
2023-08-10 22:16 ` Joseph Myers
2023-08-09 4:01 ` Phoebe Wang
2023-08-09 5:37 ` Richard Biener
2023-08-09 6:24 ` Jiang, Haochen
2023-08-09 8:14 ` Florian Weimer
2023-08-09 8:24 ` Hongtao Liu
2023-08-09 7:17 ` Jan Beulich
2023-08-09 7:38 ` Hongtao Liu [this message]
2023-08-09 8:04 ` Jan Beulich
2023-08-09 9:15 ` Florian Weimer
2023-08-09 10:15 ` Hongtao Liu
2023-08-09 10:17 ` Zhang, Annita
2023-08-09 13:54 ` Michael Matz
2023-08-09 14:34 ` Zhang, Annita
2023-08-10 15:08 ` Jiang, Haochen
2023-08-10 16:00 ` Jakub Jelinek
2023-08-19 22:44 ` ZiNgA BuRgA
2023-08-20 5:44 ` Richard Biener
2023-08-21 1:19 ` Hongtao Liu
2023-08-21 7:36 ` Richard Biener
2023-08-21 8:09 ` Jakub Jelinek
2023-08-21 8:28 ` Hongtao Liu
2023-08-21 8:37 ` Jakub Jelinek
2023-08-21 8:46 ` Hongtao Liu
2023-08-21 9:34 ` Richard Biener
2023-08-21 9:36 ` Richard Biener
2023-08-21 9:50 ` Hongtao Liu
2023-08-21 9:26 ` ZiNgA BuRgA
2023-08-22 3:20 ` Jiang, Haochen
2023-08-22 7:36 ` Richard Biener
2023-08-22 8:34 ` Jakub Jelinek
2023-08-22 8:35 ` Richard Biener
2023-08-22 8:52 ` Jiang, Haochen
2023-08-22 9:23 ` Richard Biener
2023-08-22 13:02 ` Hongtao Liu
2023-08-22 13:16 ` Jakub Jelinek
2023-08-22 13:23 ` Richard Biener
2023-08-22 13:35 ` Hongtao Liu
2023-08-22 13:54 ` Jakub Jelinek
2023-08-22 14:35 ` Hongtao Liu
2023-08-22 15:01 ` Jakub Jelinek
2023-08-23 1:57 ` Jiang, Haochen
2023-08-23 2:19 ` Hongtao Liu
2023-08-23 6:47 ` Jiang, Haochen
2023-08-23 8:16 ` Jakub Jelinek
2023-08-23 8:27 ` Hongtao Liu
2023-08-23 7:32 ` Richard Biener
2023-08-23 8:03 ` Jiang, Haochen
2023-08-23 8:31 ` Jakub Jelinek
2023-08-23 8:47 ` Hongtao Liu
2023-08-23 8:24 ` Hongtao Liu
2023-08-22 14:39 ` Hongtao Liu
2023-08-21 7:49 ` ZiNgA BuRgA
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