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References: <20221014075445.7938-1-haochen.jiang@intel.com>
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From: Hongtao Liu <crazylht@gmail.com>
Date: Tue, 25 Oct 2022 13:23:26 +0800
Message-ID: <CAMZc-bzUgMrwMExSPx8nL8aeys2aecxdjgKqGLVP_zeWOCW3Gg@mail.gmail.com>
Subject: Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT
To: "Kong, Lingling" <lingling.kong@intel.com>
Cc: "Liu, Hongtao" <hongtao.liu@intel.com>, 
	"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>, "Jiang, Haochen" <haochen.jiang@intel.com>
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On Mon, Oct 24, 2022 at 2:20 PM Kong, Lingling <lingling.kong@intel.com> wrote:
>
> > From: Gcc-patches <gcc-patches-bounces+lingling.kong=intel.com@gcc.gnu.org>
> > On Behalf Of Hongtao Liu via Gcc-patches
> > Sent: Monday, October 17, 2022 1:47 PM
> > To: Jiang, Haochen <haochen.jiang@intel.com>
> > Cc: Liu, Hongtao <hongtao.liu@intel.com>; gcc-patches@gcc.gnu.org
> > Subject: Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT
> >
> > On Fri, Oct 14, 2022 at 3:58 PM Haochen Jiang via Gcc-patches
> > <gcc-patches@gcc.gnu.org> wrote:
> > >
> > > From: Kong Lingling <lingling.kong@intel.com>
> > > +(define_insn "vbcstne<vbcstnetype>2ps_<mode>"
> > > +  [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
> > > +    (vec_duplicate:VF1_128_256
> > > +     (unspec:SF
> > > +      [(match_operand:HI 1 "memory_operand" "m")]
> > > +      VBCSTNE)))]
> > > +  "TARGET_AVXNECONVERT"
> > > +  "vbcstne<vbcstnetype>2ps\t{%1, %0|%0, %1}"
> > > +  [(set_attr "prefix" "vex")
> > > +  (set_attr "mode" "<sseinsnmode>")])
> > Since jakub has support bf16 software emulation, can we rewrite it
> > with general rtl ir without unspec?
> > Like (float_extend:SF (match_operand:BF "memory_operand" "m")
> > > +
> > > +(define_int_iterator VCVTNEBF16
> > > +  [UNSPEC_VCVTNEEBF16SF
> > > +   UNSPEC_VCVTNEOBF16SF])
> > > +
> > > +(define_int_attr vcvtnebf16type
> > > +  [(UNSPEC_VCVTNEEBF16SF "ebf16")
> > > +   (UNSPEC_VCVTNEOBF16SF "obf16")])
> > > +(define_insn "vcvtne<vcvtnebf16type>2ps_<mode>"
> > > +  [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
> > > +    (unspec:VF1_128_256
> > > +      [(match_operand:<sf_bfloat16> 1 "memory_operand" "m")]
> > > +     VCVTNEBF16))]
> > > +  "TARGET_AVXNECONVERT"
> > > +  "vcvtne<vcvtnebf16type>2ps\t{%1, %0|%0, %1}"
> > > +  [(set_attr "prefix" "vex")
> > > +   (set_attr "mode" "<sseinsnmode>")])
> > Similar for this one and all those patterns below.
>
> That's great! Thanks for the review!
> Now rewrite it without unspec and use float_extend for new define_insn.
Ok.
>
> Thanks
> Lingling
>
>


-- 
BR,
Hongtao