From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb2d.google.com (mail-yb1-xb2d.google.com [IPv6:2607:f8b0:4864:20::b2d]) by sourceware.org (Postfix) with ESMTPS id 493DC3858D32 for ; Mon, 5 Sep 2022 02:48:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 493DC3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yb1-xb2d.google.com with SMTP id 130so5375061ybz.9 for ; Sun, 04 Sep 2022 19:48:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=rCzLmVDalZ0D4YAwMkHTgkC27IKjII8tkgNOGSmambo=; b=Z7t0trVIMGvY9LCnan2QuZQpO7kegG3g+EdlQsrD5zCqF7uc70/ILRTc9akboS6rlq M6Fpi/6hA+FSm+MtHK5j5OAc8Q8dL+EdHuk8BF+JGdTicmczy0/TeSoFqEzYuQXUjmLR v/5o19n6duveQUg4wG0C+uEWVUjWG6SWi65pqyCCxv9fTak8r7tUPph+yAJUuVjxidL9 9Fei/dzEewYP0xvFXeynIqghiA03B+KKSnDAGNUnVbi28Uz89QtBetjkDGdjb0bbmaK1 W37OlZrVXTGlYx4zsDetK6SMdpZKzf5EAywd8KK/19vYGPsN85qI3TRzi9sfZBa1S45Z pakw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=rCzLmVDalZ0D4YAwMkHTgkC27IKjII8tkgNOGSmambo=; b=kTmaCeXbMQVWURM+gHUbmmh90NDTd+B2kTUgt+HlVmqO6GuOaQZttDmq1XJ86gms2/ EygbyyeZSPxPpyDcj4usoZcnCdCyWzLWH6Em8g3/9TlUZDsgSxYKDPKZPhIdYNlAHb08 5oASMo6COaF5UuajdmyFw1Ouv3NpZBDjw3PZ8sT7C0aymq9qhxF0HnmyxViYBHgt/q5J ua0ArhSSS73mhnRFb8pajTlIiJ2NIEwd1v67uCLmInx84pSIwS/SfKesSYSpZYxAogc1 w3AjNwA9KaGqw2JiN/S0i/qW+P25tfxRknZLNwXv3ODSZ3xkv7YXPhAu9IsvQQCdOOXH 0hRg== X-Gm-Message-State: ACgBeo3QD+ztORtYQOBa2NNIzrzZa0Ry55h1ETXuAwU/yLkmwdZngayW bCTMwSkcueE20iOUa/NklAO1Cf+7S6frnCjy5gI= X-Google-Smtp-Source: AA6agR5USmvQtp+exF/Ins8RGtbclrKLwMOrERWKfIEt0z40XvySPpjAKuPFsn+HxLjUJ6non1NQgIwBuPeh7n4ilnY= X-Received: by 2002:a25:d686:0:b0:6a8:e9a8:54f7 with SMTP id n128-20020a25d686000000b006a8e9a854f7mr5036064ybg.611.1662346095502; Sun, 04 Sep 2022 19:48:15 -0700 (PDT) MIME-Version: 1.0 References: <20220905024318.1259282-1-hongtao.liu@intel.com> In-Reply-To: <20220905024318.1259282-1-hongtao.liu@intel.com> From: Hongtao Liu Date: Mon, 5 Sep 2022 10:48:04 +0800 Message-ID: Subject: Re: [PATCH] Fix _mm512_cvt_roundps_ph to generate sae instruction. To: liuhongt Cc: gcc-patches@gcc.gnu.org, hjl.tools@gmail.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Sep 5, 2022 at 10:44 AM liuhongt wrote: > > zmm-version vcvtps2ph is special, it encodes {sae} in evex, but put > round control in the imm. For intrinsic _mm512_cvt_roundps_ph (a, > imm), imm contains both {sae} and round control, we need to separate > it in the assembly output since vcvtps2ph will ignore imm[3:7]. > > Corresponding llvm patch. Forgot to paste it: https://reviews.llvm.org/D132641 > Intrinsic guide will also be updated in the next version. > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} > Ready to install. > > gcc/ChangeLog: > > * config/i386/i386-builtin.def (IX86_BUILTIN_CVTPS2PH512): > Map to CODE_FOR_avx512f_vcvtps2ph512_mask_sae. > * config/i386/sse.md (avx512f_vcvtps2ph512): Extend to .. > (avx512f_vcvtps2ph512): .. this. > (avx512f_vcvtps2ph512_mask_sae): New expander > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/avx512f-vcvtps2ph-sae.c: New test. > --- > gcc/config/i386/i386-builtin.def | 2 +- > gcc/config/i386/sse.md | 30 +++++++++++++++++-- > .../gcc.target/i386/avx512f-vcvtps2ph-sae.c | 18 +++++++++++ > 3 files changed, 47 insertions(+), 3 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c > > diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def > index f9c7abde2cf..dea52a28d28 100644 > --- a/gcc/config/i386/i386-builtin.def > +++ b/gcc/config/i386/i386-builtin.def > @@ -1351,7 +1351,7 @@ BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia > BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI) > BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI) > BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI) > -BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI) > +BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_vcvtps2ph512_mask_sae, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI) > BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI) > BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT) > BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI) > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 259048481b6..a35b0d368e6 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -26902,14 +26902,40 @@ (define_insn "*vcvtps2ph256" > (set_attr "btver2_decode" "vector") > (set_attr "mode" "V8SF")]) > > -(define_insn "avx512f_vcvtps2ph512" > +;; vcvtps2ph is special, it encodes {sae} in evex, but round control in the imm > +;; For intrinsic _mm512_cvt_roundps_ph (a, imm), imm contains both {sae} > +;; and round control, we need to separate it in the assembly output. > +;; op2 in avx512f_vcvtps2ph512_mask_sae contains both sae and round control. > +(define_expand "avx512f_vcvtps2ph512_mask_sae" > + [(set (match_operand:V16HI 0 "register_operand" "=v") > + (vec_merge:V16HI > + (unspec:V16HI > + [(match_operand:V16SF 1 "register_operand" "v") > + (match_operand:SI 2 "const_0_to_255_operand")] > + UNSPEC_VCVTPS2PH) > + (match_operand:V16HI 3 "nonimm_or_0_operand") > + (match_operand:HI 4 "register_operand")))] > + "TARGET_AVX512F" > +{ > + int round = INTVAL (operands[2]); > + /* Separate {sae} from rounding control imm, > + imm[3:7] will be ignored by the instruction. */ > + if (round & 8) > + { > + emit_insn (gen_avx512f_vcvtps2ph512_mask_round (operands[0], operands[1], > + operands[2], operands[3], operands[4], GEN_INT (8))); > + DONE; > + } > +}) > + > +(define_insn "avx512f_vcvtps2ph512" > [(set (match_operand:V16HI 0 "register_operand" "=v") > (unspec:V16HI > [(match_operand:V16SF 1 "register_operand" "v") > (match_operand:SI 2 "const_0_to_255_operand")] > UNSPEC_VCVTPS2PH))] > "TARGET_AVX512F" > - "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" > + "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" > [(set_attr "type" "ssecvt") > (set_attr "prefix" "evex") > (set_attr "mode" "V16SF")]) > diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c b/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c > new file mode 100644 > index 00000000000..e0714d437d0 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mavx512f" } */ > +/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > + > +#include > + > +volatile __m512 x; > +volatile __m256i y; > + > +void extern > +avx512f_test (void) > +{ > + y = _mm512_cvtps_ph (x, 8); > + y = _mm512_maskz_cvtps_ph (4, x, 9); > + y = _mm512_mask_cvtps_ph (y, 2, x, 10); > +} > -- > 2.27.0 > -- BR, Hongtao